Reviewed-by: Mike Leach mike.leach@linaro.org

On Fri, 11 Sep 2020 at 09:41, Suzuki K Poulose suzuki.poulose@arm.com wrote:

We are about to introduce support for sysreg access to ETMv4.4+ component. Since there are generic routines that access the registers (e.g, CS_LOCK/UNLOCK , claim/disclaim operations, timeout) and in order to preserve the logic of these operations at a single place we introduce an abstraction layer for the accesses to a given device.

Cc: Mathieu Poirier mathieu.poirier@linaro.org Cc: Mike Leach mike.leach@linaro.org Signed-off-by: Suzuki K Poulose suzuki.poulose@arm.com

---

drivers/hwtracing/coresight/coresight-catu.c | 1 + drivers/hwtracing/coresight/coresight-cti.c | 1 + drivers/hwtracing/coresight/coresight-etb10.c | 1 + drivers/hwtracing/coresight/coresight-etm3x.c | 1 + drivers/hwtracing/coresight/coresight-etm4x.c | 1 + .../hwtracing/coresight/coresight-funnel.c | 1 + .../coresight/coresight-replicator.c | 1 + drivers/hwtracing/coresight/coresight-stm.c | 1 + drivers/hwtracing/coresight/coresight-tmc.c | 1 + drivers/hwtracing/coresight/coresight-tpiu.c | 1 + drivers/hwtracing/coresight/coresight.c | 49 +++++ include/linux/coresight.h | 197 ++++++++++++++++++ 12 files changed, 256 insertions(+)

diff --git a/drivers/hwtracing/coresight/coresight-catu.c b/drivers/hwtracing/coresight/coresight-catu.c index 1801804a7762..90da0b842717 100644 --- a/drivers/hwtracing/coresight/coresight-catu.c +++ b/drivers/hwtracing/coresight/coresight-catu.c @@ -551,6 +551,7 @@ static int catu_probe(struct amba_device *adev, const struct amba_id *id) dev->platform_data = pdata;

    drvdata->base = base;

•   catu_desc.access = CSDEV_ACCESS_IOMEM(base);
    catu_desc.pdata = pdata;
    catu_desc.dev = dev;
    catu_desc.groups = catu_groups;
  

diff --git a/drivers/hwtracing/coresight/coresight-cti.c b/drivers/hwtracing/coresight/coresight-cti.c index 47f3c9abae30..e13e24e4a858 100644 --- a/drivers/hwtracing/coresight/coresight-cti.c +++ b/drivers/hwtracing/coresight/coresight-cti.c @@ -849,6 +849,7 @@ static int cti_probe(struct amba_device *adev, const struct amba_id *id) return PTR_ERR(base);

    drvdata->base = base;

•   cti_desc.access = CSDEV_ACCESS_IOMEM(base);
  
    dev_set_drvdata(dev, drvdata);
  
  

diff --git a/drivers/hwtracing/coresight/coresight-etb10.c b/drivers/hwtracing/coresight/coresight-etb10.c index 03e3f2590191..42fe174a68f0 100644 --- a/drivers/hwtracing/coresight/coresight-etb10.c +++ b/drivers/hwtracing/coresight/coresight-etb10.c @@ -755,6 +755,7 @@ static int etb_probe(struct amba_device *adev, const struct amba_id *id) return PTR_ERR(base);

    drvdata->base = base;

•   desc.access = CSDEV_ACCESS_IOMEM(base);
  
    spin_lock_init(&drvdata->spinlock);
  
  

diff --git a/drivers/hwtracing/coresight/coresight-etm3x.c b/drivers/hwtracing/coresight/coresight-etm3x.c index bf22dcfd3327..e3724d8adecb 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x.c +++ b/drivers/hwtracing/coresight/coresight-etm3x.c @@ -805,6 +805,7 @@ static int etm_probe(struct amba_device *adev, const struct amba_id *id) return PTR_ERR(base);

    drvdata->base = base;

•   desc.access = CSDEV_ACCESS_IOMEM(base);
  
    spin_lock_init(&drvdata->spinlock);
  
  

diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index 00c9f0bb8b1a..466e6f304751 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -1488,6 +1488,7 @@ static int etm4_probe(struct amba_device *adev, const struct amba_id *id) return PTR_ERR(base);

    drvdata->base = base;

•   desc.access = CSDEV_ACCESS_IOMEM(base);
  
    spin_lock_init(&drvdata->spinlock);
  
  

diff --git a/drivers/hwtracing/coresight/coresight-funnel.c b/drivers/hwtracing/coresight/coresight-funnel.c index 900690a9f7f0..e8e233cbc130 100644 --- a/drivers/hwtracing/coresight/coresight-funnel.c +++ b/drivers/hwtracing/coresight/coresight-funnel.c @@ -242,6 +242,7 @@ static int funnel_probe(struct device *dev, struct resource *res) } drvdata->base = base; desc.groups = coresight_funnel_groups;

•           desc.access = CSDEV_ACCESS_IOMEM(base);
    }
  
    dev_set_drvdata(dev, drvdata);
  

diff --git a/drivers/hwtracing/coresight/coresight-replicator.c b/drivers/hwtracing/coresight/coresight-replicator.c index 78acf29c49ca..8ba9cbe1d108 100644 --- a/drivers/hwtracing/coresight/coresight-replicator.c +++ b/drivers/hwtracing/coresight/coresight-replicator.c @@ -254,6 +254,7 @@ static int replicator_probe(struct device *dev, struct resource *res) } drvdata->base = base; desc.groups = replicator_groups;

•           desc.access = CSDEV_ACCESS_IOMEM(base);
    }
  
    if (fwnode_property_present(dev_fwnode(dev),
  

diff --git a/drivers/hwtracing/coresight/coresight-stm.c b/drivers/hwtracing/coresight/coresight-stm.c index 2ba819a47cf6..fbf86f31f2ab 100644 --- a/drivers/hwtracing/coresight/coresight-stm.c +++ b/drivers/hwtracing/coresight/coresight-stm.c @@ -884,6 +884,7 @@ static int stm_probe(struct amba_device *adev, const struct amba_id *id) if (IS_ERR(base)) return PTR_ERR(base); drvdata->base = base;

•   desc.access = CSDEV_ACCESS_IOMEM(base);
  
    ret = stm_get_stimulus_area(dev, &ch_res);
    if (ret)
  

diff --git a/drivers/hwtracing/coresight/coresight-tmc.c b/drivers/hwtracing/coresight/coresight-tmc.c index 7040d583bed9..5711e55c310c 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.c +++ b/drivers/hwtracing/coresight/coresight-tmc.c @@ -458,6 +458,7 @@ static int tmc_probe(struct amba_device *adev, const struct amba_id *id) }

    drvdata->base = base;

•   desc.access = CSDEV_ACCESS_IOMEM(base);
  
    spin_lock_init(&drvdata->spinlock);
  
  

diff --git a/drivers/hwtracing/coresight/coresight-tpiu.c b/drivers/hwtracing/coresight/coresight-tpiu.c index f8583e4032a6..4eb3f50618b6 100644 --- a/drivers/hwtracing/coresight/coresight-tpiu.c +++ b/drivers/hwtracing/coresight/coresight-tpiu.c @@ -149,6 +149,7 @@ static int tpiu_probe(struct amba_device *adev, const struct amba_id *id) return PTR_ERR(base);

    drvdata->base = base;

•   desc.access = CSDEV_ACCESS_IOMEM(base);
  
    /* Disable tpiu to support older devices */
    tpiu_disable_hw(drvdata);
  

diff --git a/drivers/hwtracing/coresight/coresight.c b/drivers/hwtracing/coresight/coresight.c index e9c90f2de34a..38e9c03ab754 100644 --- a/drivers/hwtracing/coresight/coresight.c +++ b/drivers/hwtracing/coresight/coresight.c @@ -1387,6 +1387,54 @@ static int __init coresight_init(void) } postcore_initcall(coresight_init);

+u32 coresight_relaxed_read32(struct coresight_device *csdev, u32 offset) +{

•   return csdev_access_relaxed_read32(&csdev->access, offset);
  

+}

+u32 coresight_read32(struct coresight_device *csdev, u32 offset) +{

•   return csdev_access_read32(&csdev->access, offset);
  

+}

+void coresight_relaxed_write32(struct coresight_device *csdev,

•                          u32 val,
  

•                          u32 offset)
  

+{

•   csdev_access_relaxed_write32(&csdev->access, val, offset);
  

+}

+void coresight_write32(struct coresight_device *csdev, u32 val, u32 offset) +{

•   csdev_access_write32(&csdev->access, val, offset);
  

+}

+u64 coresight_relaxed_read64(struct coresight_device *csdev, u32 offset) +{

•   return csdev_access_relaxed_read64(&csdev->access, offset);
  

+}

+u64 coresight_read64(struct coresight_device *csdev, u32 offset) +{

•   return csdev_access_read64(&csdev->access, offset);
  

+}

+void coresight_relaxed_write64(struct coresight_device *csdev,

•                          u64 val,
  

•                          u32 offset)
  

+{

•   csdev_access_relaxed_write64(&csdev->access, val, offset);
  

+}

+void coresight_write64(struct coresight_device *csdev, u64 val, u32 offset) +{

•   csdev_access_write64(&csdev->access, val, offset);
  

+}

/*

• coresight_release_platform_data: Release references to the devices connected
• to the output port of this device.

@@ -1451,6 +1499,7 @@ struct coresight_device *coresight_register(struct coresight_desc *desc) csdev->type = desc->type; csdev->subtype = desc->subtype; csdev->ops = desc->ops;

•   csdev->access = desc->access;
    csdev->orphan = false;
  
    csdev->dev.type = &coresight_dev_type[desc->type];
  

diff --git a/include/linux/coresight.h b/include/linux/coresight.h index 58fffdecdbfd..1377240275d8 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -7,6 +7,7 @@ #define _LINUX_CORESIGHT_H

#include <linux/device.h> +#include <linux/io.h> #include <linux/perf_event.h> #include <linux/sched.h>

@@ -114,6 +115,38 @@ struct coresight_platform_data { struct coresight_connection *conns; };

+/**

• • struct csdev_access - Abstraction of a CoreSight device access.
• • @io_mem : True if the device has memory mapped I/O
• • @base : When io_mem == true, base address of the component
• • @read : Read from the given "offset" of the given instance.
• • @write : Write "val" to the given "offset".
• */

+struct csdev_access {

•   bool io_mem;
  

•   union {
  

•           void __iomem *base;
  

•           struct {
  

•                   u64 (*read)(struct csdev_access *csa,
  

•                               u32 offset,
  

•                               bool relaxed,
  

•                               bool _64bit);
  

•                   void (*write)(struct csdev_access *csa,
  

•                                 u64 val,
  

•                                 u32 offset,
  

•                                 bool relaxed,
  

•                                 bool _64bit);
  

•           };
  

•   };
  

+};

+#define CSDEV_ACCESS_IOMEM(addr) \

•   (struct csdev_access)   {               \
  

•           .io_mem         = true,         \
  

•           .base           = addr,         \
  

•   }
  

/**

• struct coresight_desc - description of a component required from drivers
• @type: as defined by @coresight_dev_type.

@@ -125,6 +158,7 @@ struct coresight_platform_data {

• @groups: operations specific to this component. These will end up

•         in the component's sysfs sub-directory.
  

• @name: name for the coresight device, also shown under sysfs.

• • @access: Describe access to the device
  */

struct coresight_desc { enum coresight_dev_type type; @@ -134,6 +168,7 @@ struct coresight_desc { struct device *dev; const struct attribute_group **groups; const char *name;

•   struct csdev_access access;
  

};

/** @@ -186,6 +221,7 @@ struct coresight_sysfs_link {

• @def_sink: cached reference to default sink found for this device.
• @ect_dev: Associated cross trigger device. Not part of the trace data

•         path or connections.
  

• • @access: Device i/o access abstraction for this device.
  • @nr_links: number of sysfs links created to other components from this

  •         device. These will appear in the "connections" group.
    

  • @has_conns_grp: Have added a "connections" group for sysfs links.

@@ -205,6 +241,7 @@ struct coresight_device { struct coresight_device *def_sink; /* cross trigger handling */ struct coresight_device *ect_dev;

•   struct csdev_access access;
    /* sysfs links between components */
    int nr_links;
    bool has_conns_grp;
  

@@ -324,6 +361,107 @@ struct coresight_ops { const struct coresight_ops_ect *ect_ops; };

+static inline u32 csdev_access_relaxed_read32(struct csdev_access *csa,

•                                         u32 offset)
  

+{

•   if (likely(csa->io_mem))
  

•           return readl_relaxed(csa->base + offset);
  

•   return csa->read(csa, offset, true, false);
  

+}

+static inline u32 csdev_access_read32(struct csdev_access *csa, u32 offset) +{

•   if (likely(csa->io_mem))
  

•           return readl(csa->base + offset);
  

•   return csa->read(csa, offset, false, false);
  

+}

+static inline void csdev_access_relaxed_write32(struct csdev_access *csa,

•                                           u32 val,
  

•                                           u32 offset)
  

+{

•   if (likely(csa->io_mem))
  

•           writel_relaxed(val, csa->base + offset);
  

•   else
  

•           csa->write(csa, val, offset, true, false);
  

+}

+static inline void csdev_access_write32(struct csdev_access *csa, u32 val, u32 offset) +{

•   if (likely(csa->io_mem))
  

•           writel(val, csa->base + offset);
  

•   else
  

•           csa->write(csa, val, offset, false, false);
  

+}

+#ifdef CONFIG_64BIT

+static inline u64 csdev_access_relaxed_read64(struct csdev_access *csa,

•                                      u32 offset)
  

+{

•   if (likely(csa->io_mem))
  

•           return readq_relaxed(csa->base + offset);
  

•   return csa->read(csa, offset, true, true);
  

+}

+static inline u64 csdev_access_read64(struct csdev_access *csa, u32 offset) +{

•   if (likely(csa->io_mem))
  

•           return readq(csa->base + offset);
  

•   return csa->read(csa, offset, false, true);
  

+}

+static inline void csdev_access_relaxed_write64(struct csdev_access *csa,

•                                           u64 val,
  

•                                           u32 offset)
  

+{

•   if (likely(csa->io_mem))
  

•           writeq_relaxed(val, csa->base + offset);
  

•   else
  

•           csa->write(csa, val, offset, true, true);
  

+}

+static inline void csdev_access_write64(struct csdev_access *csa, u64 val, u32 offset) +{

•   if (likely(csa->io_mem))
  

•           writeq(val, csa->base + offset);
  

•   else
  

•           csa->write(csa, val, offset, false, true);
  

+}

+#else

+static inline u64 csdev_access_relaxed_read64(struct csdev_access *csa,

•                                      u32 offset)
  

+{

•   WARN_ON(1);
  

•   return 0;
  

+}

+static inline u64 csdev_access_read64(struct csdev_access *csa, u32 offset) +{

•   WARN_ON(1);
  

•   return 0;
  

+}

+static inline void csdev_access_relaxed_write64(struct csdev_access *csa,

•                                           u64 val,
  

•                                           u32 offset)
  

+{

•   WARN_ON(1);
  

+}

+static inline void csdev_access_write64(struct csdev_access *csa, u64 val, u32 offset) +{

•   WARN_ON(1);
  

+} +#endif

#ifdef CONFIG_CORESIGHT extern struct coresight_device * coresight_register(struct coresight_desc *desc); @@ -342,6 +480,20 @@ extern char *coresight_alloc_device_name(struct coresight_dev_list *devs, struct device *dev);

extern bool coresight_loses_context_with_cpu(struct device *dev);

+u32 coresight_relaxed_read32(struct coresight_device *csdev, u32 offset); +u32 coresight_read32(struct coresight_device *csdev, u32 offset); +void coresight_write32(struct coresight_device *csdev, u32 val, u32 offset); +void coresight_relaxed_write32(struct coresight_device *csdev,

•                          u32 val,
  

•                          u32 offset);
  

+u64 coresight_relaxed_read64(struct coresight_device *csdev, u32 offset); +u64 coresight_read64(struct coresight_device *csdev, u32 offset); +void coresight_relaxed_write64(struct coresight_device *csdev,

•                          u64 val, u32 offset);
  

+void coresight_write64(struct coresight_device *csdev, u64 val, u32 offset);

#else static inline struct coresight_device * coresight_register(struct coresight_desc *desc) { return NULL; } @@ -368,6 +520,51 @@ static inline bool coresight_loses_context_with_cpu(struct device *dev) { return false; }

+static inline u32 coresight_relaxed_read32(struct coresight_device *csdev, u32 offset) +{

•   WARN_ON_ONCE(1);
  

•   return 0;
  

+}

+static inline u32 coresight_read32(struct coresight_device *csdev, u32 offset) +{

•   WARN_ON_ONCE(1);
  

•   return 0;
  

+}

+static inline void coresight_write32(struct coresight_device *csdev, u32 val, u32 offset) +{ +}

+static inline void coresight_relaxed_write32(struct coresight_device *csdev,

•                                         u32 val, u32 offset);
  

+{ +}

+static inline u64 coresight_relaxed_read64(struct coresight_device *csdev,

•                                      u32 offset)
  

+{

•   WARN_ON_ONCE(1);
  

•   return 0;
  

+}

+static inline u64 coresight_read64(struct coresight_device *csdev, u32 offset) +{

•   WARN_ON_ONCE(1);
  

•   return 0;
  

+}

+static inline void coresight_relaxed_write64(struct coresight_device *csdev,

•                                        u64 val,
  

•                                        u32 offset)
  

+{ +}

+static inline void coresight_write64(struct coresight_device *csdev, u64 val, u32 offset) +{ +}

#endif

extern int coresight_get_cpu(struct device *dev);

2.24.1

-- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK

Reviewed-by: Mike Leach mike.leach@linaro.org

On Fri, 11 Sep 2020 at 09:41, Suzuki K Poulose suzuki.poulose@arm.com wrote:

Prepare the TPIU driver to make use of the CoreSight device access abstraction layer. The driver touches the device even before the coresight device is registered. Thus we could be accessing the devices without a csdev. As we are about to use the abstraction layer for accessing the device, pass in the access directly to avoid having to deal with the un-initialised csdev.

Cc: Mathieu Poirier mathieu.poirier@linaro.org Cc: Mike Leach mike.leach@linaro.org Signed-off-by: Suzuki K Poulose suzuki.poulose@arm.com

---

drivers/hwtracing/coresight/coresight-tpiu.c | 30 +++++++++----------- 1 file changed, 13 insertions(+), 17 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-tpiu.c b/drivers/hwtracing/coresight/coresight-tpiu.c index 4eb3f50618b6..cc7d7ed474f5 100644 --- a/drivers/hwtracing/coresight/coresight-tpiu.c +++ b/drivers/hwtracing/coresight/coresight-tpiu.c @@ -60,49 +60,45 @@ struct tpiu_drvdata { struct coresight_device *csdev; };

-static void tpiu_enable_hw(struct tpiu_drvdata *drvdata) +static void tpiu_enable_hw(struct csdev_access *csa) {

•   CS_UNLOCK(drvdata->base);
  

•   CS_UNLOCK(csa->base);
  
    /* TODO: fill this up */
  
  

•   CS_LOCK(drvdata->base);
  

•   CS_LOCK(csa->base);
  

}

static int tpiu_enable(struct coresight_device *csdev, u32 mode, void *__unused) {

•   struct tpiu_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
  

•   tpiu_enable_hw(drvdata);
  

•   tpiu_enable_hw(&csdev->access);
    atomic_inc(csdev->refcnt);
    dev_dbg(&csdev->dev, "TPIU enabled\n");
    return 0;
  

}

-static void tpiu_disable_hw(struct tpiu_drvdata *drvdata) +static void tpiu_disable_hw(struct csdev_access *csa) {

•   CS_UNLOCK(drvdata->base);
  

•   CS_UNLOCK(csa->base);
  
    /* Clear formatter and stop on flush */
  

•   writel_relaxed(FFCR_STOP_FI, drvdata->base + TPIU_FFCR);
  

•   csdev_access_relaxed_write32(csa, FFCR_STOP_FI, TPIU_FFCR);
    /* Generate manual flush */
  

•   writel_relaxed(FFCR_STOP_FI | FFCR_FON_MAN, drvdata->base + TPIU_FFCR);
  

•   csdev_access_relaxed_write32(csa, FFCR_STOP_FI | FFCR_FON_MAN, TPIU_FFCR);
    /* Wait for flush to complete */
  

•   coresight_timeout(drvdata->base, TPIU_FFCR, FFCR_FON_MAN_BIT, 0);
  

•   coresight_timeout(csa->base, TPIU_FFCR, FFCR_FON_MAN_BIT, 0);
    /* Wait for formatter to stop */
  

•   coresight_timeout(drvdata->base, TPIU_FFSR, FFSR_FT_STOPPED_BIT, 1);
  

•   coresight_timeout(csa->base, TPIU_FFSR, FFSR_FT_STOPPED_BIT, 1);
  
  

•   CS_LOCK(drvdata->base);
  

•   CS_LOCK(csa->base);
  

}

static int tpiu_disable(struct coresight_device *csdev) {

•   struct tpiu_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
  

•   if (atomic_dec_return(csdev->refcnt))
            return -EBUSY;
  
  

•   tpiu_disable_hw(drvdata);
  

•   tpiu_disable_hw(&csdev->access);
  
    dev_dbg(&csdev->dev, "TPIU disabled\n");
    return 0;
  

@@ -152,7 +148,7 @@ static int tpiu_probe(struct amba_device *adev, const struct amba_id *id) desc.access = CSDEV_ACCESS_IOMEM(base);

    /* Disable tpiu to support older devices */

•   tpiu_disable_hw(drvdata);
  

•   tpiu_disable_hw(&desc.access);
  
    pdata = coresight_get_platform_data(dev);
    if (IS_ERR(pdata))
  

-- 2.24.1

-- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK

Reviewed-by: Mike Leach mike.leach@linaro.org

On Fri, 11 Sep 2020 at 09:41, Suzuki K Poulose suzuki.poulose@arm.com wrote:

Convert the generic routines to use the new access abstraction layer gradually, starting with coresigth_timeout.

Cc: Mike Leach mike.leach@linaro.org Reviewed-by: Mathieu Poirier mathieu.poirier@linaro.org Signed-off-by: Suzuki K Poulose suzuki.poulose@arm.com

---

drivers/hwtracing/coresight/coresight-catu.c | 5 ++-- drivers/hwtracing/coresight/coresight-etb10.c | 5 ++-- drivers/hwtracing/coresight/coresight-etm4x.c | 30 ++++++++++++------- drivers/hwtracing/coresight/coresight-stm.c | 3 +- drivers/hwtracing/coresight/coresight-tmc.c | 15 ++++++---- drivers/hwtracing/coresight/coresight-tpiu.c | 4 +-- drivers/hwtracing/coresight/coresight.c | 15 ++++++---- include/linux/coresight.h | 17 ++++++++--- 8 files changed, 61 insertions(+), 33 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-catu.c b/drivers/hwtracing/coresight/coresight-catu.c index 90da0b842717..15e63e52ff23 100644 --- a/drivers/hwtracing/coresight/coresight-catu.c +++ b/drivers/hwtracing/coresight/coresight-catu.c @@ -401,8 +401,9 @@ static const struct attribute_group *catu_groups[] = {

static inline int catu_wait_for_ready(struct catu_drvdata *drvdata) {

•   return coresight_timeout(drvdata->base,
  

•                            CATU_STATUS, CATU_STATUS_READY, 1);
  

•   struct csdev_access *csa = &drvdata->csdev->access;
  

•   return coresight_timeout(csa, CATU_STATUS, CATU_STATUS_READY, 1);
  

}

static int catu_enable_hw(struct catu_drvdata *drvdata, void *data) diff --git a/drivers/hwtracing/coresight/coresight-etb10.c b/drivers/hwtracing/coresight/coresight-etb10.c index 42fe174a68f0..2786d02dd23b 100644 --- a/drivers/hwtracing/coresight/coresight-etb10.c +++ b/drivers/hwtracing/coresight/coresight-etb10.c @@ -251,6 +251,7 @@ static void __etb_disable_hw(struct etb_drvdata *drvdata) { u32 ffcr; struct device *dev = &drvdata->csdev->dev;

•   struct csdev_access *csa = &drvdata->csdev->access;
  
    CS_UNLOCK(drvdata->base);
  
  

@@ -262,7 +263,7 @@ static void __etb_disable_hw(struct etb_drvdata *drvdata) ffcr |= ETB_FFCR_FON_MAN; writel_relaxed(ffcr, drvdata->base + ETB_FFCR);

•   if (coresight_timeout(drvdata->base, ETB_FFCR, ETB_FFCR_BIT, 0)) {
  

•   if (coresight_timeout(csa, ETB_FFCR, ETB_FFCR_BIT, 0)) {
            dev_err(dev,
            "timeout while waiting for completion of Manual Flush\n");
    }
  

@@ -270,7 +271,7 @@ static void __etb_disable_hw(struct etb_drvdata *drvdata) /* disable trace capture */ writel_relaxed(0x0, drvdata->base + ETB_CTL_REG);

•   if (coresight_timeout(drvdata->base, ETB_FFSR, ETB_FFSR_BIT, 1)) {
  

•   if (coresight_timeout(csa, ETB_FFSR, ETB_FFSR_BIT, 1)) {
            dev_err(dev,
                    "timeout while waiting for Formatter to Stop\n");
    }
  

diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index 466e6f304751..973fb0fd4826 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -107,7 +107,9 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) { int i, rc; struct etmv4_config *config = &drvdata->config;

•   struct device *etm_dev = &drvdata->csdev->dev;
  

•   struct coresight_device *csdev = drvdata->csdev;
  

•   struct device *etm_dev = &csdev->dev;
  

•   struct csdev_access *csa = &csdev->access;
  
    CS_UNLOCK(drvdata->base);
  
  

@@ -121,7 +123,7 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) writel_relaxed(0, drvdata->base + TRCPRGCTLR);

    /* wait for TRCSTATR.IDLE to go up */

•   if (coresight_timeout(drvdata->base, TRCSTATR, TRCSTATR_IDLE_BIT, 1))
  

•   if (coresight_timeout(csa, TRCSTATR, TRCSTATR_IDLE_BIT, 1))
            dev_err(etm_dev,
                    "timeout while waiting for Idle Trace Status\n");
  
  

@@ -208,7 +210,7 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) writel_relaxed(1, drvdata->base + TRCPRGCTLR);

    /* wait for TRCSTATR.IDLE to go back down to '0' */

•   if (coresight_timeout(drvdata->base, TRCSTATR, TRCSTATR_IDLE_BIT, 0))
  

•   if (coresight_timeout(csa, TRCSTATR, TRCSTATR_IDLE_BIT, 0))
            dev_err(etm_dev,
                    "timeout while waiting for Idle Trace Status\n");
  
  

@@ -472,7 +474,9 @@ static void etm4_disable_hw(void *info) u32 control; struct etmv4_drvdata *drvdata = info; struct etmv4_config *config = &drvdata->config;

•   struct device *etm_dev = &drvdata->csdev->dev;
  

•   struct coresight_device *csdev = drvdata->csdev;
  

•   struct device *etm_dev = &csdev->dev;
  

•   struct csdev_access *csa = &csdev->access;
    int i;
  
    CS_UNLOCK(drvdata->base);
  

@@ -499,8 +503,7 @@ static void etm4_disable_hw(void *info) writel_relaxed(control, drvdata->base + TRCPRGCTLR);

    /* wait for TRCSTATR.PMSTABLE to go to '1' */

•   if (coresight_timeout(drvdata->base, TRCSTATR,
  

•                         TRCSTATR_PMSTABLE_BIT, 1))
  

•   if (coresight_timeout(csa, TRCSTATR, TRCSTATR_PMSTABLE_BIT, 1))
            dev_err(etm_dev,
                    "timeout while waiting for PM stable Trace Status\n");
  
  

@@ -1145,7 +1148,15 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata) { int i, ret = 0; struct etmv4_save_state *state;

•   struct device *etm_dev = &drvdata->csdev->dev;
  

•   struct coresight_device *csdev = drvdata->csdev;
  

•   struct csdev_access *csa;
  

•   struct device *etm_dev;
  

•   if (WARN_ON(!csdev))
  

•           return -ENODEV;
  

•   etm_dev = &csdev->dev;
  

•   csa = &csdev->access;
  
    /*
     * As recommended by 3.4.1 ("The procedure when powering down the PE")
  

@@ -1160,8 +1171,7 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata) etm4_os_lock(drvdata);

    /* wait for TRCSTATR.PMSTABLE to go up */

•   if (coresight_timeout(drvdata->base, TRCSTATR,
  

•                         TRCSTATR_PMSTABLE_BIT, 1)) {
  

•   if (coresight_timeout(csa, TRCSTATR, TRCSTATR_PMSTABLE_BIT, 1)) {
            dev_err(etm_dev,
                    "timeout while waiting for PM Stable Status\n");
            etm4_os_unlock(drvdata);
  

@@ -1244,7 +1254,7 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata) state->trcpdcr = readl(drvdata->base + TRCPDCR);

    /* wait for TRCSTATR.IDLE to go up */

•   if (coresight_timeout(drvdata->base, TRCSTATR, TRCSTATR_IDLE_BIT, 1)) {
  

•   if (coresight_timeout(csa, TRCSTATR, TRCSTATR_IDLE_BIT, 1)) {
            dev_err(etm_dev,
                    "timeout while waiting for Idle Trace Status\n");
            etm4_os_unlock(drvdata);
  

diff --git a/drivers/hwtracing/coresight/coresight-stm.c b/drivers/hwtracing/coresight/coresight-stm.c index fbf86f31f2ab..9667c5c8f433 100644 --- a/drivers/hwtracing/coresight/coresight-stm.c +++ b/drivers/hwtracing/coresight/coresight-stm.c @@ -258,6 +258,7 @@ static void stm_disable(struct coresight_device *csdev, struct perf_event *event) { struct stm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);

•   struct csdev_access *csa = &csdev->access;
  
    /*
     * For as long as the tracer isn't disabled another entity can't
  

@@ -270,7 +271,7 @@ static void stm_disable(struct coresight_device *csdev, spin_unlock(&drvdata->spinlock);

            /* Wait until the engine has completely stopped */

•           coresight_timeout(drvdata->base, STMTCSR, STMTCSR_BUSY_BIT, 0);
  

•           coresight_timeout(csa, STMTCSR, STMTCSR_BUSY_BIT, 0);
  
            pm_runtime_put(csdev->dev.parent);
  
  

diff --git a/drivers/hwtracing/coresight/coresight-tmc.c b/drivers/hwtracing/coresight/coresight-tmc.c index 5711e55c310c..cc9d97f9eb5b 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.c +++ b/drivers/hwtracing/coresight/coresight-tmc.c @@ -33,16 +33,20 @@ DEFINE_CORESIGHT_DEVLIST(etr_devs, "tmc_etr");

void tmc_wait_for_tmcready(struct tmc_drvdata *drvdata) {

•   struct coresight_device *csdev = drvdata->csdev;
  

•   struct csdev_access *csa = &csdev->access;
  

•   /* Ensure formatter, unformatter and hardware fifo are empty */
  

•   if (coresight_timeout(drvdata->base,
  

•                         TMC_STS, TMC_STS_TMCREADY_BIT, 1)) {
  

•           dev_err(&drvdata->csdev->dev,
  

•   if (coresight_timeout(csa, TMC_STS, TMC_STS_TMCREADY_BIT, 1)) {
  

•           dev_err(&csdev->dev,
                    "timeout while waiting for TMC to be Ready\n");
    }
  

}

void tmc_flush_and_stop(struct tmc_drvdata *drvdata) {

•   struct coresight_device *csdev = drvdata->csdev;
  

•   struct csdev_access *csa = &csdev->access;
    u32 ffcr;
  
    ffcr = readl_relaxed(drvdata->base + TMC_FFCR);
  

@@ -51,9 +55,8 @@ void tmc_flush_and_stop(struct tmc_drvdata *drvdata) ffcr |= BIT(TMC_FFCR_FLUSHMAN_BIT); writel_relaxed(ffcr, drvdata->base + TMC_FFCR); /* Ensure flush completes */

•   if (coresight_timeout(drvdata->base,
  

•                         TMC_FFCR, TMC_FFCR_FLUSHMAN_BIT, 0)) {
  

•           dev_err(&drvdata->csdev->dev,
  

•   if (coresight_timeout(csa, TMC_FFCR, TMC_FFCR_FLUSHMAN_BIT, 0)) {
  

•           dev_err(&csdev->dev,
            "timeout while waiting for completion of Manual Flush\n");
    }
  
  

diff --git a/drivers/hwtracing/coresight/coresight-tpiu.c b/drivers/hwtracing/coresight/coresight-tpiu.c index cc7d7ed474f5..7dd8300cf6be 100644 --- a/drivers/hwtracing/coresight/coresight-tpiu.c +++ b/drivers/hwtracing/coresight/coresight-tpiu.c @@ -86,9 +86,9 @@ static void tpiu_disable_hw(struct csdev_access *csa) /* Generate manual flush */ csdev_access_relaxed_write32(csa, FFCR_STOP_FI | FFCR_FON_MAN, TPIU_FFCR); /* Wait for flush to complete */

•   coresight_timeout(csa->base, TPIU_FFCR, FFCR_FON_MAN_BIT, 0);
  

•   coresight_timeout(csa, TPIU_FFCR, FFCR_FON_MAN_BIT, 0);
    /* Wait for formatter to stop */
  

•   coresight_timeout(csa->base, TPIU_FFSR, FFSR_FT_STOPPED_BIT, 1);
  

•   coresight_timeout(csa, TPIU_FFSR, FFSR_FT_STOPPED_BIT, 1);
  
    CS_LOCK(csa->base);
  

} diff --git a/drivers/hwtracing/coresight/coresight.c b/drivers/hwtracing/coresight/coresight.c index 38e9c03ab754..21e7615fcbc8 100644 --- a/drivers/hwtracing/coresight/coresight.c +++ b/drivers/hwtracing/coresight/coresight.c @@ -1338,23 +1338,26 @@ static void coresight_remove_conns(struct coresight_device *csdev) }

/**

• • coresight_timeout - loop until a bit has changed to a specific state.
• • @addr: base address of the area of interest.
• • @offset: address of a register, starting from @addr.

• • coresight_timeout - loop until a bit has changed to a specific register

• •                 state.
    

• • @csa: coresight device access for the device
• • @offset: Offset of the register from the base of the device.
  • @position: the position of the bit of interest.
  • @value: the value the bit should have.
  • Return: 0 as soon as the bit has taken the desired state or -EAGAIN if
  • TIMEOUT_US has elapsed, which ever happens first.
  */

-int coresight_timeout(void __iomem *addr, u32 offset, int position, int value) +int coresight_timeout(struct csdev_access *csa,

•                 u32 offset,
  

•                 int position,
  

•                 int value)
  

{ int i; u32 val;

    for (i = TIMEOUT_US; i > 0; i--) {

•           val = __raw_readl(addr + offset);
  

•           val = csdev_access_read32(csa, offset);
            /* waiting on the bit to go from 0 to 1 */
            if (value) {
                    if (val & BIT(position))
  

diff --git a/include/linux/coresight.h b/include/linux/coresight.h index 1377240275d8..55a9c3276a28 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -468,8 +468,10 @@ coresight_register(struct coresight_desc *desc); extern void coresight_unregister(struct coresight_device *csdev); extern int coresight_enable(struct coresight_device *csdev); extern void coresight_disable(struct coresight_device *csdev); -extern int coresight_timeout(void __iomem *addr, u32 offset,

•                        int position, int value);
  

+extern int coresight_timeout(struct csdev_access *csa,

•                        u32 offset,
  

•                        int position,
  

•                        int value);
  
  

extern int coresight_claim_device(void __iomem *base); extern int coresight_claim_device_unlocked(void __iomem *base); @@ -501,8 +503,15 @@ static inline void coresight_unregister(struct coresight_device *csdev) {} static inline int coresight_enable(struct coresight_device *csdev) { return -ENOSYS; } static inline void coresight_disable(struct coresight_device *csdev) {} -static inline int coresight_timeout(void __iomem *addr, u32 offset,

•                                int position, int value) { return 1; }
  

+static inline int coresight_timeout(struct csdev_access *csa,

•                               u32 offset,
  

•                               int position,
  

•                               int value)
  

+{

•   return 1;
  

+}

static inline int coresight_claim_device_unlocked(void __iomem *base) { return -EINVAL; -- 2.24.1

-- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK

Reviewed-by: Mike Leach mike.leach@linaro.org

On Fri, 11 Sep 2020 at 09:41, Suzuki K Poulose suzuki.poulose@arm.com wrote:

Convert the generic CLAIM tag management APIs to use the device access layer abstraction.

Cc: Mathieu Poirier mathieu.poirier@linaro.org Cc: Mike Leach mike.leach@linaro.org Signed-off-by: Suzuki K Poulose suzuki.poulose@arm.com

---

drivers/hwtracing/coresight/coresight-catu.c | 6 +- drivers/hwtracing/coresight/coresight-cti.c | 17 +++-- drivers/hwtracing/coresight/coresight-etb10.c | 4 +- drivers/hwtracing/coresight/coresight-etm3x.c | 8 ++- drivers/hwtracing/coresight/coresight-etm4x.c | 4 +- .../hwtracing/coresight/coresight-funnel.c | 6 +- .../coresight/coresight-replicator.c | 16 +++-- .../hwtracing/coresight/coresight-tmc-etf.c | 10 +-- .../hwtracing/coresight/coresight-tmc-etr.c | 4 +- drivers/hwtracing/coresight/coresight.c | 66 +++++++++++-------- include/linux/coresight.h | 16 ++--- 11 files changed, 95 insertions(+), 62 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-catu.c b/drivers/hwtracing/coresight/coresight-catu.c index 15e63e52ff23..df2f45457e2b 100644 --- a/drivers/hwtracing/coresight/coresight-catu.c +++ b/drivers/hwtracing/coresight/coresight-catu.c @@ -412,6 +412,7 @@ static int catu_enable_hw(struct catu_drvdata *drvdata, void *data) u32 control, mode; struct etr_buf *etr_buf = data; struct device *dev = &drvdata->csdev->dev;

•   struct coresight_device *csdev = drvdata->csdev;
  
    if (catu_wait_for_ready(drvdata))
            dev_warn(dev, "Timeout while waiting for READY\n");
  

@@ -422,7 +423,7 @@ static int catu_enable_hw(struct catu_drvdata *drvdata, void *data) return -EBUSY; }

•   rc = coresight_claim_device_unlocked(drvdata->base);
  

•   rc = coresight_claim_device_unlocked(csdev);
    if (rc)
            return rc;
  
  

@@ -466,9 +467,10 @@ static int catu_disable_hw(struct catu_drvdata *drvdata) { int rc = 0; struct device *dev = &drvdata->csdev->dev;

•   struct coresight_device *csdev = drvdata->csdev;
  
    catu_write_control(drvdata, 0);
  

•   coresight_disclaim_device_unlocked(drvdata->base);
  

•   coresight_disclaim_device_unlocked(csdev);
    if (catu_wait_for_ready(drvdata)) {
            dev_info(dev, "Timeout while waiting for READY\n");
            rc = -EAGAIN;
  

diff --git a/drivers/hwtracing/coresight/coresight-cti.c b/drivers/hwtracing/coresight/coresight-cti.c index e13e24e4a858..e07e15593dd8 100644 --- a/drivers/hwtracing/coresight/coresight-cti.c +++ b/drivers/hwtracing/coresight/coresight-cti.c @@ -102,7 +102,7 @@ static int cti_enable_hw(struct cti_drvdata *drvdata) goto cti_state_unchanged;

    /* claim the device */

•   rc = coresight_claim_device(drvdata->base);
  

•   rc = coresight_claim_device(drvdata->csdev);
    if (rc)
            goto cti_err_not_enabled;
  
  

@@ -136,7 +136,7 @@ static void cti_cpuhp_enable_hw(struct cti_drvdata *drvdata) goto cti_hp_not_enabled;

    /* try to claim the device */

•   if (coresight_claim_device(drvdata->base))
  

•   if (coresight_claim_device(drvdata->csdev))
            goto cti_hp_not_enabled;
  
    cti_write_all_hw_regs(drvdata);
  

@@ -154,6 +154,7 @@ static int cti_disable_hw(struct cti_drvdata *drvdata) { struct cti_config *config = &drvdata->config; struct device *dev = &drvdata->csdev->dev;

•   struct coresight_device *csdev = drvdata->csdev;
  
    spin_lock(&drvdata->spinlock);
  
  

@@ -171,7 +172,7 @@ static int cti_disable_hw(struct cti_drvdata *drvdata) writel_relaxed(0, drvdata->base + CTICONTROL); config->hw_enabled = false;

•   coresight_disclaim_device_unlocked(drvdata->base);
  

•   coresight_disclaim_device_unlocked(csdev);
    CS_LOCK(drvdata->base);
    spin_unlock(&drvdata->spinlock);
    pm_runtime_put(dev);
  

@@ -645,6 +646,7 @@ static int cti_cpu_pm_notify(struct notifier_block *nb, unsigned long cmd, void *v) { struct cti_drvdata *drvdata;

•   struct coresight_device *csdev;
    unsigned int cpu = smp_processor_id();
    int notify_res = NOTIFY_OK;
  
  

@@ -652,6 +654,7 @@ static int cti_cpu_pm_notify(struct notifier_block *nb, unsigned long cmd, return NOTIFY_OK;

    drvdata = cti_cpu_drvdata[cpu];

•   csdev = drvdata->csdev;
  
    if (WARN_ON_ONCE(drvdata->ctidev.cpu != cpu))
            return NOTIFY_BAD;
  

@@ -663,13 +666,13 @@ static int cti_cpu_pm_notify(struct notifier_block *nb, unsigned long cmd, /* CTI regs all static - we have a copy & nothing to save */ drvdata->config.hw_powered = false; if (drvdata->config.hw_enabled)

•                   coresight_disclaim_device(drvdata->base);
  

•                   coresight_disclaim_device(csdev);
            break;
  
    case CPU_PM_ENTER_FAILED:
            drvdata->config.hw_powered = true;
            if (drvdata->config.hw_enabled) {
  

•                   if (coresight_claim_device(drvdata->base))
  

•                   if (coresight_claim_device(csdev))
                            drvdata->config.hw_enabled = false;
            }
            break;
  

@@ -682,7 +685,7 @@ static int cti_cpu_pm_notify(struct notifier_block *nb, unsigned long cmd, /* check enable reference count to enable HW */ if (atomic_read(&drvdata->config.enable_req_count)) { /* check we can claim the device as we re-power */

•                   if (coresight_claim_device(drvdata->base))
  

•                   if (coresight_claim_device(csdev))
                            goto cti_notify_exit;
  
                    drvdata->config.hw_enabled = true;
  

@@ -726,7 +729,7 @@ static int cti_dying_cpu(unsigned int cpu) spin_lock(&drvdata->spinlock); drvdata->config.hw_powered = false; if (drvdata->config.hw_enabled)

•           coresight_disclaim_device(drvdata->base);
  

•           coresight_disclaim_device(drvdata->csdev);
    spin_unlock(&drvdata->spinlock);
    return 0;
  

} diff --git a/drivers/hwtracing/coresight/coresight-etb10.c b/drivers/hwtracing/coresight/coresight-etb10.c index 2786d02dd23b..5b0d1c1a0442 100644 --- a/drivers/hwtracing/coresight/coresight-etb10.c +++ b/drivers/hwtracing/coresight/coresight-etb10.c @@ -132,7 +132,7 @@ static void __etb_enable_hw(struct etb_drvdata *drvdata)

static int etb_enable_hw(struct etb_drvdata *drvdata) {

•   int rc = coresight_claim_device(drvdata->base);
  

•   int rc = coresight_claim_device(drvdata->csdev);
  
    if (rc)
            return rc;
  

@@ -344,7 +344,7 @@ static void etb_disable_hw(struct etb_drvdata *drvdata) { __etb_disable_hw(drvdata); etb_dump_hw(drvdata);

•   coresight_disclaim_device(drvdata->base);
  

•   coresight_disclaim_device(drvdata->csdev);
  

}

static int etb_disable(struct coresight_device *csdev) diff --git a/drivers/hwtracing/coresight/coresight-etm3x.c b/drivers/hwtracing/coresight/coresight-etm3x.c index e3724d8adecb..a7c791f15da7 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x.c +++ b/drivers/hwtracing/coresight/coresight-etm3x.c @@ -360,10 +360,11 @@ static int etm_enable_hw(struct etm_drvdata *drvdata) int i, rc; u32 etmcr; struct etm_config *config = &drvdata->config;

•   struct coresight_device *csdev = drvdata->csdev;
  
    CS_UNLOCK(drvdata->base);
  
  

•   rc = coresight_claim_device_unlocked(drvdata->base);
  

•   rc = coresight_claim_device_unlocked(csdev);
    if (rc)
            goto done;
  
  

@@ -568,6 +569,7 @@ static void etm_disable_hw(void *info) int i; struct etm_drvdata *drvdata = info; struct etm_config *config = &drvdata->config;

•   struct coresight_device *csdev = drvdata->csdev;
  
    CS_UNLOCK(drvdata->base);
    etm_set_prog(drvdata);
  

@@ -579,7 +581,7 @@ static void etm_disable_hw(void *info) config->cntr_val[i] = etm_readl(drvdata, ETMCNTVRn(i));

    etm_set_pwrdwn(drvdata);

•   coresight_disclaim_device_unlocked(drvdata->base);
  

•   coresight_disclaim_device_unlocked(csdev);
  
    CS_LOCK(drvdata->base);
  
  

@@ -604,7 +606,7 @@ static void etm_disable_perf(struct coresight_device *csdev) * power down the tracer. */ etm_set_pwrdwn(drvdata);

•   coresight_disclaim_device_unlocked(drvdata->base);
  

•   coresight_disclaim_device_unlocked(csdev);
  
    CS_LOCK(drvdata->base);
  

} diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index 973fb0fd4826..5b81d6f12027 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -115,7 +115,7 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)

    etm4_os_unlock(drvdata);

•   rc = coresight_claim_device_unlocked(drvdata->base);
  

•   rc = coresight_claim_device_unlocked(csdev);
    if (rc)
            goto done;
  
  

@@ -519,7 +519,7 @@ static void etm4_disable_hw(void *info) readl_relaxed(drvdata->base + TRCCNTVRn(i)); }

•   coresight_disclaim_device_unlocked(drvdata->base);
  

•   coresight_disclaim_device_unlocked(csdev);
  
    CS_LOCK(drvdata->base);
  
  

diff --git a/drivers/hwtracing/coresight/coresight-funnel.c b/drivers/hwtracing/coresight/coresight-funnel.c index e8e233cbc130..b3f98ce51a68 100644 --- a/drivers/hwtracing/coresight/coresight-funnel.c +++ b/drivers/hwtracing/coresight/coresight-funnel.c @@ -52,13 +52,14 @@ static int dynamic_funnel_enable_hw(struct funnel_drvdata *drvdata, int port) { u32 functl; int rc = 0;

•   struct coresight_device *csdev = drvdata->csdev;
  
    CS_UNLOCK(drvdata->base);
  
    functl = readl_relaxed(drvdata->base + FUNNEL_FUNCTL);
    /* Claim the device only when we enable the first slave */
    if (!(functl & FUNNEL_ENSx_MASK)) {
  

•           rc = coresight_claim_device_unlocked(drvdata->base);
  

•           rc = coresight_claim_device_unlocked(csdev);
            if (rc)
                    goto done;
    }
  

@@ -101,6 +102,7 @@ static void dynamic_funnel_disable_hw(struct funnel_drvdata *drvdata, int inport) { u32 functl;

•   struct coresight_device *csdev = drvdata->csdev;
  
    CS_UNLOCK(drvdata->base);
  
  

@@ -110,7 +112,7 @@ static void dynamic_funnel_disable_hw(struct funnel_drvdata *drvdata,

    /* Disclaim the device if none of the slaves are now active */
    if (!(functl & FUNNEL_ENSx_MASK))

•           coresight_disclaim_device_unlocked(drvdata->base);
  

•           coresight_disclaim_device_unlocked(csdev);
  
    CS_LOCK(drvdata->base);
  

} diff --git a/drivers/hwtracing/coresight/coresight-replicator.c b/drivers/hwtracing/coresight/coresight-replicator.c index 8ba9cbe1d108..b8361bb808f1 100644 --- a/drivers/hwtracing/coresight/coresight-replicator.c +++ b/drivers/hwtracing/coresight/coresight-replicator.c @@ -45,12 +45,18 @@ struct replicator_drvdata {

static void dynamic_replicator_reset(struct replicator_drvdata *drvdata) {

•   struct coresight_device *csdev = drvdata->csdev;
    CS_UNLOCK(drvdata->base);
  
  

•   if (!coresight_claim_device_unlocked(drvdata->base)) {
  

•   if (WARN_ON(!csdev))
  

•           return;
  

•   CS_UNLOCK(drvdata->base);
  

•   if (!coresight_claim_device_unlocked(csdev)) {
            writel_relaxed(0xff, drvdata->base + REPLICATOR_IDFILTER0);
            writel_relaxed(0xff, drvdata->base + REPLICATOR_IDFILTER1);
  

•           coresight_disclaim_device_unlocked(drvdata->base);
  

•           coresight_disclaim_device_unlocked(csdev);
    }
  
    CS_LOCK(drvdata->base);
  

@@ -70,6 +76,7 @@ static int dynamic_replicator_enable(struct replicator_drvdata *drvdata, { int rc = 0; u32 id0val, id1val;

•   struct coresight_device *csdev = drvdata->csdev;
  
    CS_UNLOCK(drvdata->base);
  
  

@@ -84,7 +91,7 @@ static int dynamic_replicator_enable(struct replicator_drvdata *drvdata, id0val = id1val = 0xff;

    if (id0val == 0xff && id1val == 0xff)

•           rc = coresight_claim_device_unlocked(drvdata->base);
  

•           rc = coresight_claim_device_unlocked(csdev);
  
    if (!rc) {
            switch (outport) {
  

@@ -140,6 +147,7 @@ static void dynamic_replicator_disable(struct replicator_drvdata *drvdata, int inport, int outport) { u32 reg;

•   struct coresight_device *csdev = drvdata->csdev;
  
    switch (outport) {
    case 0:
  

@@ -160,7 +168,7 @@ static void dynamic_replicator_disable(struct replicator_drvdata *drvdata,

    if ((readl_relaxed(drvdata->base + REPLICATOR_IDFILTER0) == 0xff) &&
        (readl_relaxed(drvdata->base + REPLICATOR_IDFILTER1) == 0xff))

•           coresight_disclaim_device_unlocked(drvdata->base);
  

•           coresight_disclaim_device_unlocked(csdev);
    CS_LOCK(drvdata->base);
  

}

diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c index 6375504ba8b0..610a494efbbc 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c @@ -37,7 +37,7 @@ static void __tmc_etb_enable_hw(struct tmc_drvdata *drvdata)

static int tmc_etb_enable_hw(struct tmc_drvdata *drvdata) {

•   int rc = coresight_claim_device(drvdata->base);
  

•   int rc = coresight_claim_device(drvdata->csdev);
  
    if (rc)
            return rc;
  

@@ -88,7 +88,7 @@ static void __tmc_etb_disable_hw(struct tmc_drvdata *drvdata) static void tmc_etb_disable_hw(struct tmc_drvdata *drvdata) { __tmc_etb_disable_hw(drvdata);

•   coresight_disclaim_device(drvdata->base);
  

•   coresight_disclaim_device(drvdata->csdev);
  

}

static void __tmc_etf_enable_hw(struct tmc_drvdata *drvdata) @@ -109,7 +109,7 @@ static void __tmc_etf_enable_hw(struct tmc_drvdata *drvdata)

static int tmc_etf_enable_hw(struct tmc_drvdata *drvdata) {

•   int rc = coresight_claim_device(drvdata->base);
  

•   int rc = coresight_claim_device(drvdata->csdev);
  
    if (rc)
            return rc;
  

@@ -120,11 +120,13 @@ static int tmc_etf_enable_hw(struct tmc_drvdata *drvdata)

static void tmc_etf_disable_hw(struct tmc_drvdata *drvdata) {

•   struct coresight_device *csdev = drvdata->csdev;
  

•   CS_UNLOCK(drvdata->base);
  
    tmc_flush_and_stop(drvdata);
    tmc_disable_hw(drvdata);
  

•   coresight_disclaim_device_unlocked(drvdata->base);
  

•   coresight_disclaim_device_unlocked(csdev);
    CS_LOCK(drvdata->base);
  

}

diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index b29c2db94d96..1aae2405041d 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -1021,7 +1021,7 @@ static int tmc_etr_enable_hw(struct tmc_drvdata *drvdata, rc = tmc_etr_enable_catu(drvdata, etr_buf); if (rc) return rc;

•   rc = coresight_claim_device(drvdata->base);
  

•   rc = coresight_claim_device(drvdata->csdev);
    if (!rc) {
            drvdata->etr_buf = etr_buf;
            __tmc_etr_enable_hw(drvdata);
  

@@ -1115,7 +1115,7 @@ void tmc_etr_disable_hw(struct tmc_drvdata *drvdata) __tmc_etr_disable_hw(drvdata); /* Disable CATU device if this ETR is connected to one */ tmc_etr_disable_catu(drvdata);

•   coresight_disclaim_device(drvdata->base);
  

•   coresight_disclaim_device(drvdata->csdev);
    /* Reset the ETR buf used by hardware */
    drvdata->etr_buf = NULL;
  

} diff --git a/drivers/hwtracing/coresight/coresight.c b/drivers/hwtracing/coresight/coresight.c index 21e7615fcbc8..7545a22769c4 100644 --- a/drivers/hwtracing/coresight/coresight.c +++ b/drivers/hwtracing/coresight/coresight.c @@ -130,30 +130,32 @@ static int coresight_find_link_outport(struct coresight_device *csdev, return -ENODEV; }

-static inline u32 coresight_read_claim_tags(void __iomem *base) +static inline u32 coresight_read_claim_tags(struct coresight_device *csdev) {

•   return readl_relaxed(base + CORESIGHT_CLAIMCLR);
  

•   return csdev_access_relaxed_read32(&csdev->access, CORESIGHT_CLAIMCLR);
  

}

-static inline bool coresight_is_claimed_self_hosted(void __iomem *base) +static inline bool coresight_is_claimed_self_hosted(struct coresight_device *csdev) {

•   return coresight_read_claim_tags(base) == CORESIGHT_CLAIM_SELF_HOSTED;
  

•   return coresight_read_claim_tags(csdev) == CORESIGHT_CLAIM_SELF_HOSTED;
  

}

-static inline bool coresight_is_claimed_any(void __iomem *base) +static inline bool coresight_is_claimed_any(struct coresight_device *csdev) {

•   return coresight_read_claim_tags(base) != 0;
  

•   return coresight_read_claim_tags(csdev) != 0;
  

}

-static inline void coresight_set_claim_tags(void __iomem *base) +static inline void coresight_set_claim_tags(struct coresight_device *csdev) {

•   writel_relaxed(CORESIGHT_CLAIM_SELF_HOSTED, base + CORESIGHT_CLAIMSET);
  

•   csdev_access_relaxed_write32(&csdev->access, CORESIGHT_CLAIM_SELF_HOSTED,
  

•                             CORESIGHT_CLAIMSET);
    isb();
  

}

-static inline void coresight_clear_claim_tags(void __iomem *base) +static inline void coresight_clear_claim_tags(struct coresight_device *csdev) {

•   writel_relaxed(CORESIGHT_CLAIM_SELF_HOSTED, base + CORESIGHT_CLAIMCLR);
  

•   csdev_access_relaxed_write32(&csdev->access, CORESIGHT_CLAIM_SELF_HOSTED,
  

•                             CORESIGHT_CLAIMCLR);
    isb();
  

}

@@ -167,26 +169,32 @@ static inline void coresight_clear_claim_tags(void __iomem *base)

• Called with CS_UNLOCKed for the component.
• Returns : 0 on success

*/ -int coresight_claim_device_unlocked(void __iomem *base) +int coresight_claim_device_unlocked(struct coresight_device *csdev) {

•   if (coresight_is_claimed_any(base))
  

•   if (WARN_ON(!csdev))
  

•           return -EINVAL;
  

•   if (coresight_is_claimed_any(csdev))
            return -EBUSY;
  
  

•   coresight_set_claim_tags(base);
  

•   if (coresight_is_claimed_self_hosted(base))
  

•   coresight_set_claim_tags(csdev);
  

•   if (coresight_is_claimed_self_hosted(csdev))
            return 0;
    /* There was a race setting the tags, clean up and fail */
  

•   coresight_clear_claim_tags(base);
  

•   coresight_clear_claim_tags(csdev);
    return -EBUSY;
  

}

-int coresight_claim_device(void __iomem *base) +int coresight_claim_device(struct coresight_device *csdev) { int rc;

•   CS_UNLOCK(base);
  

•   rc = coresight_claim_device_unlocked(base);
  

•   CS_LOCK(base);
  

•   if (WARN_ON(!csdev))
  

•           return -EINVAL;
  

•   CS_UNLOCK(csdev->access.base);
  

•   rc = coresight_claim_device_unlocked(csdev);
  

•   CS_LOCK(csdev->access.base);
  
    return rc;
  

} @@ -195,11 +203,14 @@ int coresight_claim_device(void __iomem *base)

• coresight_disclaim_device_unlocked : Clear the claim tags for the device.
• Called with CS_UNLOCKed for the component.

*/ -void coresight_disclaim_device_unlocked(void __iomem *base) +void coresight_disclaim_device_unlocked(struct coresight_device *csdev) {

•   if (coresight_is_claimed_self_hosted(base))
  

•           coresight_clear_claim_tags(base);
  

•   if (WARN_ON(!csdev))
  

•           return;
  

•   if (coresight_is_claimed_self_hosted(csdev))
  

•           coresight_clear_claim_tags(csdev);
    else
            /*
             * The external agent may have not honoured our claim
  

@@ -209,11 +220,14 @@ void coresight_disclaim_device_unlocked(void __iomem *base) WARN_ON_ONCE(1); }

-void coresight_disclaim_device(void __iomem *base) +void coresight_disclaim_device(struct coresight_device *csdev) {

•   CS_UNLOCK(base);
  

•   coresight_disclaim_device_unlocked(base);
  

•   CS_LOCK(base);
  

•   if (WARN_ON(!csdev))
  

•           return;
  

•   CS_UNLOCK(csdev->access.base);
  

•   coresight_disclaim_device_unlocked(csdev);
  

•   CS_LOCK(csdev->access.base);
  

}

/* enable or disable an associated CTI device of the supplied CS device */ diff --git a/include/linux/coresight.h b/include/linux/coresight.h index 55a9c3276a28..811fdc21075a 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -473,11 +473,11 @@ extern int coresight_timeout(struct csdev_access *csa, int position, int value);

-extern int coresight_claim_device(void __iomem *base); -extern int coresight_claim_device_unlocked(void __iomem *base); +extern int coresight_claim_device(struct coresight_device *csdev); +extern int coresight_claim_device_unlocked(struct coresight_device *csdev);

-extern void coresight_disclaim_device(void __iomem *base); -extern void coresight_disclaim_device_unlocked(void __iomem *base); +extern void coresight_disclaim_device(struct coresight_device *csdev); +extern void coresight_disclaim_device_unlocked(struct coresight_device *csdev); extern char *coresight_alloc_device_name(struct coresight_dev_list *devs, struct device *dev);

@@ -512,18 +512,18 @@ static inline int coresight_timeout(struct csdev_access *csa, return 1; }

-static inline int coresight_claim_device_unlocked(void __iomem *base) +static inline int coresight_claim_device_unlocked(struct coresight_device *csdev) { return -EINVAL; }

-static inline int coresight_claim_device(void __iomem *base) +static inline int coresight_claim_device(struct coresight_device *csdev) { return -EINVAL; }

-static inline void coresight_disclaim_device(void __iomem *base) {} -static inline void coresight_disclaim_device_unlocked(void __iomem *base) {} +static inline void coresight_disclaim_device(struct coresight_device *csdev) {} +static inline void coresight_disclaim_device_unlocked(struct coresight_device *csdev) {}

static inline bool coresight_loses_context_with_cpu(struct device *dev) { -- 2.24.1

-- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK

Hi Suzuki,

On Fri, 11 Sep 2020 at 09:41, Suzuki K Poulose suzuki.poulose@arm.com wrote:

Convert CS_LOCK/UNLOCK operations to use the device access layer.

Cc: Mathieu Poirier mathieu.poirier@linaro.org Cc: Mike Leach mike.leach@linaro.org Signed-off-by: Suzuki K Poulose suzuki.poulose@arm.com

---

drivers/hwtracing/coresight/coresight-catu.c | 12 +++-- .../hwtracing/coresight/coresight-cpu-debug.c | 22 +++++++-- .../hwtracing/coresight/coresight-cti-sysfs.c | 5 +- drivers/hwtracing/coresight/coresight-cti.c | 16 ++++--- drivers/hwtracing/coresight/coresight-etb10.c | 19 ++++---- .../coresight/coresight-etm3x-sysfs.c | 10 ++-- drivers/hwtracing/coresight/coresight-etm3x.c | 26 +++++++---- drivers/hwtracing/coresight/coresight-etm4x.c | 27 +++++++---- .../hwtracing/coresight/coresight-funnel.c | 15 +++--- drivers/hwtracing/coresight/coresight-priv.h | 9 ++-- .../coresight/coresight-replicator.c | 16 ++++--- drivers/hwtracing/coresight/coresight-stm.c | 46 ++++++++++++------- .../hwtracing/coresight/coresight-tmc-etf.c | 28 +++++++---- .../hwtracing/coresight/coresight-tmc-etr.c | 16 ++++--- drivers/hwtracing/coresight/coresight-tpiu.c | 9 ++-- drivers/hwtracing/coresight/coresight.c | 8 ++-- 16 files changed, 179 insertions(+), 105 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-catu.c b/drivers/hwtracing/coresight/coresight-catu.c index df2f45457e2b..9e96cda2f924 100644 --- a/drivers/hwtracing/coresight/coresight-catu.c +++ b/drivers/hwtracing/coresight/coresight-catu.c @@ -456,10 +456,12 @@ static int catu_enable(struct coresight_device *csdev, void *data) { int rc; struct catu_drvdata *catu_drvdata = csdev_to_catu_drvdata(csdev);

•   struct csdev_access *csa = &csdev->access;
  
  

•   CS_UNLOCK(catu_drvdata->base);
  

•   CS_UNLOCK(csa);
    rc = catu_enable_hw(catu_drvdata, data);
  

•   CS_LOCK(catu_drvdata->base);
  

•   CS_LOCK(csa);
  

•   return rc;
  

}

@@ -484,10 +486,12 @@ static int catu_disable(struct coresight_device *csdev, void *__unused) { int rc; struct catu_drvdata *catu_drvdata = csdev_to_catu_drvdata(csdev);

•   struct csdev_access *csa = &csdev->access;
  
  

•   CS_UNLOCK(catu_drvdata->base);
  

•   CS_UNLOCK(csa);
    rc = catu_disable_hw(catu_drvdata);
  

•   CS_LOCK(catu_drvdata->base);
  

•   CS_LOCK(csa);
  

•   return rc;
  

}

diff --git a/drivers/hwtracing/coresight/coresight-cpu-debug.c b/drivers/hwtracing/coresight/coresight-cpu-debug.c index 96544b348c27..5d5619284866 100644 --- a/drivers/hwtracing/coresight/coresight-cpu-debug.c +++ b/drivers/hwtracing/coresight/coresight-cpu-debug.c @@ -108,6 +108,20 @@ static bool debug_enable; module_param_named(enable, debug_enable, bool, 0600); MODULE_PARM_DESC(enable, "Control to enable coresight CPU debug functionality");

+static inline void coresight_debug_lock(struct debug_drvdata *drvdata) +{

•   struct csdev_access dummy = CSDEV_ACCESS_IOMEM(drvdata->base);
  

•   CS_LOCK(&dummy);
  

+}

+static void coresight_debug_unlock(struct debug_drvdata *drvdata) +{

•   struct csdev_access dummy = CSDEV_ACCESS_IOMEM(drvdata->base);
  

•   CS_UNLOCK(&dummy);
  

+}

Perhaps it's just me, but whenever I see "dummy" in code, I immediately think this is stubbed out and doing nothing.

static void debug_os_unlock(struct debug_drvdata *drvdata) { /* Unlocks the debug registers */ @@ -191,7 +205,7 @@ static void debug_read_regs(struct debug_drvdata *drvdata) { u32 save_edprcr;

•   CS_UNLOCK(drvdata->base);
  

•   coresight_debug_unlock(drvdata);
  
    /* Unlock os lock */
    debug_os_unlock(drvdata);
  

@@ -238,7 +252,7 @@ static void debug_read_regs(struct debug_drvdata *drvdata) /* Restore EDPRCR register */ writel_relaxed(save_edprcr, drvdata->base + EDPRCR);

•   CS_LOCK(drvdata->base);
  

•   coresight_debug_lock(drvdata);
  

}

#ifdef CONFIG_64BIT @@ -326,13 +340,13 @@ static void debug_init_arch_data(void *info) u32 mode, pcsr_offset; u32 eddevid, eddevid1;

•   CS_UNLOCK(drvdata->base);
  

•   coresight_debug_unlock(drvdata);
  
    /* Read device info */
    eddevid  = readl_relaxed(drvdata->base + EDDEVID);
    eddevid1 = readl_relaxed(drvdata->base + EDDEVID1);
  
  

•   CS_LOCK(drvdata->base);
  

•   coresight_debug_lock(drvdata);
  
    /* Parse implementation feature */
    mode = eddevid & EDDEVID_PCSAMPLE_MODE;
  

diff --git a/drivers/hwtracing/coresight/coresight-cti-sysfs.c b/drivers/hwtracing/coresight/coresight-cti-sysfs.c index 392757f3a019..2208b5191042 100644 --- a/drivers/hwtracing/coresight/coresight-cti-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-cti-sysfs.c @@ -220,14 +220,15 @@ static ssize_t cti_reg32_show(struct device *dev, char *buf, u32 val = 0; struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); struct cti_config *config = &drvdata->config;

•   struct csdev_access *csa = &drvdata->csdev->access;
  
    spin_lock(&drvdata->spinlock);
    if ((reg_offset >= 0) && cti_active(config)) {
  

•           CS_UNLOCK(drvdata->base);
  

•           CS_UNLOCK(csa);
            val = readl_relaxed(drvdata->base + reg_offset);
            if (pcached_val)
                    *pcached_val = val;
  

•           CS_LOCK(drvdata->base);
  

•           CS_LOCK(csa);
    } else if (pcached_val) {
            val = *pcached_val;
    }
  

diff --git a/drivers/hwtracing/coresight/coresight-cti.c b/drivers/hwtracing/coresight/coresight-cti.c index e07e15593dd8..f921a9eeba81 100644 --- a/drivers/hwtracing/coresight/coresight-cti.c +++ b/drivers/hwtracing/coresight/coresight-cti.c @@ -60,10 +60,11 @@ DEFINE_CORESIGHT_DEVLIST(cti_sys_devs, "cti_sys"); /* write set of regs to hardware - call with spinlock claimed */ void cti_write_all_hw_regs(struct cti_drvdata *drvdata) {

•   struct csdev_access *csa = &drvdata->csdev->access;
    struct cti_config *config = &drvdata->config;
    int i;
  
  

•   CS_UNLOCK(drvdata->base);
  

•   CS_UNLOCK(csa);
  
    /* disable CTI before writing registers */
    writel_relaxed(0, drvdata->base + CTICONTROL);
  

@@ -83,7 +84,7 @@ void cti_write_all_hw_regs(struct cti_drvdata *drvdata) /* re-enable CTI */ writel_relaxed(1, drvdata->base + CTICONTROL);

•   CS_LOCK(drvdata->base);
  

•   CS_LOCK(csa);
  

}

/* write regs to hardware and enable */ @@ -155,6 +156,7 @@ static int cti_disable_hw(struct cti_drvdata *drvdata) struct cti_config *config = &drvdata->config; struct device *dev = &drvdata->csdev->dev; struct coresight_device *csdev = drvdata->csdev;

•   struct csdev_access *csa = &csdev->access;
  
    spin_lock(&drvdata->spinlock);
  
  

@@ -166,14 +168,14 @@ static int cti_disable_hw(struct cti_drvdata *drvdata) if (!config->hw_enabled || !config->hw_powered) goto cti_not_disabled;

•   CS_UNLOCK(drvdata->base);
  

•   CS_UNLOCK(csa);
  
    /* disable CTI */
    writel_relaxed(0, drvdata->base + CTICONTROL);
    config->hw_enabled = false;
  
    coresight_disclaim_device_unlocked(csdev);
  

•   CS_LOCK(drvdata->base);
  

•   CS_LOCK(csa);
    spin_unlock(&drvdata->spinlock);
    pm_runtime_put(dev);
    return 0;
  

@@ -186,9 +188,11 @@ static int cti_disable_hw(struct cti_drvdata *drvdata)

void cti_write_single_reg(struct cti_drvdata *drvdata, int offset, u32 value) {

•   CS_UNLOCK(drvdata->base);
  

•   struct csdev_access *csa = &drvdata->csdev->access;
  

•   CS_UNLOCK(csa);
    writel_relaxed(value, drvdata->base + offset);
  

•   CS_LOCK(drvdata->base);
  

•   CS_LOCK(csa);
  

}

void cti_write_intack(struct device *dev, u32 ackval) diff --git a/drivers/hwtracing/coresight/coresight-etb10.c b/drivers/hwtracing/coresight/coresight-etb10.c index 5b0d1c1a0442..b41cd73585cc 100644 --- a/drivers/hwtracing/coresight/coresight-etb10.c +++ b/drivers/hwtracing/coresight/coresight-etb10.c @@ -106,8 +106,9 @@ static void __etb_enable_hw(struct etb_drvdata *drvdata) { int i; u32 depth;

•   struct csdev_access *csa = &drvdata->csdev->access;
  
  

•   CS_UNLOCK(drvdata->base);
  

•   CS_UNLOCK(csa);
  
    depth = drvdata->buffer_depth;
    /* reset write RAM pointer address */
  

@@ -127,7 +128,7 @@ static void __etb_enable_hw(struct etb_drvdata *drvdata) /* ETB trace capture enable */ writel_relaxed(ETB_CTL_CAPT_EN, drvdata->base + ETB_CTL_REG);

•   CS_LOCK(drvdata->base);
  

•   CS_LOCK(csa);
  

}

static int etb_enable_hw(struct etb_drvdata *drvdata) @@ -253,7 +254,7 @@ static void __etb_disable_hw(struct etb_drvdata *drvdata) struct device *dev = &drvdata->csdev->dev; struct csdev_access *csa = &drvdata->csdev->access;

•   CS_UNLOCK(drvdata->base);
  

•   CS_UNLOCK(csa);
  
    ffcr = readl_relaxed(drvdata->base + ETB_FFCR);
    /* stop formatter when a stop has completed */
  

@@ -276,7 +277,7 @@ static void __etb_disable_hw(struct etb_drvdata *drvdata) "timeout while waiting for Formatter to Stop\n"); }

•   CS_LOCK(drvdata->base);
  

•   CS_LOCK(csa);
  

}

static void etb_dump_hw(struct etb_drvdata *drvdata) @@ -288,8 +289,9 @@ static void etb_dump_hw(struct etb_drvdata *drvdata) u32 read_ptr, write_ptr; u32 frame_off, frame_endoff; struct device *dev = &drvdata->csdev->dev;

•   struct csdev_access *csa = &drvdata->csdev->access;
  
  

•   CS_UNLOCK(drvdata->base);
  

•   CS_UNLOCK(csa);
  
    read_ptr = readl_relaxed(drvdata->base + ETB_RAM_READ_POINTER);
    write_ptr = readl_relaxed(drvdata->base + ETB_RAM_WRITE_POINTER);
  

@@ -337,7 +339,7 @@ static void etb_dump_hw(struct etb_drvdata *drvdata)

    writel_relaxed(read_ptr, drvdata->base + ETB_RAM_READ_POINTER);

•   CS_LOCK(drvdata->base);
  

•   CS_LOCK(csa);
  

}

static void etb_disable_hw(struct etb_drvdata *drvdata) @@ -435,6 +437,7 @@ static unsigned long etb_update_buffer(struct coresight_device *csdev, unsigned long offset, to_read = 0, flags; struct cs_buffers *buf = sink_config; struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);

•   struct csdev_access *csa = &drvdata->csdev->access;
  
    if (!buf)
            return 0;
  

@@ -448,7 +451,7 @@ static unsigned long etb_update_buffer(struct coresight_device *csdev, goto out;

    __etb_disable_hw(drvdata);

•   CS_UNLOCK(drvdata->base);
  

•   CS_UNLOCK(csa);
  
    /* unit is in words, not bytes */
    read_ptr = readl_relaxed(drvdata->base + ETB_RAM_READ_POINTER);
  

@@ -563,7 +566,7 @@ static unsigned long etb_update_buffer(struct coresight_device *csdev, handle->head += to_read;

    __etb_enable_hw(drvdata);

•   CS_LOCK(drvdata->base);
  

•   CS_LOCK(csa);
  

out: spin_unlock_irqrestore(&drvdata->spinlock, flags);

diff --git a/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c index e8c7649f123e..3e379b3fcdfd 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c @@ -47,14 +47,15 @@ static ssize_t etmsr_show(struct device *dev, { unsigned long flags, val; struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);

•   struct csdev_access *csa = &drvdata->csdev->access;
  
    pm_runtime_get_sync(dev->parent);
    spin_lock_irqsave(&drvdata->spinlock, flags);
  

•   CS_UNLOCK(drvdata->base);
  

•   CS_UNLOCK(csa);
  
    val = etm_readl(drvdata, ETMSR);
  
  

•   CS_LOCK(drvdata->base);
  

•   CS_LOCK(csa);
    spin_unlock_irqrestore(&drvdata->spinlock, flags);
    pm_runtime_put(dev->parent);
  
  

@@ -939,6 +940,7 @@ static ssize_t seq_curr_state_show(struct device *dev, unsigned long val, flags; struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent); struct etm_config *config = &drvdata->config;

•   struct csdev_access *csa = &drvdata->csdev->access;
  
    if (!local_read(&drvdata->mode)) {
            val = config->seq_curr_state;
  

@@ -948,9 +950,9 @@ static ssize_t seq_curr_state_show(struct device *dev, pm_runtime_get_sync(dev->parent); spin_lock_irqsave(&drvdata->spinlock, flags);

•   CS_UNLOCK(drvdata->base);
  

•   CS_UNLOCK(csa);
    val = (etm_readl(drvdata, ETMSQR) & ETM_SQR_MASK);
  

•   CS_LOCK(drvdata->base);
  

•   CS_LOCK(csa);
  
    spin_unlock_irqrestore(&drvdata->spinlock, flags);
    pm_runtime_put(dev->parent);
  

diff --git a/drivers/hwtracing/coresight/coresight-etm3x.c b/drivers/hwtracing/coresight/coresight-etm3x.c index a7c791f15da7..debb4dc15527 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x.c +++ b/drivers/hwtracing/coresight/coresight-etm3x.c @@ -361,8 +361,9 @@ static int etm_enable_hw(struct etm_drvdata *drvdata) u32 etmcr; struct etm_config *config = &drvdata->config; struct coresight_device *csdev = drvdata->csdev;

•   struct csdev_access *csa = &drvdata->csdev->access;
  
  

•   CS_UNLOCK(drvdata->base);
  

•   CS_UNLOCK(csa);
  
    rc = coresight_claim_device_unlocked(csdev);
    if (rc)
  

@@ -424,7 +425,7 @@ static int etm_enable_hw(struct etm_drvdata *drvdata) etm_clr_prog(drvdata);

done:

•   CS_LOCK(drvdata->base);
  

•   CS_LOCK(csa);
  
    dev_dbg(&drvdata->csdev->dev, "cpu: %d enable smp call done: %d\n",
            drvdata->cpu, rc);
  

@@ -457,10 +458,12 @@ int etm_get_trace_id(struct etm_drvdata *drvdata) unsigned long flags; int trace_id = -1; struct device *etm_dev;

•   struct csdev_access *csa;
  
    if (!drvdata)
            goto out;
  
  

•   csa = &drvdata->csdev->access;
    etm_dev = drvdata->csdev->dev.parent;
    if (!local_read(&drvdata->mode))
            return drvdata->traceid;
  

@@ -469,9 +472,9 @@ int etm_get_trace_id(struct etm_drvdata *drvdata)

    spin_lock_irqsave(&drvdata->spinlock, flags);

•   CS_UNLOCK(drvdata->base);
  

•   CS_UNLOCK(csa);
    trace_id = (etm_readl(drvdata, ETMTRACEIDR) & ETM_TRACEID_MASK);
  

•   CS_LOCK(drvdata->base);
  

•   CS_LOCK(csa);
  
    spin_unlock_irqrestore(&drvdata->spinlock, flags);
    pm_runtime_put(etm_dev);
  

@@ -570,8 +573,9 @@ static void etm_disable_hw(void *info) struct etm_drvdata *drvdata = info; struct etm_config *config = &drvdata->config; struct coresight_device *csdev = drvdata->csdev;

•   struct csdev_access *csa = &drvdata->csdev->access;
  
  

•   CS_UNLOCK(drvdata->base);
  

•   CS_UNLOCK(csa);
    etm_set_prog(drvdata);
  
    /* Read back sequencer and counters for post trace analysis */
  

@@ -583,7 +587,7 @@ static void etm_disable_hw(void *info) etm_set_pwrdwn(drvdata); coresight_disclaim_device_unlocked(csdev);

•   CS_LOCK(drvdata->base);
  

•   CS_LOCK(csa);
  
    dev_dbg(&drvdata->csdev->dev,
            "cpu: %d disable smp call done\n", drvdata->cpu);
  

@@ -592,11 +596,12 @@ static void etm_disable_hw(void *info) static void etm_disable_perf(struct coresight_device *csdev) { struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);

•   struct csdev_access *csa = &drvdata->csdev->access;
  
    if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id()))
            return;
  
  

•   CS_UNLOCK(drvdata->base);
  

•   CS_UNLOCK(csa);
  
    /* Setting the prog bit disables tracing immediately */
    etm_set_prog(drvdata);
  

@@ -608,7 +613,7 @@ static void etm_disable_perf(struct coresight_device *csdev) etm_set_pwrdwn(drvdata); coresight_disclaim_device_unlocked(csdev);

•   CS_LOCK(drvdata->base);
  

•   CS_LOCK(csa);
  

}

static void etm_disable_sysfs(struct coresight_device *csdev) @@ -739,11 +744,12 @@ static void etm_init_arch_data(void *info) u32 etmidr; u32 etmccr; struct etm_drvdata *drvdata = info;

•   struct csdev_access csa = CSDEV_ACCESS_IOMEM(drvdata->base);
  
    /* Make sure all registers are accessible */
    etm_os_unlock(drvdata);
  
  

•   CS_UNLOCK(drvdata->base);
  

•   CS_UNLOCK(&csa);
  
    /* First dummy read */
    (void)etm_readl(drvdata, ETMPDSR);
  

@@ -776,7 +782,7 @@ static void etm_init_arch_data(void *info)

    etm_set_pwrdwn(drvdata);
    etm_clr_pwrup(drvdata);

•   CS_LOCK(drvdata->base);
  

•   CS_LOCK(&csa);
  

}

static void etm_init_trace_id(struct etm_drvdata *drvdata) diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index 5b81d6f12027..40d242d14ffa 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -111,7 +111,7 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) struct device *etm_dev = &csdev->dev; struct csdev_access *csa = &csdev->access;

•   CS_UNLOCK(drvdata->base);
  

•   CS_UNLOCK(csa);
  
    etm4_os_unlock(drvdata);
  
  

@@ -222,7 +222,7 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) isb();

done:

•   CS_LOCK(drvdata->base);
  

•   CS_LOCK(csa);
  
    dev_dbg(etm_dev, "cpu: %d enable smp call done: %d\n",
            drvdata->cpu, rc);
  

@@ -479,7 +479,7 @@ static void etm4_disable_hw(void *info) struct csdev_access *csa = &csdev->access; int i;

•   CS_UNLOCK(drvdata->base);
  

•   CS_UNLOCK(csa);
  
    if (!drvdata->skip_power_up) {
            /* power can be removed from the trace unit now */
  

@@ -521,7 +521,7 @@ static void etm4_disable_hw(void *info)

    coresight_disclaim_device_unlocked(csdev);

•   CS_LOCK(drvdata->base);
  

•   CS_LOCK(csa);
  
    dev_dbg(&drvdata->csdev->dev,
            "cpu: %d disable smp call done\n", drvdata->cpu);
  

@@ -626,11 +626,12 @@ static void etm4_init_arch_data(void *info) u32 etmidr5; struct etmv4_drvdata *drvdata = info; int i;

•   struct csdev_access csa = CSDEV_ACCESS_IOMEM(drvdata->base);
  
    /* Make sure all registers are accessible */
    etm4_os_unlock(drvdata);
  
  

•   CS_UNLOCK(drvdata->base);
  

•   CS_UNLOCK(&csa);
  
    /* find all capabilities of the tracing unit */
    etmidr0 = readl_relaxed(drvdata->base + TRCIDR0);
  

@@ -784,7 +785,7 @@ static void etm4_init_arch_data(void *info) drvdata->nrseqstate = BMVAL(etmidr5, 25, 27); /* NUMCNTR, bits[30:28] number of counters available for tracing */ drvdata->nr_cntr = BMVAL(etmidr5, 28, 30);

•   CS_LOCK(drvdata->base);
  

•   CS_LOCK(&csa);
  

}

/* Set ELx trace filter access in the TRCVICTLR register */ @@ -1165,7 +1166,7 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata) dsb(sy); isb();

•   CS_UNLOCK(drvdata->base);
  

•   CS_UNLOCK(csa);
  
    /* Lock the OS lock to disable trace and external debugger access */
    etm4_os_lock(drvdata);
  

@@ -1273,7 +1274,7 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata) drvdata->base + TRCPDCR);

out:

•   CS_LOCK(drvdata->base);
  

•   CS_LOCK(csa);
    return ret;
  

}

@@ -1281,8 +1282,14 @@ static void etm4_cpu_restore(struct etmv4_drvdata *drvdata) { int i; struct etmv4_save_state *state = drvdata->save_state;

•   struct coresight_device *csdev = drvdata->csdev;
  

•   struct csdev_access *csa;
  

•   if (WARN_ON(!csdev))
  

•           return;
  
  

•   CS_UNLOCK(drvdata->base);
  

•   csa = &csdev->access;
  

•   CS_UNLOCK(csa);
  
    writel_relaxed(state->trcclaimset, drvdata->base + TRCCLAIMSET);
  
  

@@ -1374,7 +1381,7 @@ static void etm4_cpu_restore(struct etmv4_drvdata *drvdata)

    /* Unlock the OS lock to re-enable trace and external debug access */
    etm4_os_unlock(drvdata);

•   CS_LOCK(drvdata->base);
  

•   CS_LOCK(csa);
  

}

static int etm4_cpu_pm_notify(struct notifier_block *nb, unsigned long cmd, diff --git a/drivers/hwtracing/coresight/coresight-funnel.c b/drivers/hwtracing/coresight/coresight-funnel.c index b3f98ce51a68..5b74dd0d0652 100644 --- a/drivers/hwtracing/coresight/coresight-funnel.c +++ b/drivers/hwtracing/coresight/coresight-funnel.c @@ -53,8 +53,9 @@ static int dynamic_funnel_enable_hw(struct funnel_drvdata *drvdata, int port) u32 functl; int rc = 0; struct coresight_device *csdev = drvdata->csdev;

•   struct csdev_access *csa = &drvdata->csdev->access;
  
  

•   CS_UNLOCK(drvdata->base);
  

•   CS_UNLOCK(csa);
  
    functl = readl_relaxed(drvdata->base + FUNNEL_FUNCTL);
    /* Claim the device only when we enable the first slave */
  

@@ -70,7 +71,7 @@ static int dynamic_funnel_enable_hw(struct funnel_drvdata *drvdata, int port) writel_relaxed(functl, drvdata->base + FUNNEL_FUNCTL); writel_relaxed(drvdata->priority, drvdata->base + FUNNEL_PRICTL); done:

•   CS_LOCK(drvdata->base);
  

•   CS_LOCK(csa);
    return rc;
  

}

@@ -103,8 +104,9 @@ static void dynamic_funnel_disable_hw(struct funnel_drvdata *drvdata, { u32 functl; struct coresight_device *csdev = drvdata->csdev;

•   struct csdev_access *csa = &drvdata->csdev->access;
  
  

•   CS_UNLOCK(drvdata->base);
  

•   CS_UNLOCK(csa);
  
    functl = readl_relaxed(drvdata->base + FUNNEL_FUNCTL);
    functl &= ~(1 << inport);
  

@@ -114,7 +116,7 @@ static void dynamic_funnel_disable_hw(struct funnel_drvdata *drvdata, if (!(functl & FUNNEL_ENSx_MASK)) coresight_disclaim_device_unlocked(csdev);

•   CS_LOCK(drvdata->base);
  

•   CS_LOCK(csa);
  

}

static void funnel_disable(struct coresight_device *csdev, int inport, @@ -174,10 +176,11 @@ static DEVICE_ATTR_RW(priority); static u32 get_funnel_ctrl_hw(struct funnel_drvdata *drvdata) { u32 functl;

•   struct csdev_access *csa = &drvdata->csdev->access;
  
  

•   CS_UNLOCK(drvdata->base);
  

•   CS_UNLOCK(csa);
    functl = readl_relaxed(drvdata->base + FUNNEL_FUNCTL);
  

•   CS_LOCK(drvdata->base);
  

•   CS_LOCK(csa);
  
    return functl;
  

} diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtracing/coresight/coresight-priv.h index f2dc625ea585..a87ce11a0ea6 100644 --- a/drivers/hwtracing/coresight/coresight-priv.h +++ b/drivers/hwtracing/coresight/coresight-priv.h @@ -108,19 +108,20 @@ static inline void coresight_insert_barrier_packet(void *buf) }

-static inline void CS_LOCK(void __iomem *addr) +static inline void CS_LOCK(struct csdev_access *csa) { do { /* Wait for things to settle */ mb();

•           writel_relaxed(0x0, addr + CORESIGHT_LAR);
  

•           csdev_access_relaxed_write32(csa, 0x0, CORESIGHT_LAR);
    } while (0);
  

}

-static inline void CS_UNLOCK(void __iomem *addr) +static inline void CS_UNLOCK(struct csdev_access *csa) { do {

•           writel_relaxed(CORESIGHT_UNLOCK, addr + CORESIGHT_LAR);
  

•           csdev_access_relaxed_write32(csa, CORESIGHT_UNLOCK,
  

•                                     CORESIGHT_LAR);
            /* Make sure everyone has seen this */
            mb();
    } while (0);
  

diff --git a/drivers/hwtracing/coresight/coresight-replicator.c b/drivers/hwtracing/coresight/coresight-replicator.c index b8361bb808f1..b9b40822f3aa 100644 --- a/drivers/hwtracing/coresight/coresight-replicator.c +++ b/drivers/hwtracing/coresight/coresight-replicator.c @@ -46,12 +46,12 @@ struct replicator_drvdata { static void dynamic_replicator_reset(struct replicator_drvdata *drvdata) { struct coresight_device *csdev = drvdata->csdev;

•   CS_UNLOCK(drvdata->base);
  

•   struct csdev_access *csa = &csdev->access;
  
    if (WARN_ON(!csdev))
            return;
  
  

•   CS_UNLOCK(drvdata->base);
  

•   CS_UNLOCK(csa);
  
    if (!coresight_claim_device_unlocked(csdev)) {
            writel_relaxed(0xff, drvdata->base + REPLICATOR_IDFILTER0);
  

@@ -59,7 +59,7 @@ static void dynamic_replicator_reset(struct replicator_drvdata *drvdata) coresight_disclaim_device_unlocked(csdev); }

•   CS_LOCK(drvdata->base);
  

•   CS_LOCK(csa);
  

}

/* @@ -77,8 +77,9 @@ static int dynamic_replicator_enable(struct replicator_drvdata *drvdata, int rc = 0; u32 id0val, id1val; struct coresight_device *csdev = drvdata->csdev;

•   struct csdev_access *csa = &csdev->access;
  
  

•   CS_UNLOCK(drvdata->base);
  

•   CS_UNLOCK(csa);
  
    id0val = readl_relaxed(drvdata->base + REPLICATOR_IDFILTER0);
    id1val = readl_relaxed(drvdata->base + REPLICATOR_IDFILTER1);
  

@@ -113,7 +114,7 @@ static int dynamic_replicator_enable(struct replicator_drvdata *drvdata, writel_relaxed(id1val, drvdata->base + REPLICATOR_IDFILTER1); }

•   CS_LOCK(drvdata->base);
  

•   CS_LOCK(csa);
  
    return rc;
  

} @@ -148,6 +149,7 @@ static void dynamic_replicator_disable(struct replicator_drvdata *drvdata, { u32 reg; struct coresight_device *csdev = drvdata->csdev;

•   struct csdev_access *csa = &csdev->access;
  
    switch (outport) {
    case 0:
  

@@ -161,7 +163,7 @@ static void dynamic_replicator_disable(struct replicator_drvdata *drvdata, return; }

•   CS_UNLOCK(drvdata->base);
  

•   CS_UNLOCK(csa);
  
    /* disable the flow of ATB data through port */
    writel_relaxed(0xff, drvdata->base + reg);
  

@@ -169,7 +171,7 @@ static void dynamic_replicator_disable(struct replicator_drvdata *drvdata, if ((readl_relaxed(drvdata->base + REPLICATOR_IDFILTER0) == 0xff) && (readl_relaxed(drvdata->base + REPLICATOR_IDFILTER1) == 0xff)) coresight_disclaim_device_unlocked(csdev);

•   CS_LOCK(drvdata->base);
  

•   CS_LOCK(csa);
  

}

static void replicator_disable(struct coresight_device *csdev, int inport, diff --git a/drivers/hwtracing/coresight/coresight-stm.c b/drivers/hwtracing/coresight/coresight-stm.c index 9667c5c8f433..ddf90c76284c 100644 --- a/drivers/hwtracing/coresight/coresight-stm.c +++ b/drivers/hwtracing/coresight/coresight-stm.c @@ -148,7 +148,9 @@ struct stm_drvdata {

static void stm_hwevent_enable_hw(struct stm_drvdata *drvdata) {

•   CS_UNLOCK(drvdata->base);
  

•   struct csdev_access *csa = &drvdata->csdev->access;
  

•   CS_UNLOCK(csa);
  
    writel_relaxed(drvdata->stmhebsr, drvdata->base + STMHEBSR);
    writel_relaxed(drvdata->stmheter, drvdata->base + STMHETER);
  

@@ -157,29 +159,33 @@ static void stm_hwevent_enable_hw(struct stm_drvdata *drvdata) 0x04, /* Error detection on event tracing */ drvdata->base + STMHEMCR);

•   CS_LOCK(drvdata->base);
  

•   CS_LOCK(csa);
  

}

static void stm_port_enable_hw(struct stm_drvdata *drvdata) {

•   CS_UNLOCK(drvdata->base);
  

•   struct csdev_access *csa = &drvdata->csdev->access;
  

•   CS_UNLOCK(csa);
    /* ATB trigger enable on direct writes to TRIG locations */
    writel_relaxed(0x10,
                   drvdata->base + STMSPTRIGCSR);
    writel_relaxed(drvdata->stmspscr, drvdata->base + STMSPSCR);
    writel_relaxed(drvdata->stmsper, drvdata->base + STMSPER);
  
  

•   CS_LOCK(drvdata->base);
  

•   CS_LOCK(csa);
  

}

static void stm_enable_hw(struct stm_drvdata *drvdata) {

•   struct csdev_access *csa = &drvdata->csdev->access;
  

•   if (drvdata->stmheer)
            stm_hwevent_enable_hw(drvdata);
  
    stm_port_enable_hw(drvdata);
  
  

•   CS_UNLOCK(drvdata->base);
  

•   CS_UNLOCK(csa);
  
    /* 4096 byte between synchronisation packets */
    writel_relaxed(0xFFF, drvdata->base + STMSYNCR);
  

@@ -188,7 +194,7 @@ static void stm_enable_hw(struct stm_drvdata *drvdata) 0x01), /* global STM enable */ drvdata->base + STMTCSR);

•   CS_LOCK(drvdata->base);
  

•   CS_LOCK(csa);
  

}

static int stm_enable(struct coresight_device *csdev, @@ -218,36 +224,41 @@ static int stm_enable(struct coresight_device *csdev,

static void stm_hwevent_disable_hw(struct stm_drvdata *drvdata) {

•   CS_UNLOCK(drvdata->base);
  

•   struct csdev_access *csa = &drvdata->csdev->access;
  

•   CS_UNLOCK(csa);
  
    writel_relaxed(0x0, drvdata->base + STMHEMCR);
    writel_relaxed(0x0, drvdata->base + STMHEER);
    writel_relaxed(0x0, drvdata->base + STMHETER);
  
  

•   CS_LOCK(drvdata->base);
  

•   CS_LOCK(csa);
  

}

static void stm_port_disable_hw(struct stm_drvdata *drvdata) {

•   CS_UNLOCK(drvdata->base);
  

•   struct csdev_access *csa = &drvdata->csdev->access;
  

•   CS_UNLOCK(csa);
  
    writel_relaxed(0x0, drvdata->base + STMSPER);
    writel_relaxed(0x0, drvdata->base + STMSPTRIGCSR);
  
  

•   CS_LOCK(drvdata->base);
  

•   CS_LOCK(csa);
  

}

static void stm_disable_hw(struct stm_drvdata *drvdata) { u32 val;

•   struct csdev_access *csa = &drvdata->csdev->access;
  
  

•   CS_UNLOCK(drvdata->base);
  

•   CS_UNLOCK(csa);
  
    val = readl_relaxed(drvdata->base + STMTCSR);
    val &= ~0x1; /* clear global STM enable [0] */
    writel_relaxed(val, drvdata->base + STMTCSR);
  
  

•   CS_LOCK(drvdata->base);
  

•   CS_LOCK(csa);
  
    stm_port_disable_hw(drvdata);
    if (drvdata->stmheer)
  

@@ -538,6 +549,8 @@ static ssize_t port_select_store(struct device *dev, const char *buf, size_t size) { struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);

•   struct csdev_access *csa = &drvdata->csdev->access;
  

•   unsigned long val, stmsper;
    int ret = 0;
  
  

@@ -549,13 +562,13 @@ static ssize_t port_select_store(struct device *dev, drvdata->stmspscr = val;

    if (local_read(&drvdata->mode)) {

•           CS_UNLOCK(drvdata->base);
  

•           CS_UNLOCK(csa);
            /* Process as per ARM's TRM recommendation */
            stmsper = readl_relaxed(drvdata->base + STMSPER);
            writel_relaxed(0x0, drvdata->base + STMSPER);
            writel_relaxed(drvdata->stmspscr, drvdata->base + STMSPSCR);
            writel_relaxed(stmsper, drvdata->base + STMSPER);
  

•           CS_LOCK(drvdata->base);
  

•           CS_LOCK(csa);
    }
    spin_unlock(&drvdata->spinlock);
  
  

@@ -585,6 +598,7 @@ static ssize_t port_enable_store(struct device *dev, const char *buf, size_t size) { struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);

•   struct csdev_access *csa = &drvdata->csdev->access;
    unsigned long val;
    int ret = 0;
  
  

@@ -596,9 +610,9 @@ static ssize_t port_enable_store(struct device *dev, drvdata->stmsper = val;

    if (local_read(&drvdata->mode)) {

•           CS_UNLOCK(drvdata->base);
  

•           CS_UNLOCK(csa);
            writel_relaxed(drvdata->stmsper, drvdata->base + STMSPER);
  

•           CS_LOCK(drvdata->base);
  

•           CS_LOCK(csa);
    }
    spin_unlock(&drvdata->spinlock);
  
  

diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c index 610a494efbbc..05f65bd08cb1 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c @@ -18,7 +18,9 @@ static int tmc_set_etf_buffer(struct coresight_device *csdev,

static void __tmc_etb_enable_hw(struct tmc_drvdata *drvdata) {

•   CS_UNLOCK(drvdata->base);
  

•   struct csdev_access *csa = &drvdata->csdev->access;
  

•   CS_UNLOCK(csa);
  
    /* Wait for TMCSReady bit to be set */
    tmc_wait_for_tmcready(drvdata);
  

@@ -32,7 +34,7 @@ static void __tmc_etb_enable_hw(struct tmc_drvdata *drvdata) writel_relaxed(drvdata->trigger_cntr, drvdata->base + TMC_TRG); tmc_enable_hw(drvdata);

•   CS_LOCK(drvdata->base);
  

•   CS_LOCK(csa);
  

}

static int tmc_etb_enable_hw(struct tmc_drvdata *drvdata) @@ -71,7 +73,9 @@ static void tmc_etb_dump_hw(struct tmc_drvdata *drvdata)

static void __tmc_etb_disable_hw(struct tmc_drvdata *drvdata) {

•   CS_UNLOCK(drvdata->base);
  

•   struct csdev_access *csa = &drvdata->csdev->access;
  

•   CS_UNLOCK(csa);
  
    tmc_flush_and_stop(drvdata);
    /*
  

@@ -82,7 +86,7 @@ static void __tmc_etb_disable_hw(struct tmc_drvdata *drvdata) tmc_etb_dump_hw(drvdata); tmc_disable_hw(drvdata);

•   CS_LOCK(drvdata->base);
  

•   CS_LOCK(csa);
  

}

static void tmc_etb_disable_hw(struct tmc_drvdata *drvdata) @@ -93,7 +97,9 @@ static void tmc_etb_disable_hw(struct tmc_drvdata *drvdata)

static void __tmc_etf_enable_hw(struct tmc_drvdata *drvdata) {

•   CS_UNLOCK(drvdata->base);
  

•   struct csdev_access *csa = &drvdata->csdev->access;
  

•   CS_UNLOCK(csa);
  
    /* Wait for TMCSReady bit to be set */
    tmc_wait_for_tmcready(drvdata);
  

@@ -104,7 +110,7 @@ static void __tmc_etf_enable_hw(struct tmc_drvdata *drvdata) writel_relaxed(0x0, drvdata->base + TMC_BUFWM); tmc_enable_hw(drvdata);

•   CS_LOCK(drvdata->base);
  

•   CS_LOCK(csa);
  

}

static int tmc_etf_enable_hw(struct tmc_drvdata *drvdata) @@ -121,13 +127,14 @@ static int tmc_etf_enable_hw(struct tmc_drvdata *drvdata) static void tmc_etf_disable_hw(struct tmc_drvdata *drvdata) { struct coresight_device *csdev = drvdata->csdev;

•   struct csdev_access *csa = &csdev->access;
  
  

•   CS_UNLOCK(drvdata->base);
  

•   CS_UNLOCK(csa);
  
    tmc_flush_and_stop(drvdata);
    tmc_disable_hw(drvdata);
    coresight_disclaim_device_unlocked(csdev);
  

•   CS_LOCK(drvdata->base);
  

•   CS_LOCK(csa);
  

}

/* @@ -452,6 +459,7 @@ static unsigned long tmc_update_etf_buffer(struct coresight_device *csdev, unsigned long offset, to_read = 0, flags; struct cs_buffers *buf = sink_config; struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);

•   struct csdev_access *csa = &csdev->access;
  
    if (!buf)
            return 0;
  

@@ -466,7 +474,7 @@ static unsigned long tmc_update_etf_buffer(struct coresight_device *csdev, if (atomic_read(csdev->refcnt) != 1) goto out;

•   CS_UNLOCK(drvdata->base);
  

•   CS_UNLOCK(csa);
  
    tmc_flush_and_stop(drvdata);
  
  

@@ -551,7 +559,7 @@ static unsigned long tmc_update_etf_buffer(struct coresight_device *csdev, if (buf->snapshot) handle->head += to_read;

•   CS_LOCK(drvdata->base);
  

•   CS_LOCK(csa);
  

out: spin_unlock_irqrestore(&drvdata->spinlock, flags);

diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index 1aae2405041d..d33b93deefcb 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -952,8 +952,9 @@ static void __tmc_etr_enable_hw(struct tmc_drvdata *drvdata) { u32 axictl, sts; struct etr_buf *etr_buf = drvdata->etr_buf;

•   struct csdev_access *csa = &drvdata->csdev->access;
  
  

•   CS_UNLOCK(drvdata->base);
  

•   CS_UNLOCK(csa);
  
    /* Wait for TMCSReady bit to be set */
    tmc_wait_for_tmcready(drvdata);
  

@@ -995,7 +996,7 @@ static void __tmc_etr_enable_hw(struct tmc_drvdata *drvdata) writel_relaxed(drvdata->trigger_cntr, drvdata->base + TMC_TRG); tmc_enable_hw(drvdata);

•   CS_LOCK(drvdata->base);
  

•   CS_LOCK(csa);
  

}

static int tmc_etr_enable_hw(struct tmc_drvdata *drvdata, @@ -1094,7 +1095,9 @@ static void tmc_etr_sync_sysfs_buf(struct tmc_drvdata *drvdata)

static void __tmc_etr_disable_hw(struct tmc_drvdata *drvdata) {

•   CS_UNLOCK(drvdata->base);
  

•   struct csdev_access *csa = &drvdata->csdev->access;
  

•   CS_UNLOCK(csa);
  
    tmc_flush_and_stop(drvdata);
    /*
  

@@ -1106,7 +1109,7 @@ static void __tmc_etr_disable_hw(struct tmc_drvdata *drvdata)

    tmc_disable_hw(drvdata);

•   CS_LOCK(drvdata->base);
  

•   CS_LOCK(csa);
  
  

}

@@ -1482,6 +1485,7 @@ tmc_update_etr_buffer(struct coresight_device *csdev, struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); struct etr_perf_buffer *etr_perf = config; struct etr_buf *etr_buf = etr_perf->etr_buf;

•   struct csdev_access *csa = &csdev->access;
  
    spin_lock_irqsave(&drvdata->spinlock, flags);
  
  

@@ -1497,12 +1501,12 @@ tmc_update_etr_buffer(struct coresight_device *csdev, goto out; }

•   CS_UNLOCK(drvdata->base);
  

•   CS_UNLOCK(csa);
  
    tmc_flush_and_stop(drvdata);
    tmc_sync_etr_buf(drvdata);
  
  

•   CS_LOCK(drvdata->base);
  

•   CS_LOCK(csa);
    spin_unlock_irqrestore(&drvdata->spinlock, flags);
  
    lost = etr_buf->full;
  

diff --git a/drivers/hwtracing/coresight/coresight-tpiu.c b/drivers/hwtracing/coresight/coresight-tpiu.c index 7dd8300cf6be..dd38be482c21 100644 --- a/drivers/hwtracing/coresight/coresight-tpiu.c +++ b/drivers/hwtracing/coresight/coresight-tpiu.c @@ -62,11 +62,11 @@ struct tpiu_drvdata {

static void tpiu_enable_hw(struct csdev_access *csa) {

•   CS_UNLOCK(csa->base);
  

•   CS_UNLOCK(csa);
  
    /* TODO: fill this up */
  
  

•   CS_LOCK(csa->base);
  

•   CS_LOCK(csa);
  

}

static int tpiu_enable(struct coresight_device *csdev, u32 mode, void *__unused) @@ -79,7 +79,8 @@ static int tpiu_enable(struct coresight_device *csdev, u32 mode, void *__unused)

static void tpiu_disable_hw(struct csdev_access *csa) {

•   CS_UNLOCK(csa->base);
  

•   CS_UNLOCK(csa);
  
    /* Clear formatter and stop on flush */
    csdev_access_relaxed_write32(csa, FFCR_STOP_FI, TPIU_FFCR);
  

@@ -90,7 +91,7 @@ static void tpiu_disable_hw(struct csdev_access *csa) /* Wait for formatter to stop */ coresight_timeout(csa, TPIU_FFSR, FFSR_FT_STOPPED_BIT, 1);

•   CS_LOCK(csa->base);
  

•   CS_LOCK(csa);
  

}

static int tpiu_disable(struct coresight_device *csdev) diff --git a/drivers/hwtracing/coresight/coresight.c b/drivers/hwtracing/coresight/coresight.c index 7545a22769c4..64353ee0a2bc 100644 --- a/drivers/hwtracing/coresight/coresight.c +++ b/drivers/hwtracing/coresight/coresight.c @@ -192,9 +192,9 @@ int coresight_claim_device(struct coresight_device *csdev) if (WARN_ON(!csdev)) return -EINVAL;

•   CS_UNLOCK(csdev->access.base);
  

•   CS_UNLOCK(&csdev->access);
    rc = coresight_claim_device_unlocked(csdev);
  

•   CS_LOCK(csdev->access.base);
  

•   CS_LOCK(&csdev->access);
  
    return rc;
  

} @@ -225,9 +225,9 @@ void coresight_disclaim_device(struct coresight_device *csdev) if (WARN_ON(!csdev)) return;

•   CS_UNLOCK(csdev->access.base);
  

•   CS_UNLOCK(&csdev->access);
    coresight_disclaim_device_unlocked(csdev);
  

•   CS_LOCK(csdev->access.base);
  

•   CS_LOCK(&csdev->access);
  

}

/* enable or disable an associated CTI device of the supplied CS device */

2.24.1

Reviewed by: Mike Leach mike.leach@linaro.org

-- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK

Hi Mike

On 09/18/2020 04:34 PM, Mike Leach wrote:

Hi Suzuki,

On Fri, 11 Sep 2020 at 09:41, Suzuki K Poulose suzuki.poulose@arm.com wrote:

...

Define the fields of the DEVARCH register for identifying a component as an ETMv4.x unit. Going forward, we use the DEVARCH register for the component identification, rather than the TRCIDR3.

TRCIDR1? - but either way, we are not using this for component ID. For

Sorry, it is TRCIDR1. Got it mixed with the TRCIDR3 for exlevel mask.

the AMBA path component ID is made using CID + PID + optionally if in the table UCI - which includes DEVARCH. TRCIDR1 is simply used to get the architecture version so we can be sure the driver supports it, and can adjust behaviour for version dependent elements.

Correct. The idea is to use the TRCDEVARCH instead of the TRCIDR1 for drvdata->arch. We use drvdata->arch to detect if the ETM is supported. At the moment, we blindly support all ETMv4.x components. With the system instruction support, we want to make sure we use a CoreSight architected register and not an ETM architected one to detect if the component is an ETM.

...

Cc: Mathieu Poirier mathieu.poirier@linaro.org Cc: Mike Leach mike.leach@linaro.org Signed-off-by: Suzuki K Poulose suzuki.poulose@arm.com

---

drivers/hwtracing/coresight/coresight-etm4x.c | 4 ++-- drivers/hwtracing/coresight/coresight-etm4x.h | 18 ++++++++++++++++++ 2 files changed, 20 insertions(+), 2 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index 40f8113191e0..34b27c26591b 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -1598,8 +1598,8 @@ static int etm4_probe(struct amba_device *adev, const struct amba_id *id) static struct amba_cs_uci_id uci_id_etm4[] = { { /* ETMv4 UCI data */

•           .devarch        = 0x47704a13,
  

•           .devarch_mask   = 0xfff0ffff,
  

•           .devarch        = ETM_DEVARCH_ETMv4x_ARCH,
  

•           .devarch_mask   = ETM_DEVARCH_ID_MASK,
             .devtype        = 0x00000013,
  

Perhaps a good time to change this to a #define constant too.

Yes, I can change it.

I assume that if the system access is going to use the coresight architected registers for ID - it should use the same set as the AMBA path - i.e. DEVARCH + DEVTYPE.

I doubt if DEVTYPE is necessary when we are doing a system instruction access from the CPU. The DEVTYPE identifies the component as PE and a trace source. Both of which are implicit with the system instruction access, but is mandatory for an AMBA bus discovery as it is memory mapped. Moreover the TRCDEVTYPE is only accessible from the memory mapped interface and the external debugger interface. (as per ETM TRM).

Thanks for the review.

Suzuki

Hi Suzuki

On Fri, 11 Sep 2020 at 09:41, Suzuki K Poulose suzuki.poulose@arm.com wrote:

An ETM instance may not implement the OS/Software Lock. This is advertised via TRCOSLSR/TRCLSR respectively. Detect the presence of these lock registers and skip the lock/unlock if they are not implemented.

Signed-off-by: Suzuki K Poulose suzuki.poulose@arm.com

drivers/hwtracing/coresight/coresight-etm4x.c | 77 +++++++++++++++---- drivers/hwtracing/coresight/coresight-etm4x.h | 24 +++++- 2 files changed, 83 insertions(+), 18 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index 34b27c26591b..7feb57108bdc 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -95,12 +95,19 @@ void etm4x_sysreg_write(struct csdev_access *csa, } }

+static inline bool etm4_os_lock_implemented(struct etmv4_drvdata *drvdata) +{

•   return drvdata->os_lock_model == ETM_OS_LOCK_IMPLEMENTED;
  

+}

static void etm4_os_unlock_csa(struct etmv4_drvdata *drvdata, struct csdev_access *csa) {

•   /* Writing 0 to TRCOSLAR unlocks the trace registers */
  

•   etm4x_relaxed_write32(csa, 0x0, TRCOSLAR);
  

•   if (etm4_os_lock_implemented(drvdata)) {
  

•           /* Writing 0 to TRCOSLAR unlocks the trace registers */
  

•           etm4x_relaxed_write32(csa, 0x0, TRCOSLAR);
  

•           isb();
  

•   }
    drvdata->os_unlock = true;
  

•   isb();
  

}

static void etm4_os_unlock(struct etmv4_drvdata *drvdata) @@ -115,10 +122,26 @@ static void etm4_os_lock(struct etmv4_drvdata *drvdata) if (WARN_ON(!drvdata->csdev)) return;

•   /* Writing 0x1 to TRCOSLAR locks the trace registers */
  

•   etm4x_relaxed_write32(&drvdata->csdev->access, 0x1, TRCOSLAR);
  

•   if (etm4_os_lock_implemented(drvdata)) {
  

•           /* Writing 0x1 to TRCOSLAR locks the trace registers */
  

•           etm4x_relaxed_write32(&drvdata->csdev->access, 0x1, TRCOSLAR);
  

•           isb();
  

•   }
    drvdata->os_unlock = false;
  

•   isb();
  

+}

+static void etm4_cs_lock(struct etmv4_drvdata *drvdata,

•                    struct csdev_access *csa)
  

+{

•   if (drvdata->sw_lock)
  

•           CS_LOCK(csa);
  

+}

+static void etm4_cs_unlock(struct etmv4_drvdata *drvdata,

•                    struct csdev_access *csa)
  

+{

•   if (drvdata->sw_lock)
  

•           CS_UNLOCK(csa);
  

}

static bool etm4_arch_supported(u8 arch) @@ -160,7 +183,7 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) struct device *etm_dev = &csdev->dev; struct csdev_access *csa = &csdev->access;

•   CS_UNLOCK(csa);
  

•   etm4_cs_unlock(drvdata, csa);
  
    etm4_os_unlock(drvdata);
  
  

@@ -258,7 +281,7 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) isb();

done:

•   CS_LOCK(csa);
  

•   etm4_cs_lock(drvdata, csa);
  
    dev_dbg(etm_dev, "cpu: %d enable smp call done: %d\n",
            drvdata->cpu, rc);
  

@@ -515,7 +538,7 @@ static void etm4_disable_hw(void *info) struct csdev_access *csa = &csdev->access; int i;

•   CS_UNLOCK(csa);
  

•   etm4_cs_unlock(drvdata, csa);
  
    if (!drvdata->skip_power_up) {
            /* power can be removed from the trace unit now */
  

@@ -557,7 +580,7 @@ static void etm4_disable_hw(void *info)

    coresight_disclaim_device_unlocked(csdev);

•   CS_LOCK(csa);
  

•   etm4_cs_lock(drvdata, csa);
  
    dev_dbg(&drvdata->csdev->dev,
            "cpu: %d disable smp call done\n", drvdata->cpu);
  

@@ -652,6 +675,20 @@ static const struct coresight_ops etm4_cs_ops = { .source_ops = &etm4_source_ops, };

+/*

• • ETM may or may not implement the Software Lock and the OS Lock.
• • Detect this before we attempt to do any locking.
• */

+static void etm_detect_lock_status(struct etmv4_drvdata *drvdata,

•                              struct csdev_access *csa)
  

+{

•   u32 sw_lsr = etm4x_relaxed_read32(csa, TRCLSR);
  

7.3.48 - ETMv4.5 spec -> TRCLSR accessible only from the memory mapped interface.

•   u32 os_lsr = etm4x_relaxed_read32(csa, TRCOSLSR);
  

This is unneeded. 7.3.50 of the ETM4.5 spec says for OS lock bits "always 0b10 for Armv8-A/R, Armv7-A/R,". So always implemented.

•   drvdata->sw_lock = TRCLSR_SLI(sw_lsr);
  

•   drvdata->os_lock_model = TRCOSLSR_OSM(os_lsr);
  

+}

static void etm4_init_arch_data(void *info) { u32 etmidr0; @@ -664,10 +701,15 @@ static void etm4_init_arch_data(void *info) int i; struct csdev_access csa = CSDEV_ACCESS_IOMEM(drvdata->base);

•   /*
  

•    * We must check if the locks are implemented
  

•    * as early as possible.
  

•    */
  

•   etm_detect_lock_status(drvdata, &csa);
  

•   /* Make sure all registers are accessible */
    etm4_os_unlock_csa(drvdata, &csa);
  

•   CS_UNLOCK(&csa);
  

•   etm4_cs_unlock(drvdata, &csa);
  
    /* find all capabilities of the tracing unit */
    etmidr0 = etm4x_relaxed_read32(&csa, TRCIDR0);
  

@@ -821,7 +863,8 @@ static void etm4_init_arch_data(void *info) drvdata->nrseqstate = BMVAL(etmidr5, 25, 27); /* NUMCNTR, bits[30:28] number of counters available for tracing */ drvdata->nr_cntr = BMVAL(etmidr5, 28, 30);

•   CS_LOCK(&csa);
  

•   etm4_cs_lock(drvdata, &csa);
  

}

/* Set ELx trace filter access in the TRCVICTLR register */ @@ -1202,7 +1245,7 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata) dsb(sy); isb();

•   CS_UNLOCK(csa);
  

•   etm4_cs_unlock(drvdata, csa);
  
    /* Lock the OS lock to disable trace and external debugger access */
    etm4_os_lock(drvdata);
  

@@ -1309,7 +1352,7 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata) etm4x_relaxed_write32(csa, (state->trcpdcr & ~TRCPDCR_PU), TRCPDCR);

out:

•   CS_LOCK(csa);
  

•   etm4_cs_lock(drvdata, csa);
    return ret;
  

}

@@ -1324,7 +1367,7 @@ static void etm4_cpu_restore(struct etmv4_drvdata *drvdata) return;

    csa = &csdev->access;

•   CS_UNLOCK(csa);
  

•   etm4_cs_unlock(drvdata, csa);
  
    etm4x_relaxed_write32(csa, state->trcclaimset, TRCCLAIMSET);
  
  

@@ -1404,7 +1447,7 @@ static void etm4_cpu_restore(struct etmv4_drvdata *drvdata)

    /* Unlock the OS lock to re-enable trace and external debug access */
    etm4_os_unlock(drvdata);

•   CS_LOCK(csa);
  

•   etm4_cs_lock(drvdata, csa);
  

}

static int etm4_cpu_pm_notify(struct notifier_block *nb, unsigned long cmd, diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index 29ffad6a5279..efd903688edd 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -417,7 +417,7 @@ if ((csa)->io_mem) \ writel_relaxed((val), (csa)->base + (offset)); \ else \

•                   write_etm4x_sysreg_offset((csa), (val), \
  

•                   write_etm4x_sysreg_offset((csa), (val),         \
                                                (offset), false);   \
    } while (0)
  
  

@@ -541,6 +541,22 @@ /* NS MON (EL3) mode never implemented */ #define ETM_EXLEVEL_NS_VICTLR_MASK GENMASK(22, 20)

+/*

• • TRCOSLSR.OSM - Bit[3,0]
• • 0b00 - Trace OS Lock is not implemented.
• • 0b10 - Trace OS Lock is implemented.
• */

+#define TRCOSLSR_OSM(x) ((((x) & BIT(3)) >> 2) | ((x) & BIT(0))) +#define ETM_OS_LOCK_IMPLEMENTED 0b10

As per my comment above - can be dropped as always implemented.

+/*

• • TRCLSR.SLI - Bit[0]
• • 0b0 - Software Lock is not implemented.
• • 0b1 - Software Lock is implmented.
• */

+#define TRCLSR_SLI(x) ((x) & BIT(0))

/**

• struct etmv4_config - configuration information related to an ETMv4
• @mode: Controls various modes supported by this ETM.

@@ -726,6 +742,10 @@ struct etmv4_save_state {

•         supported for the corresponding Exception level.
  

• @ns_ex_level:In non-secure state, indicates whether instruction tracing is

•         supported for the corresponding Exception level.
  

• • @sw_lock: Cached value of TRCLSR.SLI, tells you whether the software lock

• •         is implemented.
    

• • @os_lock_model: Cached value of TRCOSLSR.OSM, tells you whether OS lock

• •         is implemented.
    

  • @sticky_enable: true if ETM base configuration has been done.
  • @boot_enable:True if we should start tracing at boot time.
  • @os_unlock: True if access to management registers is allowed.

@@ -782,6 +802,8 @@ struct etmv4_drvdata { u8 s_ex_level; u8 ns_ex_level; u8 q_support;

•   u8                              sw_lock;
  

•   u8                              os_lock_model;
    bool                            sticky_enable;
    bool                            boot_enable;
    bool                            os_unlock;
  

-- 2.24.1

Regards

Mike -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK

On 09/18/2020 04:35 PM, Mike Leach wrote:

On Fri, 11 Sep 2020 at 09:41, Suzuki K Poulose suzuki.poulose@arm.com wrote:

...

We rely on the ETM architecture version to decide whether Secure EL2 is available on the CPU for excluding the level for address comparators and viewinst main control register. We must instead use the TRCDIDR3.EXLEVEL_S field to detect the supported levels.

Signed-off-by: Suzuki K Poulose suzuki.poulose@arm.com

drivers/hwtracing/coresight/coresight-etm4x.c | 13 +++---------- drivers/hwtracing/coresight/coresight-etm4x.h | 6 ++++-- 2 files changed, 7 insertions(+), 12 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index 7feb57108bdc..439e9da41006 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -758,7 +758,6 @@ static void etm4_init_arch_data(void *info) * TRCARCHMAJ, bits[11:8] architecture major versin number */ drvdata->arch = BMVAL(etmidr1, 4, 11);

•   drvdata->config.arch = drvdata->arch;
  
     /* maximum size of resources */
     etmidr2 = etm4x_relaxed_read32(&csa, TRCIDR2);
  

@@ -774,6 +773,7 @@ static void etm4_init_arch_data(void *info) drvdata->ccitmin = BMVAL(etmidr3, 0, 11); /* EXLEVEL_S, bits[19:16] Secure state instruction tracing */ drvdata->s_ex_level = BMVAL(etmidr3, 16, 19);

•   drvdata->config.s_ex_level = drvdata->s_ex_level;
     /* EXLEVEL_NS, bits[23:20] Non-secure state instruction tracing */
     drvdata->ns_ex_level = BMVAL(etmidr3, 20, 23);
  
  

@@ -935,16 +935,9 @@ static u64 etm4_get_ns_access_type(struct etmv4_config *config) static u64 etm4_get_access_type(struct etmv4_config *config) { u64 access_type = etm4_get_ns_access_type(config);

•   u64 s_hyp = (config->arch & 0x0f) >= 0x4 ? ETM_EXLEVEL_S_HYP : 0;
  
  

•   /*
  

•    * EXLEVEL_S, bits[11:8], don't trace anything happening
  

•    * in secure state.
  

•    */
  

•   access_type |= (ETM_EXLEVEL_S_APP       |
  

•                   ETM_EXLEVEL_S_OS        |
  

•                   s_hyp                   |
  

•                   ETM_EXLEVEL_S_MON);
  

•   /* All supported secure ELs are excluded */
  

•   access_type |= (u64)config->s_ex_level << TRCACATR_EXLEVEL_SHIFT;
  
  

What is the << TRCACATR_EXLEVEL_SHIFT doing here?

The config->s_ex_level is the EXLVEL mask from the TRCIDR3 shifted to bit 0, as above. We need to make sure that we use the mask in the correct position for TRCACATR register. Basically, we simply exclude all the secure levels supported by the ETM.

...

     return access_type;

} diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index efd903688edd..407ad6647f36 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -522,6 +522,8 @@ /* PowerDown Control Register bits */ #define TRCPDCR_PU BIT(3)

+#define TRCACATR_EXLEVEL_SHIFT 8

• /* secure state access levels - TRCACATRn */ #define ETM_EXLEVEL_S_APP BIT(8) #define ETM_EXLEVEL_S_OS BIT(9)

@@ -604,7 +606,7 @@

• @vmid_mask0: VM ID comparator mask for comparator 0-3.
• @vmid_mask1: VM ID comparator mask for comparator 4-7.
• @ext_inp: External input selection.

• • @arch: ETM architecture version (for arch dependent config).

• • @s_ex_level: Secure ELs where tracing is supported.
  */ struct etmv4_config { u32 mode;

@@ -648,7 +650,7 @@ struct etmv4_config { u32 vmid_mask0; u32 vmid_mask1; u32 ext_inp;

•   u8                              arch;
  

•   u8                              s_ex_level;
  

  };

  /**

-- 2.24.1

Perhaps this patch could be combined with the next patch as it operates on the same set of flags.

I agree that they both deal with the same set of masks. However, functionally they have separate purposes.

1) This patch disconnects the usage of drvdata->arch field to determine the secure exception level mask. This is more of a correctness, as a given v4.4 implementation may not have a Secure EL2.

2) The next patch cleans up the way we define and use all the exception level masks, both secure and non-secure.

I understand that the subjects are quite similar. I could try to fix the subject for this one to make (1) more explicit. This way it is more easier to review.

Suzuki

Hi Mike,

On 09/22/2020 01:47 PM, Mike Leach wrote:

Hi Suzuki,

...

...

...

@@ -935,16 +935,9 @@ static u64 etm4_get_ns_access_type(struct etmv4_config *config) static u64 etm4_get_access_type(struct etmv4_config *config) { u64 access_type = etm4_get_ns_access_type(config);

•   u64 s_hyp = (config->arch & 0x0f) >= 0x4 ? ETM_EXLEVEL_S_HYP : 0;
  
  

•   /*
  

•    * EXLEVEL_S, bits[11:8], don't trace anything happening
  

•    * in secure state.
  

•    */
  

•   access_type |= (ETM_EXLEVEL_S_APP       |
  

•                   ETM_EXLEVEL_S_OS        |
  

•                   s_hyp                   |
  

•                   ETM_EXLEVEL_S_MON);
  

•   /* All supported secure ELs are excluded */
  

•   access_type |= (u64)config->s_ex_level << TRCACATR_EXLEVEL_SHIFT;
  
  

What is the << TRCACATR_EXLEVEL_SHIFT doing here?

The config->s_ex_level is the EXLVEL mask from the TRCIDR3 shifted to bit 0, as above. We need to make sure that we use the mask in the correct position for TRCACATR register. Basically, we simply exclude all the secure levels supported by the ETM.

Sorry, should have been a little more explicit. This breaks the next patch!

...

...

...

      return access_type;

} diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index efd903688edd..407ad6647f36 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -522,6 +522,8 @@ /* PowerDown Control Register bits */ #define TRCPDCR_PU BIT(3)

+#define TRCACATR_EXLEVEL_SHIFT 8

• /* secure state access levels - TRCACATRn */ #define ETM_EXLEVEL_S_APP BIT(8) #define ETM_EXLEVEL_S_OS BIT(9)

@@ -604,7 +606,7 @@ * @vmid_mask0: VM ID comparator mask for comparator 0-3. * @vmid_mask1: VM ID comparator mask for comparator 4-7. * @ext_inp: External input selection.

• • @arch: ETM architecture version (for arch dependent config).

• • @s_ex_level: Secure ELs where tracing is supported. */
  struct etmv4_config { u32 mode;

@@ -648,7 +650,7 @@ struct etmv4_config { u32 vmid_mask0; u32 vmid_mask1; u32 ext_inp;

•   u8                              arch;
  

•   u8                              s_ex_level;
  

  };

  /**

-- 2.24.1

Perhaps this patch could be combined with the next patch as it operates on the same set of flags.

I agree that they both deal with the same set of masks. However, functionally they have separate purposes.

1. This patch disconnects the usage of drvdata->arch field to determine

the secure exception level mask. This is more of a correctness, as a given v4.4 implementation may not have a Secure EL2.

2. The next patch cleans up the way we define and use all the exception level

masks, both secure and non-secure.

Applying this and the next patch which moves to the bits being indexed from 0 for a common reusable field gets you the following code sequence:-