linaro-dev October 2012

linaro-dev@lists.linaro.org

76 participants
108 discussions

2012-10-03 Android Platform Team Meeting Agenda Posted

by Zach Pfeffer

Please take a look at: https://wiki.linaro.org/Platform/Android/Meetings/2012-10-03 Feel free to add to the agenda and join us in #linaro-meeting on irc.freenode.net at 13:00 UTC on 2012/10/03. -- Zach Pfeffer Android Platform Team Lead, Linaro Platform Teams Linaro.org | Open source software for ARM SoCs Follow Linaro: http://www.facebook.com/pages/Linaro http://twitter.com/#!/linaroorg - http://www.linaro.org/linaro-blog

11 years, 7 months

Question: What is the current level of Free Software support by vendors?

by Graeme Russ

Hello, Firstly, sorry if this is the wrong forum - please feel free to re-direct me to a more appropriate place. I've been searching around for the 'net for a while but really have not come across a conclusive answer to just how well the free software community is supported by ARM vendors. Now I know that is a rather vague statement, so I will elaborate by framing it is a personal desire... What I would like is a 'device' which I can hack on (and contribute to the community) with the following features: - Ethernet (at least 100Mb/s, but 1Gb/s and/or WiFi would be a bonus) - USB 2.0 (3.0 would be a bonus) - HDMI (dual monitor support would be a big bonus) - 1080p video output - Hi-definition video codec - SATA - MMC/SD - 3D graphics not a big desire, but would be a bonus Essentially, I'm after a device I can use as a media box / thin-client X-term / hacker platform where every single byte of code that runs on the device is free software. This includes: - Boot loader (including SDRAM init) - Operating system (GNU / Linux would be my personal choice) - All drivers (no binary blobs, no 'firmware' blobs) - All application software I have yet to see such a platform. A lot come close, but it seems to me that most fall short when it comes to drivers for the video codecs. Am I living a pipe-dream, or does such a device really exist? Regards, Graeme

11 years, 7 months

[PATCH 0/3] EXYNOS: Add support for Exynos4x12

by Chander Kashyap

This patch series popultes Register addresses, clock structure and gpio structure for Exynos4x12. Chander Kashyap (3): EXYNOS: EXYNOS4X12: Populate Exynos4x12 register addresses EXYNOS: EXYNOS4X12: Add clock structure for EXYNOS4X12 EXYNOS: EXYNOS4X12: Add gpio structure for EXYNOS4X12 arch/arm/include/asm/arch-exynos/clock.h | 276 ++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-exynos/cpu.h | 48 +++++- arch/arm/include/asm/arch-exynos/gpio.h | 85 +++++++++ 3 files changed, 402 insertions(+), 7 deletions(-) -- 1.7.9.5

11 years, 7 months

[PATCH] EXYNOS: Clock: Add common function for pll rate calculation

by Chander Kashyap

Moved the common code to calculate pll clock rate to new funtion exynos_get_pll_clk(). Signed-off-by: Chander Kashyap <chander.kashyap(a)linaro.org> --- arch/arm/cpu/armv7/exynos/clock.c | 102 ++++++++++++++----------------------- 1 file changed, 38 insertions(+), 64 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 4f3b451..a042423 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -26,41 +26,19 @@ #include <asm/arch/clock.h> #include <asm/arch/clk.h> -/* exynos4: return pll clock frequency */ -static unsigned long exynos4_get_pll_clk(int pllreg) +/* exynos: return pll clock frequency */ +static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k) { - struct exynos4_clock *clk = - (struct exynos4_clock *)samsung_get_base_clock(); - unsigned long r, m, p, s, k = 0, mask, fout; + unsigned long m, p, s = 0, mask, fout; unsigned int freq; - - switch (pllreg) { - case APLL: - r = readl(&clk->apll_con0); - break; - case MPLL: - r = readl(&clk->mpll_con0); - break; - case EPLL: - r = readl(&clk->epll_con0); - k = readl(&clk->epll_con1); - break; - case VPLL: - r = readl(&clk->vpll_con0); - k = readl(&clk->vpll_con1); - break; - default: - printf("Unsupported PLL (%d)\n", pllreg); - return 0; - } - /* * APLL_CON: MIDV [25:16] * MPLL_CON: MIDV [25:16] * EPLL_CON: MIDV [24:16] * VPLL_CON: MIDV [24:16] + * BPLL_CON: MIDV [25:16]: Exynos5 */ - if (pllreg == APLL || pllreg == MPLL) + if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL) mask = 0x3ff; else mask = 0x1ff; @@ -92,13 +70,43 @@ static unsigned long exynos4_get_pll_clk(int pllreg) return fout; } +/* exynos4: return pll clock frequency */ +static unsigned long exynos4_get_pll_clk(int pllreg) +{ + struct exynos4_clock *clk = + (struct exynos4_clock *)samsung_get_base_clock(); + unsigned long r, k = 0; + + switch (pllreg) { + case APLL: + r = readl(&clk->apll_con0); + break; + case MPLL: + r = readl(&clk->mpll_con0); + break; + case EPLL: + r = readl(&clk->epll_con0); + k = readl(&clk->epll_con1); + break; + case VPLL: + r = readl(&clk->vpll_con0); + k = readl(&clk->vpll_con1); + break; + default: + printf("Unsupported PLL (%d)\n", pllreg); + return 0; + } + + return exynos_get_pll_clk(pllreg, r, k); +} + /* exynos5: return pll clock frequency */ static unsigned long exynos5_get_pll_clk(int pllreg) { struct exynos5_clock *clk = (struct exynos5_clock *)samsung_get_base_clock(); - unsigned long r, m, p, s, k = 0, mask, fout; - unsigned int freq, pll_div2_sel, fout_sel; + unsigned long r, k = 0, fout; + unsigned int pll_div2_sel, fout_sel; switch (pllreg) { case APLL: @@ -123,41 +131,7 @@ static unsigned long exynos5_get_pll_clk(int pllreg) return 0; } - /* - * APLL_CON: MIDV [25:16] - * MPLL_CON: MIDV [25:16] - * EPLL_CON: MIDV [24:16] - * VPLL_CON: MIDV [24:16] - * BPLL_CON: MIDV [25:16] - */ - if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL) - mask = 0x3ff; - else - mask = 0x1ff; - - m = (r >> 16) & mask; - - /* PDIV [13:8] */ - p = (r >> 8) & 0x3f; - /* SDIV [2:0] */ - s = r & 0x7; - - freq = CONFIG_SYS_CLK_FREQ; - - if (pllreg == EPLL) { - k = k & 0xffff; - /* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */ - fout = (m + k / 65536) * (freq / (p * (1 << s))); - } else if (pllreg == VPLL) { - k = k & 0xfff; - /* FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV) */ - fout = (m + k / 1024) * (freq / (p * (1 << s))); - } else { - if (s < 1) - s = 1; - /* FOUT = MDIV * FIN / (PDIV * 2^(SDIV - 1)) */ - fout = m * (freq / (p * (1 << (s - 1)))); - } + fout = exynos_get_pll_clk(pllreg, r, k); /* According to the user manual, in EVT1 MPLL and BPLL always gives * 1.6GHz clock, so divide by 2 to get 800MHz MPLL clock.*/ -- 1.7.9.5

11 years, 7 months

[PATCH] ARCH: EXYNOS: add support to match product id

by Chander Kashyap

From: Chander Kashyap <chander.kashyap(a)gmail.com> Based upon single SoC there can be multiple varients. This patch add support to match the complete product ID. Signed-off-by: Chander Kashyap <chander.kashyap(a)linaro.org> --- arch/arm/include/asm/arch-exynos/cpu.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h index 2cd4ae1..2bde10c 100644 --- a/arch/arm/include/asm/arch-exynos/cpu.h +++ b/arch/arm/include/asm/arch-exynos/cpu.h @@ -139,6 +139,15 @@ static inline int cpu_is_##type(void) \ IS_SAMSUNG_TYPE(exynos4, 0x4) IS_SAMSUNG_TYPE(exynos5, 0x5) +#define IS_EXYNOS_TYPE(type, id) \ +static inline int proid_is_##type(void) \ +{ \ + return s5p_cpu_id == id; \ +} + +IS_EXYNOS_TYPE(exynos4210, 0x4210) +IS_EXYNOS_TYPE(exynos5250, 0x5250) + #define SAMSUNG_BASE(device, base) \ static inline unsigned int samsung_get_base_##device(void) \ { \ -- 1.7.9.5

11 years, 7 months

Re: [PATCH v3 2/3] devfreq: Add suspend and resume apis

by MyungJoo Ham

11 years, 7 months

Linaro, Gumstix, and illegal instructions

by Jonathan Kunkee

Hello, I recently acquired a Gumstix Overo Water with a Tobi and decided to put Node.js on it to turn it into a web server of sorts. The build dies with an "Illegal instruction" error, and I am thoroughly confused. In order to set up the build, I did the following: 1. imaged a microSD card with the Linaro binaries indicated by http://wiki.gumstix.org/index.php?title=Installing_Linaro_Image 2. booted 3. dd'd/enabled 200MB of swap on the SD card 4. apt-get update/upgrade everything 5. installed various development dependencies (git, libc6-dev, g++, and many others) 6. cloned Joyent's repo. 7. modified `wscript` in the repo with V8-specific changes for ARM (including enabling hard-float) (modified the scons invocation in v0.8) 8. ./configure 8. make 9. observed 'illegal instruction' death in the make process: /root/node/deps/v8/src/arguments.h: In constructor 'v8::internal::CustomArguments::CustomArguments(v8::internal::Isolate*, v8::internal::Object*, v8::internal::Object*, v8::internal::JSObject*)': /root/node/deps/v8/src/arguments.h:93:65: internal compiler error: Illegal instruction Please submit a full bug report, with preprocessed source if appropriate. See <file:///usr/share/doc/gcc-4.6/README.Bugs> for instructions. The bug is not reproducible, so it is likely a hardware or OS problem. scons: *** [obj/release/runtime-profiler.o] Error 1 scons: building terminated because of errors. If I restart the build, it works fine for a while (including rebuilding the object it died building) then dies again. A different portion of the build is running and it usually receives a segfault: [ 9/35] cxx: src/node_javascript.cc -> out/Release/src/node_javascript_5.o /usr/bin/g++ -pthread -g -O3 -DHAVE_OPENSSL=1 -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -DHAVE_FDATASYNC=1 -DARCH="arm" -DPLATFORM="linux" -D__POSIX__=1 -Wno-unused-parameter -D_FORTIFY_SOURCE=2 -IRelease/src -I../src -IRelease/deps/http_parser -I../deps/http_parser -IRelease/deps/uv/include -I../deps/uv/include -IRelease/deps/uv/src/ares -I../deps/uv/src/ares -IRelease/deps/v8/include -I../deps/v8/include -Ideps/v8/include ../src/node_javascript.cc -c -o Release/src/node_javascript_5.o g++: internal compiler error: Segmentation fault (program as) Please submit a full bug report, with preprocessed source if appropriate. See <file:///usr/share/doc/gcc-4.6/README.Bugs> for instructions. Waf: Leaving directory `/root/node/out' I am confused. I've made a few observations about my setup: * Thinking that it might be a thermal problem because it was under heavy load at 600MHz in open air, I dug out a small heat sink, attached it, and pointed a small fan at it. It now runs cool to the touch. I still get the same 'illegal instruction' deaths under load. * Usually three invocations of 'make' are required before it actually finishes, but it does finish. I can run the command-line interpreter and it seems to behave inasmuch as I've used it. * 'make test' fails, but I think that's a Node.js/ARM problem. * I run htop to monitor the build, and sometimes the build system works fine while htop dies with an 'illegal instruction' error. * Node.js on ARM is presently somewhat sticky, so I checked out the v0.6.6 tag. v0.6.18 encounters the same problem. v0.8.9 simply segfaults instead. * I have an Overo Water (GS3503W-R2889) on a Tobi. * MLO version: I haven't the foggiest, but I get the U-Boot version string twice, once being before u-boot.bin is loaded. * U-Boot 2012.04.01 (Jul 19 2012 - 17:31:34) * I moved the SD card to a different Water/Tobi pair and I got the same error (illegal instruction, Node.js v0.8.9) It feels like a task swapping bug in the kernel. Perhaps it's related to errata on the OMAP3530. It could also be read timeouts from the swap file on the SD card, though dmesg doesn't say anything of the sort. I found a kernel patch regarding inconsistent caches on ARM, but it hit in 2.6.33 and I'm running 3.2.1. Has anyone seen something like this? Would anyone be willing to replicate the problem? I'd be happy to share my tweaks to Node.js' build system to get it to build. Thanks for reading! Jon Kunkee

11 years, 7 months

[PATCH v2 0/3] Delay switch to Non-Secure Hyp until kernel entry

by Dave Martin

The bootwrapper is really doubling as firmware, so it doesn't make sense for it to drop out of the Secure World before getting a chance to parse its parameters and configuration. Instead, it should make sense to delay switching to the Normal World for as long as possible so that we have a chance to do any required firmware-level configuration in the Secure World first. This quick hack is ***completely untested***, since I'm not working with any suitable kernel tree right now. If someone with a KVM tree ready to run could give it a try, that would definitely save me some time. Review also welcome (naturally) Changes since v1: * Don't rely on preservation of lr or sp across enter_hyp (this doesn't work because those registers are banked per-mode). I'm still not convinced this series works, due image/model/dtb mismatches in my testing, but execution at least reaches the kernel now. Cheers ---Dave Dave Martin (3): bootwrapper: Fix misaligned Hyp mode vector table bootwrapper: Refactor entry into Hyp mode to be more reusable bootwrapper: Delay switch to Hyp mode until kernel entry boot.S | 58 +++++++++++++++++++++++++++++++++++++------------------- semi_loader.h | 6 +++- 2 files changed, 42 insertions(+), 22 deletions(-) -- 1.7.4.1 @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ Dave Martin (3): bootwrapper: Fix misaligned Hyp mode vector table bootwrapper: Refactor entry into Hyp mode to be more reusable bootwrapper: Delay switch to Hyp mode until kernel entry boot.S | 58 +++++++++++++++++++++++++++++++++++++------------------- semi_loader.h | 6 +++- 2 files changed, 42 insertions(+), 22 deletions(-) -- 1.7.4.1

11 years, 7 months

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linaro-dev October 2012