userspace access to cache geometry information
r-woodruff2 at ti.com
Sat Oct 16 01:05:02 UTC 2010
> From: linaro-dev-bounces at lists.linaro.org [mailto:linaro-dev-
> bounces at lists.linaro.org] On Behalf Of Peter Maydell
> One of the Valgrind subtools is Cachegrind; this is a cache
> profiler. (It simulates the I1, D1 and L2 caches so it can
> pinpoint the sources of cache misses in application code.)
Part of this info is exported to user space through /proc/cpuinfo
Catalin did post a patch long back to fix up decode for v7. I recall RMK not linking some aspect. The reasons are buried in mail archives. IIRC it had to do with expectations around that interface and the constant churn around he formatting that happened.
There is enough info in cpuinfo you can guess, but you will be wrong due to errata modifications. Also there are a lot of cache options which are changeable. Things like if your using write-alloc or not will change results a lot.
Is it possible on the tool to just have it take input from some config file? If you know your CPU it could fall back and use that information. Getting the cache information from the tool would be cool. If the kernel has some issues getting the info letting the user pick and having a default config would be next best.
... if you look at proc and see v7 and smp you can infer a lot of the configuration and pick a close default.
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