[PATCH 0/5] OMAP4: cache fixes for 4460
santosh.shilimkar at ti.com
Tue Nov 22 12:57:06 UTC 2011
On Tue, Nov 22, 2011 at 6:02 PM, Mans Rullgard <mans.rullgard at linaro.org> wrote:
> On 22 November 2011 05:14, Shilimkar, Santosh <santosh.shilimkar at ti.com> wrote:
>> On Tue, Nov 22, 2011 at 8:15 AM, Mans Rullgard <mans.rullgard at linaro.org> wrote:
>>> These patches fix and tweak various cache settings for the 4460
>>> resulting in a speed increase exceeding 10% in some tests.
>>> Mans Rullgard (5):
>>> OMAP4: apply L2 cache lockdown workaround only on 4460 ES1.0
>> This one is OK though the Panda were suppose to made out of es1.1 and es1.0
>> was not suppose to be supported. The WA is not full proof and you
>> still might see
>> corruption with this. Hence for mainline, we have decided not to push this
> Well, currently the tilt kernel applies this to all 4460 versions,
> twice even. This patch makes it do the right thing on both 1.0 and
I see. If it's for Linaro internal tree it's fine.
>>> OMAP4: enable double linefill on 4460
>> Don't do that. We found a new errata around this recently which
>> demanded to disable the DLF. Signature of the failure is full
>> cache line getting corrupted. The errata should soon go into
>> the ARM documentation. So this one too isn't useful even
>> though it improves benchmarks.
> Do you have an erratum number for this?
This was very recent BUG and not yet made it to the public errata
numbers. Most likely next PL310 errata update should have
this one documented.
>>> OMAP4: fix PL310 prefetch offset setting
>>> OMAP4: set PL310 prefetch offset to 3
>> You can combine above two if possible and it can go
>> to mainline.
>>> OMAP4: do not force workarounds for errata fixed in 4460
>> I agree though with single defconfig (omap2plus), it's hard to
>> have such distinctions since most of the ARM errata WA are
>> static configurations.
> So keep them on by default but allow them to be turned off. In the
> longer term, we should of course try to make these selectively
> applied at runtime whenever possible.
Yep. That's the idea. On internal product kernels we do disable
once which are NA for a chip.
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