[Linaro-mm-sig] Memory region attribute bits and multiple mappings
laurent.pinchart at ideasonboard.com
Wed Apr 20 08:29:06 UTC 2011
On Tuesday 19 April 2011 23:37:48 Rebecca Schultz Zavin wrote:
> On Tue, Apr 19, 2011 at 2:23 PM, Arnd Bergmann <arnd at arndb.de> wrote:
> > On Tuesday 19 April 2011 22:06:50 Rebecca Schultz Zavin wrote:
> > > Hey all,
> > >
> > > While we are working out requirements, I was hoping to get some more
> > > information about another related issue that keeps coming up on mailing
> > > lists and in discussions.
> > Thanks for the summary and getting this started!
> > > ARM has stated that if you have the same physical memory mapped with
> > > two different sets of attribute bits you get undefined behavior. I
> > > think it's going to be a requirement that some of the memory allocated
> > > via the unified memory manager is mapped uncached.
> > This may be a stupid question, but do we have an agreement that it
> > is actually a requirement to have uncached mappings? With the
> > streaming DMA mapping API, it should be possible to work around
> > noncoherent DMA by flushing the caches at the right times, which
> > probably results in better performance than simply doing noncached
> > mappings. What is the specific requirement for noncached memory
> > regions?
> That was my original plan, but our graphics folks and those at our partner
> companies basically have me convinced that the common case is for userspace
> to stream data into memory, say copying an image into a texture, and never
> read from it or touch it again. The alternative will mean a lot of cache
> flushes for small memory regions, in and of itself this becomes a
> performance problem. I think we want to optimize for this case, rather
> than the much less likely case of read-modify-write to these buffers.
Another important use case is image/video capture (V4L2 API), where the device
writes to memory using DMA, and applications read from the memory. Depending
on how applications process captured data, an uncached mapping might impact
We also need to keep in mind that buffers might be passed between different
cores (when compressing video data on a DSP for instance). Even if we map the
memory uncached on the cores running Linux, other cores might still cache the
data by default. This will need to be addressed.
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