[Linaro-mm-sig] [RFC] ARM DMA mapping TODO, v1
pullip.cho at samsung.com
Thu Apr 28 07:24:30 UTC 2011
On Thu, Apr 28, 2011 at 6:45 AM, Benjamin Herrenschmidt
<benh at kernel.crashing.org> wrote:
> Don't you have a risk where speculative loads or prefetches might bring
> back some stuff into the cache via the cachable mapping ? Is that an
> issue ? As long as it's non-dirty and the cachable mapping isn't
> otherwise used, I suppose it might be a non-issue, tho I've seen in
> powerpc land cases of processors that can checkstop if a subsequent non
> cachable access "hits" the stuff that was loaded in the cache.
As far as I know, ARM processors does not have the capability
to detect non-cacheable access hits the stuff in the cache.
IMHO, speculative prefetch becomes a problem
when a coherent buffer (that is not-cacheable in ARM) is modified by a
while old data is already loaded in the cache via another cacheable
mapping onto the buffer
even though it is never touched by CPU.
We can avoid this problem if the kernel removes 'executable' property
from the cacheable mapping.
But it is not able to modify page table entries in the direct mapping area.
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