[ACTIVITY] 5th - 9th March

[Andrew Stubbs]

Committed the 4.6.3 merge to Linaro GCC 4.6.

Merged from FSF 4.5 to Linaro GCC 4.5.

Thought about how to do register-class allocation for NEON v. core 
registers case. Discussed the problem at the GCC performance meeting. 
Lots of interesting discussion was had. I have some interesting 
experiments to do, but the first step needs to be to get my 64-bit 
operator patch to work correctly.

Tried to track down the problems in my NEON-immediates patch. The 
problem is that it's putting constants in different pools in stage 3 to 
what it does in stage 2. Presumably this is something to do with the 
pool-offset attributes in the instruction patterns? My patch has caused 
it to switch from using 'fldd' to using 'vmov' in some cases (the 
instructions are aliases, but it's indicative of a different machine 
description pattern in the compiler), but I don't know why the change 
would be different between the different bootstrap stages? I made some 
alterations to switch it back to `fldd` when it wasn't supposed to 
change, but bootstrap still fails. More investigation required...again.

Rewrote the NEON one's-complement patch and posted it upstream.

Tracked down the cause of the bootstrap failures in my NEON 64-bit 
shifts patch: out-of-range shift amounts were not handled leading to 
ICEs. Reworked the constant shift handling cases, and resumbitted the 
patch for testing. It's failed again. A job for next week.