From de750c3282940b750d82131f9b87390c03bc5904 Mon Sep 17 00:00:00 2001
From: Olivier Martin <olivier.martin@arm.com>
Date: Mon, 20 Feb 2012 19:13:24 +0000
Subject: [PATCH 6/7] SamsungPlatformPkg/SmdkBoardPkg: Removed memory initialization in 'ArmPlatformInitializeBootMemory'

All the memory controllers are already initialized when the SEC/PEI/UEFI phases are started.

Signed-off-by: Olivier Martin <olivier.martin@arm.com>
---
 .../Library/SmdkBoardLib/SmdkBoardHelper.S         |  248 --------------------
 .../Library/SmdkBoardLib/SmdkBoardHelper.asm       |  245 -------------------
 2 files changed, 0 insertions(+), 493 deletions(-)
 mode change 100644 => 100755 SamsungPlatformPkg/SmdkBoardPkg/Library/SmdkBoardLib/SmdkBoardHelper.S
 mode change 100644 => 100755 SamsungPlatformPkg/SmdkBoardPkg/Library/SmdkBoardLib/SmdkBoardHelper.asm

diff --git a/SamsungPlatformPkg/SmdkBoardPkg/Library/SmdkBoardLib/SmdkBoardHelper.S b/SamsungPlatformPkg/SmdkBoardPkg/Library/SmdkBoardLib/SmdkBoardHelper.S
old mode 100644
new mode 100755
index b1af424..46a14d1
--- a/SamsungPlatformPkg/SmdkBoardPkg/Library/SmdkBoardLib/SmdkBoardHelper.S
+++ b/SamsungPlatformPkg/SmdkBoardPkg/Library/SmdkBoardLib/SmdkBoardHelper.S
@@ -377,254 +377,6 @@ ASM_PFX(ArmPlatformIsMemoryInitialized):
  * required to use assembly language)
  */
 ASM_PFX(ArmPlatformInitializeBootMemory):
-/*
- * Check if the Memory is already Initialized.
- * If Initialized goto Stack setup
- */
-	mov r10, lr
-	bl   ASM_PFX(ArmPlatformIsMemoryInitialized)
-	bne  skip_initmem
-
-	ldr r0, =0x10010350
-        mov r1, #1
-        str r1, [r0]
-
-/* CLK_DIV_DMC0 on iROM DMC=50MHz for Init DMC */
-        ldr     r0, =Exynos4210_CMU_BASE
-        ldr     r1, =0x13113113
-        ldr     r2, =Exynos4210_CMU_DIV_DMC0
-        str     r1, [r0, r2]
-
-/* MIU Setting */
-        ldr     r0, =Exynos4210_MIU_BASE
-
-        ldr     r1, =0x20001507
-        str     r1, [r0, #0x400]
-        ldr     r1, =0x00000001
-        str     r1, [r0, #0xc00]
-
-/*****************************************************************/
-/*DREX0***********************************************************/
-/*****************************************************************/
-
-        ldr     r0, =Exynos4210_DMC_0_BASE
-
-        ldr     r1, =0xE3855503
-        str     r1, [r0, #DMC_PHYZQCONTROL]
-
-        ldr     r1, =0x71101008
-        str     r1, [r0, #DMC_PHYCONTROL0]
-
-        ldr     r1, =0x7110100A
-        str     r1, [r0, #DMC_PHYCONTROL0]
-
-        ldr     r1, =0x00000084
-        str     r1, [r0, #DMC_PHYCONTROL1]
-
-        ldr     r1, =0x71101008
-        str     r1, [r0, #DMC_PHYCONTROL0]
-
-        ldr     r1, =0x0000008C
-        str     r1, [r0, #DMC_PHYCONTROL1]
-
-        ldr     r1, =0x00000084
-        str     r1, [r0, #DMC_PHYCONTROL1]
-
-        ldr     r1, =0x0000008C
-        str     r1, [r0, #DMC_PHYCONTROL1]
-
-        ldr     r1, =0x00000084
-        str     r1, [r0, #DMC_PHYCONTROL1]
-
-        ldr     r1, =0x00000000
-         str     r1, [r0, #DMC_PHYCONTROL2]
-
-        ldr     r1, =0x0FFF30da
-        str     r1, [r0, #DMC_CONCONTROL]
-
-        ldr     r1, =0x00202500
-        str     r1, [r0, #DMC_MEMCONTROL]
-
-        ldr     r1, =0x20f01223
-        str     r1, [r0, #DMC_MEMCONFIG0]
-
-        ldr     r1, =0xff000000
-        str     r1, [r0, #DMC_PRECHCONFIG]
-
-        ldr     r1, =0x0000005D
-        str     r1, [r0, #DMC_TIMINGAREF]
-
-        ldr     r1, =0x34498691
-        str     r1, [r0, #DMC_TIMINGROW]
-
-        ldr     r1, =0x36330306
-        str     r1, [r0, #DMC_TIMINGDATA]
-
-        ldr     r1, =0x50380365
-        str     r1, [r0, #DMC_TIMINGPOWER]
-
-        mov     r2, #Exynos4210_DMC_DELAY
-
-loop_2:
-        subs    r2, r2, #1
-        bne     loop_2
-        ldr     r1, =0x07000000
-        str     r1, [r0, #DMC_DIRECTCMD]
-        mov     r2, #Exynos4210_DMC_DELAY
-loop_3:
-        subs    r2, r2, #1
-        bne     loop_3
-        ldr     r1, =0x00071C00
-        str     r1, [r0, #DMC_DIRECTCMD]
-        mov     r2, #Exynos4210_DMC_DELAY
-loop_4:
-        subs    r2, r2, #1
-        bne     loop_4
-
-        ldr     r1, =0x00010BFC
-        str     r1, [r0, #DMC_DIRECTCMD]
-        mov     r2, #Exynos4210_DMC_DELAY
-loop_5:
-        subs    r2, r2, #1
-        bne     loop_5
-        ldr     r1, =0x00000488
-        str     r1, [r0, #DMC_DIRECTCMD]
-        ldr     r1, =0x00000810
-        str     r1, [r0, #DMC_DIRECTCMD]
-        ldr     r1, =0x00000C08
-        str     r1, [r0, #DMC_DIRECTCMD]
-
-/* get DMC density information */
-        ldr r1, =0x09010000
-        mov r3, #10
-loop_6:
-        str r1, [r0, #DMC_DIRECTCMD]
-        mov     r2, #Exynos4210_DMC_DELAY
-loop_7:
-        subs r2, r2, #1
-        bne     loop_7
-        ldr r6, [r0, #DMC_MRSTATUS]
-        subs r3, r3, #1
-        bne     loop_6
-        and r6, r6, #0x3c
-        lsr r6, r6, #2
-        cmp r6, #6
-        ldreq r1, =0x20e01323
-        ldrne r1, =0x20f01223
-        str     r1, [r0, #DMC_MEMCONFIG0]
-
-/*****************************************************************/
-/*DREX1***********************************************************/
-/*****************************************************************/
-        ldr     r0, =Exynos4210_DMC_1_BASE
-        ldr     r1, =0xE3855503
-        str     r1, [r0, #DMC_PHYZQCONTROL]
-
-        ldr     r1, =0x71101008
-        str     r1, [r0, #DMC_PHYCONTROL0]
-
-        ldr     r1, =0x7110100A
-        str     r1, [r0, #DMC_PHYCONTROL0]
-
-        ldr     r1, =0x00000084
-        str     r1, [r0, #DMC_PHYCONTROL1]
-
-        ldr     r1, =0x71101008
-        str     r1, [r0, #DMC_PHYCONTROL0]
-
-        ldr     r1, =0x0000008C
-        str     r1, [r0, #DMC_PHYCONTROL1]
-        ldr     r1, =0x00000084
-        str     r1, [r0, #DMC_PHYCONTROL1]
-
-        ldr     r1, =0x0000008C
-        str     r1, [r0, #DMC_PHYCONTROL1]
-
-        ldr     r1, =0x00000084
-        str     r1, [r0, #DMC_PHYCONTROL1]
-
-        ldr     r1, =0x00000000
-        str     r1, [r0, #DMC_PHYCONTROL2]
-
-        ldr     r1, =0x0FFF30da
-        str     r1, [r0, #DMC_CONCONTROL]
-
-        ldr     r1, =0x00202500
-        str     r1, [r0, #DMC_MEMCONTROL]
-
-        ldr     r1, =0x40f01223
-        str     r1, [r0, #DMC_MEMCONFIG0]
-
-        ldr     r1, =0x20f01223
-        str     r1, [r0, #DMC_MEMCONFIG0]
-
-        ldr     r1, =0xff000000
-        str     r1, [r0, #DMC_PRECHCONFIG]
-
-        ldr     r1, =0x0000005D
-        str     r1, [r0, #DMC_TIMINGAREF]
-
-        ldr     r1, =0x34498691
-        str     r1, [r0, #DMC_TIMINGROW]
-
-        ldr     r1, =0x36330306
-        str     r1, [r0, #DMC_TIMINGDATA]
-
-        ldr     r1, =0x50380365
-        str     r1, [r0, #DMC_TIMINGPOWER]
-
-        mov     r2, #Exynos4210_DMC_DELAY
-loop_8:
-        subs    r2, r2, #1
-        bne     loop_8
-        ldr     r1, =0x07000000
-        str     r1, [r0, #DMC_DIRECTCMD]
-        mov     r2, #Exynos4210_DMC_DELAY
-loop_9:
-        subs    r2, r2, #1
-        bne     loop_9
-        ldr     r1, =0x00071C00
-        str     r1, [r0, #DMC_DIRECTCMD]
-        mov     r2, #Exynos4210_DMC_DELAY
-loop_10:
-        subs    r2, r2, #1
-        bne     loop_10
-
-        ldr     r1, =0x00010BFC
-        str     r1, [r0, #DMC_DIRECTCMD]
-        mov     r2, #Exynos4210_DMC_DELAY
-loop_11:
-        subs    r2, r2, #1
-        bne     loop_11
-        ldr     r1, =0x00000488
-        str     r1, [r0, #DMC_DIRECTCMD]
-
-        ldr     r1, =0x00000810
-        str     r1, [r0, #DMC_DIRECTCMD]
-
-        ldr     r1, =0x00000C08
-        str     r1, [r0, #DMC_DIRECTCMD]
-
-/* get DMC density information */
-        ldr r1, =0x09010000
-        mov r3, #10
-loop_12:
-        str r1, [r0, #DMC_DIRECTCMD]
-        mov     r2, #Exynos4210_DMC_DELAY
-loop_13:
-        subs r2, r2, #1
-        bne     loop_13
-        ldr r7, [r0, #DMC_MRSTATUS]
-        subs r3, r3, #1
-        bne     loop_12
-        and r7, r7, #0x3c
-        lsr r7, r7, #2
-        cmp r7, #6
-        ldreq r1, =0x20e01323
-        ldrne r1, =0x20f01223
-        str     r1, [r0, #DMC_MEMCONFIG0]
-skip_initmem:
-	mov lr, r10
 	bx    lr
 
 .end
diff --git a/SamsungPlatformPkg/SmdkBoardPkg/Library/SmdkBoardLib/SmdkBoardHelper.asm b/SamsungPlatformPkg/SmdkBoardPkg/Library/SmdkBoardLib/SmdkBoardHelper.asm
old mode 100644
new mode 100755
index 7960f22..e3171f3
--- a/SamsungPlatformPkg/SmdkBoardPkg/Library/SmdkBoardLib/SmdkBoardHelper.asm
+++ b/SamsungPlatformPkg/SmdkBoardPkg/Library/SmdkBoardLib/SmdkBoardHelper.asm
@@ -359,251 +359,6 @@ ArmPlatformIsMemoryInitialized
 
 **/
 ArmPlatformInitializeBootMemory
-
-//Async bridge configuration at CPU_core(1: half_sync 0: full_sync)
-	ldr r0, =0x10010350
-	mov r1, #1
-	str r1, [r0]
-
-//CLK_DIV_DMC0 on iROM DMC=50MHz for Init DMC
-	ldr	r0, =Exynos4210_CMU_BASE
-	ldr	r1, =0x13113113
-	ldr	r2, =Exynos4210_CMU_DIV_DMC0
-	str	r1, [r0, r2]
-
-//MIU Setting
-	ldr	r0, =Exynos4210_MIU_BASE
-
-	ldr	r1, =0x20001507
-	str	r1, [r0, #0x400]
-	ldr	r1, =0x00000001
-	str	r1, [r0, #0xc00]
-
-/*****************************************************************/
-/*DREX0***********************************************************/
-/*****************************************************************/
-
-	ldr	r0, =Exynos4210_DMC_0_BASE
-
-	ldr	r1, =0xE3855503
-	str	r1, [r0, #DMC_PHYZQCONTROL]
-
-	ldr	r1, =0x71101008
-	str	r1, [r0, #DMC_PHYCONTROL0]
-
-	ldr	r1, =0x7110100A
-	str	r1, [r0, #DMC_PHYCONTROL0]
-
-	ldr	r1, =0x00000084
-	str	r1, [r0, #DMC_PHYCONTROL1]
-
-	ldr	r1, =0x71101008
-	str	r1, [r0, #DMC_PHYCONTROL0]
-
-	ldr	r1, =0x0000008C
-	str	r1, [r0, #DMC_PHYCONTROL1]
-
-	ldr	r1, =0x00000084
-	str	r1, [r0, #DMC_PHYCONTROL1]
-
-	ldr	r1, =0x0000008C
-	str	r1, [r0, #DMC_PHYCONTROL1]
-
-	ldr	r1, =0x00000084
-	str	r1, [r0, #DMC_PHYCONTROL1]
-
-	ldr	r1, =0x00000000
-	str	r1, [r0, #DMC_PHYCONTROL2]
-
-	ldr	r1, =0x0FFF30da
-	str	r1, [r0, #DMC_CONCONTROL]
-
-	ldr	r1, =0x00202500
-	str	r1, [r0, #DMC_MEMCONTROL]
-
-	ldr	r1, =0x20f01223
-	str	r1, [r0, #DMC_MEMCONFIG0]
-
-	ldr	r1, =0xff000000
-	str	r1, [r0, #DMC_PRECHCONFIG]
-
-	ldr	r1, =0x0000005D
-	str	r1, [r0, #DMC_TIMINGAREF]
-
-	ldr	r1, =0x34498691
-	str	r1, [r0, #DMC_TIMINGROW]
-
-	ldr	r1, =0x36330306
-	str	r1, [r0, #DMC_TIMINGDATA]
-
-	ldr	r1, =0x50380365
-	str	r1, [r0, #DMC_TIMINGPOWER]
-
-	mov	r2, #Exynos4210_DMC_DELAY
-
-loop_2
-	subs	r2, r2, #1
-	bne	loop_2
-	ldr	r1, =0x07000000
-	str	r1, [r0, #DMC_DIRECTCMD]
-	mov	r2, #Exynos4210_DMC_DELAY
-loop_3
-	subs	r2, r2, #1
-	bne	loop_3
-	ldr	r1, =0x00071C00
-	str	r1, [r0, #DMC_DIRECTCMD]
-	mov	r2, #Exynos4210_DMC_DELAY
-loop_4
-	subs	r2, r2, #1
-	bne	loop_4
-
-	ldr	r1, =0x00010BFC
-	str	r1, [r0, #DMC_DIRECTCMD]
-	mov	r2, #Exynos4210_DMC_DELAY
-loop_5
-	subs	r2, r2, #1
-	bne	loop_5
-	ldr	r1, =0x00000488
-	str	r1, [r0, #DMC_DIRECTCMD]
-	ldr	r1, =0x00000810
-	str	r1, [r0, #DMC_DIRECTCMD]
-	ldr	r1, =0x00000C08
-	str	r1, [r0, #DMC_DIRECTCMD]
-#if 1
-//get DMC density information
-	ldr r1, =0x09010000
-	mov r3, #10
-loop_6
-	str r1, [r0, #DMC_DIRECTCMD]
-	mov	r2, #Exynos4210_DMC_DELAY
-loop_7
-	subs r2, r2, #1
-	bne	loop_7
-	ldr r6, [r0, #DMC_MRSTATUS]
-	subs r3, r3, #1
-	bne	loop_6
-	and r6, r6, #0x3c
-	lsr r6, r6, #2
-	cmp r6, #6
-	ldreq r1, =0x20e01323
-	ldrne r1, =0x20f01223
-	str	r1, [r0, #DMC_MEMCONFIG0]
-#endif
-
-/*****************************************************************/
-/*DREX1***********************************************************/
-/*****************************************************************/
-	ldr	r0, =Exynos4210_DMC_1_BASE
-	ldr	r1, =0xE3855503
-	str	r1, [r0, #DMC_PHYZQCONTROL]
-
-	ldr	r1, =0x71101008
-	str	r1, [r0, #DMC_PHYCONTROL0]
-
-	ldr	r1, =0x7110100A
-	str	r1, [r0, #DMC_PHYCONTROL0]
-
-	ldr	r1, =0x00000084
-	str	r1, [r0, #DMC_PHYCONTROL1]
-
-	ldr	r1, =0x71101008
-	str	r1, [r0, #DMC_PHYCONTROL0]
-
-	ldr	r1, =0x0000008C
-	str	r1, [r0, #DMC_PHYCONTROL1]
-
-	ldr	r1, =0x00000084
-	str	r1, [r0, #DMC_PHYCONTROL1]
-
-	ldr	r1, =0x0000008C
-	str	r1, [r0, #DMC_PHYCONTROL1]
-
-	ldr	r1, =0x00000084
-	str	r1, [r0, #DMC_PHYCONTROL1]
-
-	ldr	r1, =0x00000000
-	str	r1, [r0, #DMC_PHYCONTROL2]
-
-	ldr	r1, =0x0FFF30da
-	str	r1, [r0, #DMC_CONCONTROL]
-
-	ldr	r1, =0x00202500
-	str	r1, [r0, #DMC_MEMCONTROL]
-
-	ldr	r1, =0x40f01223
-	str	r1, [r0, #DMC_MEMCONFIG0]
-
-	ldr	r1, =0x20f01223
-	str	r1, [r0, #DMC_MEMCONFIG0]
-
-	ldr	r1, =0xff000000
-	str	r1, [r0, #DMC_PRECHCONFIG]
-
-	ldr	r1, =0x0000005D
-	str	r1, [r0, #DMC_TIMINGAREF]
-
-	ldr	r1, =0x34498691
-	str	r1, [r0, #DMC_TIMINGROW]
-
-	ldr	r1, =0x36330306
-	str	r1, [r0, #DMC_TIMINGDATA]
-
-	ldr	r1, =0x50380365
-	str	r1, [r0, #DMC_TIMINGPOWER]
-
-	mov	r2, #Exynos4210_DMC_DELAY
-loop_8
-	subs	r2, r2, #1
-	bne	loop_8
-	ldr	r1, =0x07000000
-	str	r1, [r0, #DMC_DIRECTCMD]
-	mov	r2, #Exynos4210_DMC_DELAY
-loop_9
-	subs	r2, r2, #1
-	bne	loop_9
-	ldr	r1, =0x00071C00
-	str	r1, [r0, #DMC_DIRECTCMD]
-	mov	r2, #Exynos4210_DMC_DELAY
-loop_10
-	subs	r2, r2, #1
-	bne	loop_10
-
-	ldr	r1, =0x00010BFC
-	str	r1, [r0, #DMC_DIRECTCMD]
-	mov	r2, #Exynos4210_DMC_DELAY
-loop_11
-	subs	r2, r2, #1
-	bne	loop_11
-	ldr	r1, =0x00000488
-	str	r1, [r0, #DMC_DIRECTCMD]
-
-	ldr	r1, =0x00000810
-	str	r1, [r0, #DMC_DIRECTCMD]
-
-	ldr	r1, =0x00000C08
-	str	r1, [r0, #DMC_DIRECTCMD]
-
-#if 1
-// get DMC density information
-	ldr r1, =0x09010000
-	mov r3, #10
-loop_12
-	str r1, [r0, #DMC_DIRECTCMD]
-	mov	r2, #Exynos4210_DMC_DELAY
-loop_13
-	subs r2, r2, #1
-	bne	loop_13
-	ldr r7, [r0, #DMC_MRSTATUS]
-	subs r3, r3, #1
-	bne	loop_12
-	and r7, r7, #0x3c
-	lsr r7, r7, #2
-	cmp r7, #6
-	ldreq r1, =0x20e01323
-	ldrne r1, =0x20f01223
-	str	r1, [r0, #DMC_MEMCONFIG0]
-#endif
-
   bx    lr
 
   END
-- 
1.7.0.4

