From 6c6c7238cce5d9c4eb3bf76983721581e0bf8feb Mon Sep 17 00:00:00 2001 From: Olivier Martin Date: Mon, 20 Feb 2012 18:57:29 +0000 Subject: [PATCH 3/7] SamsungPlatformPkg/ExynosPkg: Fixed UART Rx Ready Flag The source code was using BIT0 of UTRSTATn as 'Buffer Empty'. But BIT0 means 'Rx Buffer Ready'. Signed-off-by: Olivier Martin --- .../ExynosPkg/Include/Platform/ArmPlatform.h | 5 +++-- .../ExynosPkg/Library/GdbSerialLib/GdbSerialLib.c | 4 ++-- .../Library/SerialPortLib/SerialPortLib.c | 4 ++-- 3 files changed, 7 insertions(+), 6 deletions(-) mode change 100644 => 100755 SamsungPlatformPkg/ExynosPkg/Include/Platform/ArmPlatform.h mode change 100644 => 100755 SamsungPlatformPkg/ExynosPkg/Library/GdbSerialLib/GdbSerialLib.c mode change 100644 => 100755 SamsungPlatformPkg/ExynosPkg/Library/SerialPortLib/SerialPortLib.c diff --git a/SamsungPlatformPkg/ExynosPkg/Include/Platform/ArmPlatform.h b/SamsungPlatformPkg/ExynosPkg/Include/Platform/ArmPlatform.h old mode 100644 new mode 100755 index edb8142..4459b40 --- a/SamsungPlatformPkg/ExynosPkg/Include/Platform/ArmPlatform.h +++ b/SamsungPlatformPkg/ExynosPkg/Include/Platform/ArmPlatform.h @@ -127,8 +127,9 @@ #define UARTIBRD UBRDIV_OFFSET #define UARTFBRD UDIVSLOT_OFFSET -#define UART_TX_EMPTY_FLAG_MASK (0x02) -#define UART_RX_EMPTY_FLAG_MASK (0x01) +#define UART_TX_EMPTY_FLAG_MASK (0x02) +#define UART_RX_BUFFER_READY_MASK (0x01) + // Exynos4210 TZPC Register #define Exynos4210_TZPC0_BASE 0x10110000 #define Exynos4210_TZPC1_BASE 0x10120000 diff --git a/SamsungPlatformPkg/ExynosPkg/Library/GdbSerialLib/GdbSerialLib.c b/SamsungPlatformPkg/ExynosPkg/Library/GdbSerialLib/GdbSerialLib.c old mode 100644 new mode 100755 index 353cad1..5b448d3 --- a/SamsungPlatformPkg/ExynosPkg/Library/GdbSerialLib/GdbSerialLib.c +++ b/SamsungPlatformPkg/ExynosPkg/Library/GdbSerialLib/GdbSerialLib.c @@ -72,7 +72,7 @@ GdbIsCharAvailable ( { UINT32 FR = PcdGet32 (PcdGdbUartBase) + UTRSTAT_OFFSET; - if ((MmioRead32 (FR) & UART_RX_EMPTY_FLAG_MASK) == 0) { + if (MmioRead32 (FR) & UART_RX_BUFFER_READY_MASK) { return TRUE; } else { return FALSE; @@ -88,7 +88,7 @@ GdbGetChar ( UINT32 FR = PcdGet32 (PcdGdbUartBase) + UTRSTAT_OFFSET; UINT32 DR = PcdGet32 (PcdGdbUartBase) + URXH_OFFSET; - while ((MmioRead32 (FR) & UART_RX_EMPTY_FLAG_MASK) == 0); + while ((MmioRead32 (FR) & UART_RX_BUFFER_READY_MASK) == 0); return MmioRead8 (DR); } diff --git a/SamsungPlatformPkg/ExynosPkg/Library/SerialPortLib/SerialPortLib.c b/SamsungPlatformPkg/ExynosPkg/Library/SerialPortLib/SerialPortLib.c old mode 100644 new mode 100755 index 812a490..1c7a78a --- a/SamsungPlatformPkg/ExynosPkg/Library/SerialPortLib/SerialPortLib.c +++ b/SamsungPlatformPkg/ExynosPkg/Library/SerialPortLib/SerialPortLib.c @@ -120,7 +120,7 @@ SerialPortRead ( UARTConsoleBase=PcdGet32(PcdConsoleUartBase); for (Count = 0; Count < NumberOfBytes; Count++, Buffer++) { - while ((MmioRead32 (UARTConsoleBase + UTRSTAT_OFFSET) & UART_RX_EMPTY_FLAG_MASK) == 0); + while ((MmioRead32 (UARTConsoleBase + UTRSTAT_OFFSET) & UART_RX_BUFFER_READY_MASK) == 0); *Buffer = MmioRead8 (UARTConsoleBase + URXH_OFFSET); } @@ -144,5 +144,5 @@ SerialPortPoll ( UINT32 UARTConsoleBase; UARTConsoleBase=PcdGet32(PcdConsoleUartBase); - return ((MmioRead32 (UARTConsoleBase + UTRSTAT_OFFSET) & UART_RX_EMPTY_FLAG_MASK) != 0); + return (MmioRead32 (UARTConsoleBase + UTRSTAT_OFFSET) & UART_RX_BUFFER_READY_MASK); } -- 1.7.0.4