Hello.

I backported 4.13 coresight driver to my kernel to use the latest CoreSight drivers.

I checked whether issues that I mentioned is resolved or not.

 

1. ETR issue

>You will have to give us more information than simply it "doesn't work".

>There are 2 problems.

>First, etr driver don't support 64bit physical address. My model has 64bit physical address.

=> This issue was resolved.

 

2. ETR issue

> I saw auxtrace data area is all 0. 

> Maybe I think the problem occured during copying from etr dma buffer area to mmaped memory

> 0x29c8b8 [0x30]: PERF_RECORD_AUXTRACE size: 0x122d30  offset: 0x29abe0  ref: 0x68d3ed7647ee5271  idx: 0  tid: 12108  cpu: -1

> . ... CoreSight ETM Trace data: size 1191216 bytes

=> I execute like below.

    ./perf record -e cs_etm/timestamp,cycacc,@1e00a000.etr/u --per-thread taskset 1 uname

    But, I got the same result. I saw auxtrace data area is all 0.

 

3. injection issue

> 0 0 0x1158 [0x40]: PERF_RECORD_FORK(2:2):(0:0)

> 0x1198 [0x40]: event: 3
>. ... raw event: size 64 bytes
> ...skipping...
>... branch stack: nr:0
> ... thread: :-1:-1
> ...... dso: <not found>

=> I execute like below.

    ./perf record -e cs_etm/timestamp,cycacc,@1e005000.etf1/u -C 0 --per-thread taskset 1 uname

    I got the same result. I got 0 in branch stack nr.

    I debugged it to give information.

    Branch stack nr is 0 because decoder->packet_count is 0.

    The perf data must include OCSD_GEN_TRC_ELEM_INSTR_RANGE to get packt_count.

    But my perf data includes OCSD_GEN_TRC_ELEM_ADDR_NACC.

    Can you explain about this situation?

 

Thank you.

 

Best Regard

Youngjae

 

 

--------- Original Message ---------

Sender : Mathieu Poirier <mathieu.poirier@linaro.org>

Date : 2017-09-23 00:13 (GMT+9)

Title : Re: Re: FW: RE: Re: FW: Re: Question for openCSD - open soruce Coresight Trace Decode

 

On 22 September 2017 at 03:10, 임영재 <youngjae24.lim@samsung.com> wrote:

Hello .Mathieu Poirier 

 

>You will have to give us more information than simply it "doesn't work".

=> There are 2 problems.

First, etr driver don't support 64bit physical address. My model has 64bit physical address.

Below code, there is problem.

 writel_relaxed(drvdata->paddr, drvdata->base + TMC_DBALO);
 writel_relaxed(0x0, drvdata->base + TMC_DBAHI);

Suzuki wrote a patchset to fix that.  On github, branch perf-opencsd-4.13:

98b62f69c4af coresight: Add support for Coresight SoC 600 components

c9b590717a3a coresight tmc: Add support for Coresight SoC 600 TMC

29f38854110e coresight tmc: Support for save-restore in ETR

0863f7b1f278 coresight tmc etr: Setup AXI cache encoding for read transfers

f7bab28b7f16 coresight tmc etr: Cleanup AXICTL register handling

d81598f029b5 coresight tmc etr: Detect address width at runtime

3c97c4f2566a coresight tmc: Detect support for scatter gather

ca684de0ba58 coresight tmc etr: Add capabilitiy information

b8b9228d7160 coresight tmc: Handle configuration types properly

cc442642fcf5 coresight replicator: Expose replicator management registers

16c65a29684e coresight tmc: Expose DBA and AXICTL

560c49a5aa57 coresight tmc: Add helpers for accessing 64bit registers

I suggest you backport the relevant bit to your kernel 4.9.

 

 

Anyway, I fixed it like below.

 

drivers/base/dma-contiguous.c

+static phys_addr_t size_cmdline = 0x1400000;
+static phys_addr_t base_cmdline = 0xE8000000;
+static phys_addr_t limit_cmdline = 0xE8000000+0x1400000;

I checked rrp of etr. it's ok.

And I tried to read etr dma buffer area.  Etm information was saved normally.

 

 

Second, I recorded etm information using perf like below.

echo 1 > /sys/devices/platform/1e00a000.etr/1e00a000.etr/enable_sink

The above is not required.

 

./perf record -e cs_etm/timestamp,cycacc,@1e00a000.etr/u --per-thread taskset 1 uname

 

I checked the dump like below.

./perf report --stdio --dump

 

I saw auxtrace data area is all 0. 

Things look good - everything seems to be in order.  There isn't much else I can do here...  Things do work on both reference platform (DB401c and Juno).

I always tell people in your situation to get a DB410c and see where the discrepancies are.  Clocks could be an issue but I'm just guessing here.

 

Maybe I think the problem occured during copying from etr dma buffer area to mmaped memory

 

0x29c8b8 [0x30]: PERF_RECORD_AUXTRACE size: 0x122d30  offset: 0x29abe0  ref: 0x68d3ed7647ee5271  idx: 0  tid: 12108  cpu: -1

. ... CoreSight ETM Trace data: size 1191216 bytes

>Also, on gitHub I see close to 30 patches on top of kernel 4.9, where below you have only 10.  Please add all the patches so that your environment is as close to ours.

=> Of course, there are 30 patches on top of kernel 4.9.  20 patches is relative to tools/perf.  Because I use perf in opencsd-4.9, I don't need to apply it.

    Anyway, I compared my kernel source with opencsd-perf-4.9. It is the same..

 

b50067a cs-etm: Update to perf cs-etm decoder for OpenCSD v0.5                                                tools/perf/util/cs-etm-decoder/cs-etm-decoder.c |    2 ++ 2308063 cs-etm: fixing map__load() parameter                                                                         tools/perf/util/cs-etm.c |    2 +- ae6ba28 cs-etm: Update to perf cs-etm decode for OpenCSD v0.4                                                 tools/perf/util/cs-etm-decoder/cs-etm-decoder.c |   30 +++++++++++++++++------ 29ff0bf perf scripts: Fixing file name extension                                                                         tools/perf/scripts/python/cs-trace-disasm.py |    2 +- 9074ff4 perf scripts: Fix binary filename and path                                                                     tools/perf/scripts/python/cs-trace-disasm.py |   12 +++++++++++- 5f5c594 cs-etm: Update to cs-etm-decoder to handle new packet type from OpenCSD.                         tools/perf/util/cs-etm-decoder/cs-etm-decoder.c |    6 +----- a02ed95 cs-etm: associating output packet with CPU they executed on                                            tools/perf/... 9e34dee cs-etm: removing unecessary structure field                                                                  tools/perf/util/cs-etm.c |   10 +--------- 677a287 cs-etm: account for each trace buffer in the queue                                                         tools/perf/util/cs-etm.c |   17 +++++++++-------- 593a948 cs-etm: avoid casting variable                                                                                   tools/perf/util/cs-etm.c |    6 ++++-- 26cee10 cs-etm: fixing uninitialised cpumode                                                                           tools/perf/util/cs-etm.c |    1 + 328948b perf tools: fixing Makefile problems                                                                          tools/perf/Makefile.config |    4 ++-- 73d4294 perf tools: new naming convention for openCSD                                                          tools/perf/util/cs-etm-decoder/cs-etm-decoder.c |  138 ++++++++++++----------- 451ca19 perf scripts: Add python scripts for CoreSight traces                                                       tools/perf/scripts/python/... 8f510fb perf tools: decoding capabilitity for CoreSight traces                                                       tools/perf/ .. b5d782e perf symbols: Check before overwriting build_id                                                            tools/perf/... dad8531 coresight: updating documentation to reflect integration with perf                                      Documentation/trace/coresight.txt |  138 +++++++++++++++++++++++++++++++++---- ea817df coresight: tmc: implementing TMC-ETR AUX space API                                                    drivers/hwtracing/coresight/coresight-tmc-etr.c |  243 +++++++++++++++++++++++ 0a189e4 perf tools: Removing miscellaneous debug output                                                         tools/perf/arch/arm/util/cs-etm.c |    2 -- 285fb22 coresight: perf: Add a missing call to etm_free_aux                                                        drivers/hwtracing/coresight/coresight-etm-perf.c |    2 +- 3bfa9ae coresight: Add support for ARM Coresight STM-500                                                      drivers/hwtracing/coresight/coresight-stm.c |    5 +++++ 8044597 coresight: tmc: Remove duplicate memset                                                                   drivers/hwtracing/coresight/coresight-tmc-etr.c |    2 -- 63c0930 coresight: tmc: Get rid of mode parameter for helper routines                                          drivers/hwtracing/coresight/... 034cd3a coresight: tmc: Cleanup operation mode handling                                                        drivers/hwtracing/coresight/... 2866655 coresight: reset "enable_sink" flag when need be                                                          drivers/hwtracing/coresight/ 4cba396 coresight: etm3x: Adding missing features of Coresight PTM components                            .../hwtracing/coresight/... 6f6514b coresight: etm3x: indentation fix (extra space removed)                                                 .../hwtracing/coresight/coresight-etm3x-sysfs.c    |    2 +- d3167d3 coresight: stm: return error code instead of zero in .packet()                                         drivers/hwtracing/coresight/coresight-stm.c |    4 ++--

 

 

 

 

 

 

--------- Original Message ---------

Sender : Mathieu Poirier <mathieu.poirier@linaro.org>

Date : 2017-09-16 01:09 (GMT+9)

Title : Re: FW: RE: Re: FW: Re: Question for openCSD - open soruce Coresight Trace Decode

 

On 15 September 2017 at 00:22, 임영재 <youngjae24.lim@samsung.com> wrote:

Hello Mike.

 

I wonder whether opencsd-perf-4.9 supports injection of branch stack or not.

 

Thank you.

 

--------- Original Message ---------

Sender : 임영재 <youngjae24.lim@samsung.com> Senior Engineer/System S/W개발2그룹(무선)/삼성전자

Date : 2017-09-15 14:32 (GMT+9)

Title : RE: Re: FW: Re: Question for openCSD - open soruce Coresight Trace Decode

 

Hello Mike,

 

I cannot build a kernel using opencsd-perf-4.13.

My project has kernel version 4.9.

I don't want to change kernel version.

So, I just want to apply patches of coresight drvier in opencsd-perf-4.9.

I applyed pathes of coresight like below.

But, ETR didn't have normal operation.

You will have to give us more information than simply it "doesn't work".

Also, on gitHub I see close to 30 patches on top of kernel 4.9, where below you have only 10.  Please add all the patches so that your environment is as close to ours.

 

 

0001-coresight-stm-return-error-code-instead-of-zero-in-..patch 0002-coresight-etm3x-indentation-fix-extra-space-removed.patch 0003-coresight-etm3x-Adding-missing-features-of-Coresight.patch 0004-coresight-reset-enable_sink-flag-when-need-be.patch       0005-coresight-tmc-Cleanup-operation-mode-handling.patch       0006-coresight-tmc-Get-rid-of-mode-parameter-for-helper-r.patch 0007-coresight-tmc-Remove-duplicate-memset.patch               0008-coresight-Add-support-for-ARM-Coresight-STM-500.patch     0009-coresight-perf-Add-a-missing-call-to-etm_free_aux.patch   0010-coresight-tmc-implementing-TMC-ETR-AUX-space-API.patch

 

 

 

 

--------- Original Message ---------

Sender : Mike Leach <mike.leach@linaro.org>

Date : 2017-09-13 19:37 (GMT+9)

Title : Re: FW: Re: Question for openCSD - open soruce Coresight Trace Decode

 

Hello Youngkae Lim,

V8A cores should not be producing the conditional packets mentioned earlier in this e-mail. Please build a kernel using the opencsd-perf-4.13 or opencsd-perf-master branches which contain the latest CoreSight drivers.

I cannot comment on the inject issue - Sebastian may be of more help here. There are two additional patches submitted to this list which are not integrated into the opencsd-perf branches. Please add these patches before building perf because they correct some issues.

Best Regards

Mike

On 13 September 2017 at 08:38, 임영재 <youngjae24.lim@samsung.com> wrote:

Dear. Mike Leach.

 

My cores are v8-a cores.

Perf datas that I gathered don't include unsupported packet.

But, injection is failed below.

 

0 0 0x1158 [0x40]: PERF_RECORD_FORK(2:2):(0:0) 0x1198 [0x40]: event: 3 . . ... raw event: size 64 bytes ...skipping... ... branch stack: nr:0  ... thread: :-1:-1  ...... dso: <not found>

 

Best regards.

Youngjae Lim

 

--------- Original Message ---------

Sender : Mike Leach <mike.leach@linaro.org>

Date : 2017-09-05 01:14 (GMT+9)

Title : Re: Question for openCSD - open soruce Coresight Trace Decode

 

Hi Sebastian and Youngjae.


The decoder does not support at present the packet types for tracing
of Conditional non-branches (i.e. the /* conditional instruction
tracing */ block above).
Looking at the TRCIDR0 for each core from the perf dump above, the
cores in this system do not support conditional instruction tracing,
so these packets should never be seen.
Architecturally it is not permitted in ETMv4 for A class cores to
trace conditional none branch instructions, so these values should
never be seen on any A class trace output.

Can you confirm that these cores are in fact v7-A or v8-A cores?

These unsupported packets can be due to perf concatenating wrapped
trace data into a single buffer which throws out the decoder. The
latest drivers in the opencsd-perf-master branch insert barrier
packets to overcome this issue. Can you confirm that the kernel you
are using uses the latest driver set?

Conditional instruction trace of none-branches is associated with data
trace - this is only permitted on R and M class cores, if implemented
at all.

Regarding the change above - I agree this is a good change. I can make
it myself or you can send a patch - either works for me.

Regards

Mike


On 1 September 2017 at 15:23, Sebastian Pop <sebpop@gmail.com> wrote:
> The next problem that I see is an unhandled packet in
> decoder/source/etmv4/trc_pkt_decode_etmv4i.cpp:
> TrcPktDecodeEtmV4I::decodePacket()
>
> (gdb) p m_curr_packet_in->getType()
> $267 = ETM4_PKT_I_COND_RES_F1
>
>     /*** presently unsupported packets ***/
>     /* conditional instruction tracing */
>     case ETM4_PKT_I_COND_FLUSH:
>     case ETM4_PKT_I_COND_I_F1:
>     case ETM4_PKT_I_COND_I_F2:
>     case ETM4_PKT_I_COND_I_F3:
>     case ETM4_PKT_I_COND_RES_F1:
>     case ETM4_PKT_I_COND_RES_F2:
>     case ETM4_PKT_I_COND_RES_F3:
>     case ETM4_PKT_I_COND_RES_F4:
>     // speculation
>     case ETM4_PKT_I_CANCEL_F1:
>     case ETM4_PKT_I_CANCEL_F2:
>     case ETM4_PKT_I_CANCEL_F3:
>     case ETM4_PKT_I_COMMIT:
>     case ETM4_PKT_I_MISPREDICT:
>     case ETM4_PKT_I_DISCARD:
>     // data synchronisation markers
>     case ETM4_PKT_I_NUM_DS_MKR:
>     case ETM4_PKT_I_UNNUM_DS_MKR:
>     /* Q packets */
>     case ETM4_PKT_I_Q:
>         resp = OCSD_RESP_FATAL_INVALID_DATA;
>
> LogError(ocsdError(OCSD_ERR_SEV_ERROR,OCSD_ERR_BAD_DECODE_PKT,"Unsupported
> packet type."));
>         break;
>
>



-- 
Mike Leach
Principal Engineer, ARM Ltd.
Blackburn Design Centre. UK

--

Mike Leach

Principal Engineer, ARM Ltd.

Blackburn Design Centre. UK