Hi Mike,
Thanks so much. We got it by reading ETM v4 RS, we missed something, the big/little endian is not right. And we also disable the data trace to reduce the ETB log.
ETB DUMP:
read data ->
00000005
00000000
00000000
80060180
04000100
00186782
02F60000
2C9AE5B8
DA8005D6
F718F096
96F64696
E0FE05DE
012C7302
012C0300
00000001
0A000000
read pointer 40
write pointer 50
After we Converted to raw stream.
The yellow highlight is the async frame. It also has two timestamp(02)
B8E59AD60580DA96F0
732D0100032D010100
0000000000000000000000801610001
0004836719000000F702B8E59AD6058
0DA96F018F79646F796DF05FF02732D
0100032D01010000000000000
We will try to use OpenCSD to make it easier later.
Idx:0; ID:0; I_ASYNC : Alignment Synchronisation.
Idx:12; ID:0; I_CCNT_F3 : Cycle Count format 3.; Count=0x2
Idx:13; ID:0; I_CCNT_F3 : Cycle Count format 3.; Count=0x0
Idx:14; ID:0; I_BAD_SEQUENCE : Invalid Sequence in packet.[I_EXTENSION]
Idx:16; ID:0; I_BAD_SEQUENCE : Invalid Sequence in packet.[I_EXTENSION]
Idx:18; ID:0; I_CANCEL_F2 : Cancel Format 2.; Atom: EE, Cancel(1), Mispredict
Idx:19; ID:0; I_EVENT : Trace Event.
Idx:20; ID:0; I_ADDR_MATCH : Exact Address Match., [0]; Addr=0x0000000000000000;
Idx:21; ID:0; I_BAD_SEQUENCE : Invalid Sequence in packet.[I_ASYNC]
PKTP_ETMV4I : 0x0014 (OCSD_ERR_INVALID_PCKT_HDR) [Invalid packet header]; TrcIdx=24; CS ID=03; Idx:24; ID:0; I_RESERVED : Reserved Packet Header
PKTP_ETMV4I : 0x0014 (OCSD_ERR_INVALID_PCKT_HDR) [Invalid packet header]; TrcIdx=25; CS ID=03; Idx:25; ID:0; I_RESERVED_CFG : Reserved header for current configuration.[I_UNNUM_DS_MKR]
PKTP_ETMV4I : 0x0014 (OCSD_ERR_INVALID_PCKT_HDR) [Invalid packet header]; TrcIdx=26; CS ID=03; Idx:26; ID:0; I_RESERVED : Reserved Packet Header
PKTP_ETMV4I : 0x0014 (OCSD_ERR_INVALID_PCKT_HDR) [Invalid packet header]; TrcIdx=27; CS ID=03; Idx:27; ID:0; I_RESERVED_CFG : Reserved header for current configuration.[I_COND_RES_F3]
Thanks again for your support.
BR//Jinnan
From: Mike Leach <mike.leach@linaro.org>
Sent: Tuesday, June 29, 2021 8:04 PM
To: Jinnan Li A <jinnan.a.li@ericsson.com>
Cc: coresight@lists.linaro.org
Subject: Re: ETM4 for Cortex-M7
Hi,
On Tue, 29 Jun 2021 at 07:10, Jinnan Li A <jinnan.a.li@ericsson.com> wrote:
Hi Linaro Coresight Team,
We are debugging Arm ETB. We don’t know how to dump the ETB data with the right method. Please give me some comments, thanks so much.
- Let’s me give a description for our ETB environment first.
For the Core-sight components, after enabled ETM and ETB. We can dump the ETB data after a while.
According to ARM_CoreSight_Architecture_Specification.pdf, then We think it works by changing the trace source ID.
The following data is from the head of trace buffer.
Before the trace source ID = 2:
00000005 = 00 | 0b10<<1+0b1 | 0x0 | 0x0
After the trace source ID = 4:
00000009 = 00 | 0b100<<1+0b1 | 0x0 | 0x0
0000000B
00000000
04000000
00800000
This doesn't match the file you attached. (tracebuffer.bin)
1st 16 bytes are 00 00 09 00 00 00 0b 00 00 00 00 00 00 04 00 00
The registers about ETM are as follows.
TRCCONFIGR(id:0x10)=0x31F07
TRCTRACEIDR(id:0x40)=0x2
TRCIDR8(id:0x180)=0x1
TRCIDR9(id:0x184)=0x20
TRCIDR10(id:0x188)=0x2
TRCIDR11(id:0x18c)=0x0
TRCIDR12(id:0x190)=0x1
TRCIDR13(id:0x194)=0x0
TRCIDR0(id:0x1e0)=0x8020EFF
TRCIDR1(id:0x1e4)=0x4100F401 ARM ETM4.0.1
TRCIDR2(id:0x1e8)=0x420004
- How to use OpenCSD for M7?
We also try to dump with your source code “OpenCSD” https://github.com/Linaro/OpenCSD, it’s a useful tool. But maybe we lost some configuration, our ETB can’t be dumped.
Trace Packet Lister : Protocol printer ETMV4I on Trace ID 0x0
Idx:0; ID:0; I_NOT_SYNC : I Stream not synchronised
Idx:285; ID:0; I_INCOMPLETE_EOT : Incomplete packet at end of trace.[I_NOT_SYNC]
ID:0 END OF TRACE DATA
Trace Packet Lister : Trace buffer done, processed 288 bytes.
The attachments are the settings and trace buffer.
The trc_pkt_decoder requires a snapshot in the format defined in the docs supplied with the opencsd project. The traceinfo.ini file you provide is not valid.;
So my question is:
- Should we use ETM4D instead of ETMV4I?
#define OCSD_BUILTIN_DCD_ETMV4D "ETMV4D" /**< ETMv4 data decoder */
ETMv4 uses separate streams for ETM instruction and data trace. The ID of the data trace is ID of Instruction trace +1.
You would need to enable two decoders, one for instruction trace, one for data trace. However, the OpenCSD development has not yet implemented the decoder for data trace.
- Does OpenCSD support ETMV4D and Cortex-M7?
We can see the TODO from git repo.
Support to be added: ETMv4 data trace - packet processing and decode.
const char *decoderName = bDataChannel ? OCSD_BUILTIN_DCD_ETMV4D : OCSD_BUILTIN_DCD_ETMV4I;
The data decoder for ETM v4 has not been implemented. You can decode instriuction trace from ETMv4 / M class core..
I didn’t see the M7 support.
69 { "Cortex-M0", { ARCH_V7, profile_CortexM } },
70 { "Cortex-M0+", { ARCH_V7, profile_CortexM } },
71 { "Cortex-M3", { ARCH_V7, profile_CortexM } },
72 { "Cortex-M4", { ARCH_V7, profile_CortexM } }
This support associates core types from the snapshot with architecture and profile types. If the one you want is not there, add it, or use one that is and has the same profile and architecture
version.
- A stupid question, could you kindly tell me which ARM document introduce the data encoder?
I do not understand what you mean by "data encoder"? The ETMv4 specification contains all the information on trace formats.