Hi Wojciech,

Thanks for the patch. The patch works. The devices are recognized by the kernel.

@Mathieu, I try to enable tracing but the kernel reports 'building path(s) failed". Any idea why?

root@xilinx-zcu102-2017_4:/sys/bus/coresight/devices# cat /sys/bus/coresight/devices/fec40000.etm0/enable_source
0
root@xilinx-zcu102-2017_4:/sys/bus/coresight/devices# echo 1 > /sys/bus/coresight/devices/fec40000.etm0/enable_source
[ 9786.121394] building path(s) failed
-sh: echo: write error: No such device
root@xilinx-zcu102-2017_4:/sys/bus/coresight/devices#

It this because coresight_build_path/_coresight_build_path try to find a connected sink node which does not exist?

Regards,

Jan

--

Jan Hoogerbrugge

Principal Security Architect

Competence Center Crypto & Security

NXP Semiconductors

High Tech Campus 46, 5656AE Eindhoven, The Netherlands

Phone: +31 6 57728704

From: Wojciech Żmuda <wzmuda@n7space.com>
Sent: Wednesday, October 23, 2019 12:20 PM
To: Jan Hoogerbrugge <jan.hoogerbrugge@nxp.com>
Cc: coresight@lists.linaro.org <coresight@lists.linaro.org>; mathieu.poirier@linaro.org <mathieu.poirier@linaro.org>; guermazi_zied@yahoo.com <guermazi_zied@yahoo.com>; al.grant@arm.com <al.grant@arm.com>; Michal Mosdorf <mmosdorf@n7space.com>; Micha³ Kurowski <mkurowski@n7space.com>; Wojciech Żmuda <wzmuda@n7space.com>
Subject: [EXT] [PATCH 0/1] Xilinx Zynq Ultrascale+ CoreSight device tree nodes
 
Caution: EXT Email

From: Wojciech Zmuda <wzmuda@n7space.com>

Hello Jan, hello all,

Sorry for not keeping up with the list recently. I had plans to deliver
working Coresight support for Zynq Ultrascale+, but it looks like I
won't be able to dedicate a proper time slice for that in the nearest
future.

I guess, the best solution for everybody would be to share what I've got
so far.

A few notes first:
1. I'm successfully using this configuration on Xilinx ZCU104 board
running mainline Linux 5.1-rc1 with some Linaro patches applied.
Since I can see those patches have already made it into mainline, I think
this DTS should work, with a minor tweaks, the on current mainline.
2. Since I forked Linux, bindings for funnel and replicator has changed.
The ones used here are obsolete now. I think they should still work, but
warnings will be issued in dmesg. New bindings are described in
Documentation/devicetree/bindings/arm/coresight.txt in Linux tree.
3. I'm successfully tracing with all four ETMs to both ETFs and ETR.
This suggests ETM, ETF and ETR bindings as well as replicators and
funnels bindings should be correct.
4. However, I haven't tested the TPIU port or STM. While the description
seems accurate with the Zynq US+ TRM, I cannot confirm it is complete.
5. Platform specific: for timestamp support, the timestamp generator
must be enabled. It can be done from uBoot with the following command:

  ZynqMP> mw fe900000 1

Not doing this will cause Perf to report 'Timestamp: 0x0' when the
'timestamp' flag is added to cs_etm event. This is described in details
somewhere on this list.

6. I based the DTS file on what I've found here:
https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgitlab.fel.cvut.cz%2Fbarysmax%2Fdiploma-sw-hw-xilinx%2F&amp;data=02%7C01%7Cjan.hoogerbrugge%40nxp.com%7C69069710fa05443c241c08d757a2b3de%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C1%7C637074228621947481&amp;sdata=aGuXnqtF1UkRQBSID672YxvQqGQ1VcPdiE03oUV4Hc4%3D&amp;reserved=0
The DTS patch stored in this repo didn't work out of the box, but gave me
a starting point.

Many thanks for the Linaro team, who offered me a great help on enabling
and testing Coresight on this SoC. I'll try to monitor Zynq-related
threads on the list and to offer my help.



Wojciech Zmuda (1):
  zynqmp: Add CoreSight support to DTS

 .../boot/dts/xilinx/zynqmp-coresight.dtsi     | 312 ++++++++++++++++++
 .../boot/dts/xilinx/zynqmp-zcu104-revA.dts    |   1 +
 2 files changed, 313 insertions(+)
 create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-coresight.dtsi

--
2.20.1