Hi Hanjun,
I think SRAT is the correct way for us to do it. We can carry your patches in our tree until upstream has decided.
Thanks
Graeme
On 30/07/13 11:08, Hanjun Guo wrote:
Hi
It seems that the upstream will not accept my patch for cpu topology
using MPIDR register, they raised another solution which get cpu topology
from FDT.
I proposed another solution using ACPI to get the cpu topology, how do you
think of this solution?
Thanks
Hanjun
On 2013-7-30 1:23, Lorenzo Pieralisi wrote:
On Mon, Jul 29, 2013 at 02:36:30PM +0100, Dave Martin wrote:
On Mon, Jul 29, 2013 at 10:54:01AM +0100, Will Deacon wrote:Will and Dave summed up the existing issues with MPIDR definition related to
On Mon, Jul 29, 2013 at 10:46:06AM +0100, Vincent Guittot wrote:In fact, the ARM Architecture doesn't place any requirements on MPIDRs to
On 27 July 2013 12:42, Hanjun Guo <hanjun.guo@linaro.org> wrote:... except that the architecture doesn't define what the AFF fields in MPIDR
Power aware scheduling needs the cpu topology information to improve theIt's not only power aware scheduling. The scheduler already uses
cpu scheduler decision making.
topology and cache sharing when CONFIG_SCHED_MC and/or
CONFIG_SCHED_SMT are enable. So you should also add these configs for
arm64 so the scheduler can use it
really represent. Using them to make key scheduling decisions relating to
force the aff fields to exist _at all_. It's just a recommendation.
Instead, you have a 24 or 32-bit number which is unique per CPU, and which
is _probably_ assigned in a way resembling the aff fields.
cache proximity seems pretty risky to me, especially given the track record+1
we've seen already on AArch32 silicon. It's a convenient register if it
contains the data we want it to contain, but we need to force ourselves to
come to terms with reality here and simply use it as an identifier for a
CPU.
Also, we should align arm and arm64. The problem is basically exactly
the same, and the solution needs to be the same. struct cputopo_arm is
already being abused -- for example, TC2 describes the A15 and A7
clusters on a single die as having different "socket_id" values, even
though this is obviously nonsense. But there's no other way to describe
that system today.
Can't we just use the device-tree to represent this topological data forThis may become more important as we start to see things like asymmetric
arm64? Lorenzo has been working on bindings in this area.
topologies appearing (different numbers of nodes and different
interdependence characteristics in adjacent branches of the topology
etc.)
the topology description.
FYI, a link to the current topology bindings posted on DT-discuss and LAKML:
https://lists.ozlabs.org/pipermail/devicetree-discuss/2013-April/031725.html
I am waiting for the dust to settle on the DT bindings review discussions to
repost them and get them finalized.
Lorenzo