From: Al Stone ahs3@redhat.com

This is the first in a series to eventually convert all of the Arndale GPIO controllers to ACPI. This is the proposed ACPI description meant to match what is done in DT, but is very specific to the Samsung driver.

Signed-off-by: Al Stone al.stone@linaro.org --- platforms/exynos5250-arndale.acpi/ssdt0.asl | 64 ++++++++++++++++++++++++++++- 1 file changed, 63 insertions(+), 1 deletion(-)

diff --git a/platforms/exynos5250-arndale.acpi/ssdt0.asl b/platforms/exynos5250-arndale.acpi/ssdt0.asl index 69dce10..8b8efc7 100644 --- a/platforms/exynos5250-arndale.acpi/ssdt0.asl +++ b/platforms/exynos5250-arndale.acpi/ssdt0.asl @@ -12,6 +12,68 @@ DefinitionBlock ( 2, // SSDT compliance revision "LINARO", // OEM ID "ARNDALE ", // table ID - 0x00000001) // OEM revision + 0x00000003) // OEM revision { + Scope (_SB) + { + // Base Address: 0x03860000 + Device (SPC3) // Samsung pin controller + { + Name (_HID, "LINA0002") + Name (_UID, 0x3) + + Name (BNKS, 0x1) // number of pin banks + Name (NGRP, 0x1) // number of pin groups + Name (NFUN, 0x1) // number of pinmux functions + + Method (_CRS, 0x0, Serialized) + { + // Base address for the pin controller + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + 0x03860000, + 0x20) + }) + Return (RBUF) + } + + Device (GPZ) // GPIO chip GPZ -- first bank + { + Name (TAG, "gpz") // human-readable name + Name (BASE, 0x0) // base pin number + Name (NPIN, 0x7) // number of pins + + // We need _CRS here in order to provide + // the actual registers for this part of + // the controller + Method (_CRS, 0x0, Serialized) + { + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + 0x03860000, + 0x20) + }) + Return (RBUF) + } + } + + Device (I2S0) // First Pin Group + { + Name (NPIN, 0x7) // number of pins + Name (FUNC, 0x2) // function number + Name (PUD, 0x0) // direction + Name (DRV, 0x0) // drive + Method (PINS, 0x0, NotSerialized) + { + Return (Package () { + "gpz-0", "gpz-1", "gpz-2", + "gpz-3", "gpz-4", "gpz-5", + "gpz-6" + }) + } + } + } + } }