In message <
CANuQgHHq_+aZ6z100agOuaumeUyXwH-HL6aNPgrtOWBadEQaHQ@mail.gmail.com> you wrote:
>
> > In message <
1324275424-29468-3-git-send-email-chander.kashyap@linaro.org>
> > you wrote:
> > > Earliar ARM clock frequency was calculated by:
> > > MOUTAPLL/(DIVAPLL + 1) which is actually returning SCLKAPLL.
> > > It is fixed by calcuating it as follows:
> >
> > Um.... Comment and code disagree:
> >
> > > ARMCLK=MOUTCORE/(DIVCORE + 1)/DIVCORE2 + 1)
> >
> > ...or is this just missing a paren?
> >
> > > + dout_apll = get_pll_clk(APLL) / (core_ratio + 1);
> > > + dout_apll /= (core2_ratio + 1);
> >
> > This gives
> >
> > ARMCLK=MOUTCORE/(DIVCORE + 1)/ (DIVCORE2 + 1)
> >
> > Please check if this is correct.
> >
>
> Below is the scenario of selection.
> ____________
> MOUTAPLL --------------->| MUX_CORE |------------>MOUTCORE
> MOUTMPLL --------------->|____________|
>
> Here MOUTAPLL is selected as input. So Parent is correct.