Hi there,

I am trying to implement cpuidle driver for imx51, and for better understanding how various c-state map to ARM soc,

I would like to get some comments.

First of all, we basically have 3 major state for imx51, which are defined in specification of the soc. Like:

RUN - Core is active, clocks are on, the peripheral modules required are active. SW can close

clocks of modules that are not in use. In addition CCM can enable power gating for the modules described above.

WAIT - Core is disabled and clock gated, bus clocks to peripherals can be on as required. PG [power gating] and

SRPG[state retention PG] can be applied to Cortex_A8 and the different blocks as described on the section above.

STOP - Core is disabled, peripherals are disabled, bus clocks are off, PLLs off. PG and SRPG can

be applied to Cortex_A8 and the different blocks as described on the section above.

Naturely, I think the maping can be:

RUN - c0

WAIT - c1

STOP - c2

Or, if possible, some extra states can be assert into each c-state to get c3, c4....

Since other SOCs, like omap or samsung's chip, already have cpuidle driver, I would like to especially compare imx51 with those.

thanks

Yong