Hi Leif，

Another questions:

In Arm V8 Architecture Reference Manual，there is an example (see beblow) to explain the shareability attribute of clusters. It is easy to know: each cluster is corresponding to a Inner shareable domain; the two cluster comprise a Outer shareable domain.

So, how does the big.LITTLE HMP system treat two clusters as a Inner shareable domain？


>From Page B2-91, DDI0487A_b_armv8_arm.pdf:

Example B2-1 Use of shareability attributes
In an implementation, a particular subsystem with two clusters of PEs has the requirement that:
• In each cluster, the data caches or unified caches of the PEs in the cluster are transparent for all data accesses
to memory locations with the Inner Shareable attribute.
• However, between the two clusters, the caches:
— Are not required to be coherentfor data accesses that have only the Inner Shareable attribute.
— Are coherent for data accesses that have the Outer Shareable attribute.
In this system, each cluster is in a different shareability domain for the Inner Shareable attribute,but all components
of the subsystem are in the same shareability domain for the Outer Shareable attribute.
A system might implement two such subsystems. If the data caches or unified caches of onesubsystem are not
transparent to the accesses from the other subsystem, this system has two Outer Shareable shareability domains.



-----Original Message-----
From: Kelvin K. Li
Sent: 2014-5-1 (星期四) 18:08
To: Leif Lindholm
Cc: linaro-dev
Subject: 答复: why is the the smp_mb() in arm64's barrier.h "dmb ish"?


Hi Leif，

Why do the smp_mb()/smp_rmb()/smp_wmb() for arm (arm-32) not change to the "dmb ishxx" too?

Is there some consideration？

-----Original Message-----
From: Leif Lindholm [mailto:leif.lindholm@linaro.org]
Sent: 2014-5-1 (星期四) 0:39
To: Kelvin K. Li
Cc: linaro-dev
Subject: Re: why is the the smp_mb() in arm64's barrier.h "dmb ish"?

Hi Kelvin.

On 30 April 2014 10:52,  <KelvinKLi@via-alliance.com> wrote:
> In arch/arm64/include/asm/barrier.h, there is the definition of
> smp_mb()/smp_rmb()/smp_wmb() for arm64. I noticed that all the 3 macors are
> using “dmb ishxx”, which is only affect the cluster of the CPU executing the
> instruction.

This is incorrect.

> But in the big.LITTLE system, there will be 2 cluster. So the
> smp_mb()/smp_rmb()/smp_wmb() cannot affect all the CPU in the system.

Yes, they do.

In a big.LITTLE HMP system, all participating CPUs are part of the
inner-shareable domain.

Regards,

Leif