== Progress ==
* [GlobalISel] AArch64 test-suite and self-host [TCWG-1074][3/10]
- Ran more tests and reported the results upstream
* [ARM GlobalISel] Add support for soft float targets [TCWG-1039][3/10]
- Started supporting G_FREM and G_FPOW, which are already handled by
the target-independent code
- Committed G_FREM upstream, G_FPOW is ready to commit first thing next week
* Migrate scripts to Python 3 [TCWG-896] [1/10]
- Moved llvm-helper-scripts
* Misc [3/10]
- Mailing lists, code reviews, meetings
== Plan ==
* [ARM GlobalISel] Add support for soft float targets [TCWG-1039][3/10]
=== This Week ===
GDB Kernel Awarenes - Kernel Dump setup for ARM [9/10]
-- Background study on kdump and try to find working steps for QEMU ARM.
-- There is a problem with kdump-tools install script with QEMU
-- Tried building kernel for Raspberry Pi2 and Pi3 with kdump, no
success so far.
-- Setup B2260 with debian and try kdump setup
-- Setup and kernel config successful but kdump couldn't configure
-- Tried the same with HiKey board
Miscellaneous Activities [1/10]
-- Meetings, Emails etc.
=== Next Week ===
GDB Kernel Awarenes
-- Start merging Peter's and IBM patches
-- Look around for help on Kdump setup.
== This Week ==
* TCWG-1005 (6/10)
- Fixed firefox ICE
- Unfortunately that gives rise to another ICE with ipa-icf pass :(
Investigating if this
caused by the patch or a latent bug in ipa-icf.
- Builds well with chromium
* Validation (1/10)
- abe/extraconfig patches
- backport review
* Public Holiday (2/10)
* Misc (1/10)
- Meetings
== Next Week ==
- Continue ongoing tasks
~ Progress ~
* TCWG-1050, GDB 8.0 release. [7/10]
** Fix PR 19942, but looks my patch is completely wrong as I fully
misunderstood the "reference count" in GDB. Writing the v2.
** Intel btrace python interface discussion, a marathon discussion
about both the interface and implementation. Good thing is that we
agree that we need to change the interface. This takes most of my
time this week.
* TCWG-1040, Review SVE patches. [2/10]
Some discussions on avoid copying register contents to a local buffer
again, which is from my review comments to Alan's patch and my
suggested patch. Spend some time on understanding the zero
initialization of union in C++. I'll update my suggested patch.
* Update AArch32 GDB buildbot option, so we can get more reasonable
test result. [1/10]
~ Plan ~
* More remote tests for GDB 8.0 release.
* Fix PR 19942.
* One day off on Thu.
--
Yao Qi
[Eurollvm]
Attended, we have recorded our thoughts in EuroLLVM 2017 Recap doc
[TCWG-614] Range extension thunks
- I've finished my downstream implementation, and have written almost
all the lld tests I'd like to write
- Still need to test on real large programs such as libclang.so
- Made a start at breaking down the implementation into smaller
patches that can be sensibly upstreamed
Plans for next week
[TCWG-614]
- Aiming to start upstreaming on Monday, I'm expecting this to be
quite a drawn out process
- Continue testing on ARM Linux
Planned Absences
ACCU conference 2017 27-29 April
== Progress ==
* Validation
- helped with new llvm build scripts and jobs
- improvements to container scripts to cope with llvm's higher needs
in resources
- improved tcwg-regression tests
- various to remove dependencies on env variables
- comparison script now reports the associated .exp file name,
making it easier to reproduce a regression
- experimented with lava
- started work on benchmarking scripts
* GCC
- keeping an eye on trunk regressions
- update to qemu-2.8.0 introduced regressions in validation for
armeb on some atomic tests
* misc (conf-calls, meetings, emails, ....)
== Next ==
* Validation:
- hopefully nothing :)
* Benchmarking:scripting
== Progress ==
* EuroLLVM trip [6/10]
* [GlobalISel] AArch64 test-suite and self-host [TCWG-1074][2/10]
- Apple wants to switch the default O0 to GlobalISel for AArch64, so
we need to run tests and gather metrics
- I'm running the test-suite and selfhost with GlobalISel to see how
it performs
* Misc [2/10]
- Mailing list, code reviews, meetings, herding GlobalISel cats
(we're trying to open more communication channels with Apple so we can
unblock progress)
== Plan ==
* Wrap up TCWG-1074
* Learn more TableGen and do more code review
Hello all,
I've been using GCC 4.9.4 for a while now (arm-linux-gnueabi-gcc (Linaro
GCC 4.9-2017.01) 4.9.4), and I found this strange behavior:
In the library header (libm5op.h):
-----
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
void warm_and_run_(int64_t intervals_warm, int64_t intervals_run);
#ifdef __cplusplus
}
#endif
-----
In the library C file (m5op_arm_.c):
-----
#include "stdio.h"
#include <stdlib.h>
#include "libm5op.h"
void warm_and_run_(int64_t intervals_warm, int64_t intervals_run)
{
// Code here using args
}
-----
The code above is in
/home/fernando/work/benchs/SPEC_CPU2006v1.1-aarch64/m5op/ and compiled as a
library with GCC 6.3.1 and is ok:
~/work/toolchains/gcc-linaro-6.3.1-2017.02-x86_64_arm-linux-gnueabi/bin/arm-linux-gnueabi-gcc
-march=armv7-a -mfpu=neon-vfpv4 -mfloat-abi=softfp -O3
-fno-optimize-sibling-calls -c m5op_arm_.c -o m5op_arm_.o
~/work/toolchains/gcc-linaro-6.3.1-2017.02-x86_64_arm-linux-gnueabi/bin/arm-linux-gnueabi-gcc
-c m5op_arm.S -o m5op_arm.o
~/work/toolchains/gcc-linaro-6.3.1-2017.02-x86_64_arm-linux-gnueabi/bin/arm-linux-gnueabi-ar
rcs libm5op32.a m5op_arm_.o m5op_arm.o
The library is used in a source code compiled with the GCC 4.9.4 describe
at the begining.
In the C file:
-----
#include <libm5op.h>
S_regmatch(pTHX_ regnode *prog)
{
warm_and_run_(161, 818);
// Code continues
}
------
This source is compile with:
~/work/toolchains/gcc-linaro-4.9.4-2017.01-x86_64_arm-linux-gnueabi/bin/arm-linux-gnueabi-gcc
-c -o regexec.o -DSPEC_CPU -DNDEBUG -DPERL_CORE -static -marm
-march=armv7-a - mtune=generic-armv7-a -mfpu=neon-vfpv4
-mfloat-abi=softfp -O3 -fno-strict-aliasing -std=gnu89
-I/home/fernando/work/benchs/SPEC_CPU2006v1.1-aarch64/m5op/
-L/home/fernando/work/benchs/ SPEC_CPU2006v1.1-aarch64/m5op/
-DGEM5_ARM32=1 -DSPEC_CPU_ILP32 -DSPEC_CPU_LINUX_IA32 regexec.c
~/work/toolchains/gcc-linaro-4.9.4-2017.01-x86_64_arm-linux-gnueabi/bin/arm-linux-gnueabi-gcc
-static -marm -march=armv7-a -mtune=generic-armv7-a -mfpu=neon-vfpv4
-mfloat- abi=softfp -O3 -fno-strict-aliasing -std=gnu89
-I/home/fernando/work/benchs/SPEC_CPU2006v1.1-aarch64/m5op/
-L/home/fernando/work/benchs/SPEC_CPU2006v1.1-aarch64/m5op/ -DGEM5_ARM32=1
-DSPEC_CPU_ILP32 -DSPEC_CPU_LINUX_IA32 av.o deb.o doio.o doop.o
dump.o globals.o gv.o hv.o locale.o mg.o numeric.o op.o pad.o perl.o
perlapi.o perlio.o perlmain.o perly.o pp.o pp_ctl.o pp_hot.o pp_pack.o
pp_sort.o pp_sys.o regcomp.o regexec.o run.o scope.o sv.o taint.o toke.o
universal.o utf8.o util.o xsutils.o Base64.o Cwd.o Dumper.o HiRes.o IO.o
Peek.o attrs.o poll.o stdio.o DynaLoader.o MD5.o Storable.o Parser.o
specrand.o Hostname.o Opcode.o -lm -lm5op32 -lm5op32 -o
perlbench
Finally, the assembled code of S_regmatch has:
-----
af2d0: e3a000a1 mov r0, #161 ; 0xa1
af2d4: e3001332 movw r1, #818 ; 0x332
af2d8: e58d3018 str r3, [sp, #24]
af2dc: e58d2028 str r2, [sp, #40] ; 0x28
af2e0: fa02615c blx 147858 <warm_and_run_>
-----
So, this means that warm_and_run_ is assumed by GCC 4.9.4 to have 32 bits
arguments, while they are indeed 64 bits. This seems to be a bug for me.
The code in the library is correctly allocating 2*32 bits regs for each
argument.
For now, I'm using int32_t, and I just thought it could be useful to
feedback you guys.
--
Fernando A. Endo, Post-doc
INRIA Rennes-Bretagne Atlantique
France
== Progress ==
* Validation
- finally merged most of work of the past weeks
- main jobs are now using start-container scripts
- helped with new llvm build scripts and jobs
- abe initial config for gcc7: need to investigate a binutils build
problem in a trusty container
- improved tcwg-regression tests, identified a regression for bug-2123
- many validation-related patches to review
* GCC
- reported a regresion upstream
* misc (conf-calls, meetings, emails, ....)
- started discussing benchmarking
== Next ==
* Validation:
- a few patches pending review (to improve reports, debug-ability of
containers, ...)
- work on a new proposal to upgrade our qemu
- probably more cleanup needed in the jobs (slaves, basedir scm option, ...)
- improve tcwg-regression
- boot kernel after build
* Benchmarking: start to contribute
== Progress ==
o Linaro GCC/Validation (6/10)
* Validation/Infra patch reviews
* Upstream monitoring job
* Release automation:
- Reworking tcwg-release.sh
o Misc (4/10)
* Various meetings and discussions.
== Plan ==
o Focusing on release automation and validation
Achievements:
[TCWG-614] Range extension Thunks
- About 3 hours in total of rebasing due to upstream refactoring
- Have finished the non-linkerscript tests and fixed all the bugs
detected by them
- Started the linkerscript tests, no problems found so far
[TLS]
- Some explanation to upstream of how ARM TLS works
- Discovered that upstream have broken TLS global-dynamic for
executables, I have a fix but will need to write a test case.
Plans for next week:
- Euro LLVM Monday, Tuesday
- Continue with TCWG-614
-- Try and link clang (> 30 Mb) to test range thunks on some real programs
-- Aim to get something ready for upstream review by end of week, may
slip to beginning of next week depending on if I find any hard to
debug problems.
~ Progress ~
* TCWG-1050, GDB 8.0 release. [6/10]
** Pushed a fix to AArch64 process record bug on PRFM instruction.
AArch64 native test looks good now.
** Start to look at ARM native test, triage the fails in
watch-bitfields.exp. Test doesn't fail on old Linux kernel, likely
a kernel bug. Further analysis is needed.
** Request reverting Intel btrace python interface before release, as
they are too btrace-specific.
** Fixing a bug about thread_info refcount issue. Testing the patch.
* Discussion on RTOS awareness in debugging. OpenOCD people want GDB
aware more about different RTOSes. [1/10]
* TCWG-1040, SVE patches review, [2/10]
* Misc, [1/10]
~ Plan ~
* Take a look at native ARM testing, and cross testing.
* Post my fix to thread_info refcount issue.
--
Yao Qi
== Progress ==
* [ARM GlobalISel] Use TableGen for inst selector [TCWG-1037] [3/10]
- Got some patches ready but they depend on the TableGen support for
predicates, which has not been committed upstream yet
* [GlobalISel] Use proper calling conv for calls [TCWG-1051] [1/10]
- Patch accepted upstream, will commit next week
* Migrate scripts to Python 3 [TCWG-896] [1/10]
- Started migrating tcwg-release-tools to Python 3, still in progress
* Misc [5/10]
- Mailing lists, code reviews, buildbot monitoring, catching up after Connect
- LLVM social in Stockholm
- Fiddling with the new container for our LLVM buildmasters
== Plan ==
* Commit TCWG-1051, maybe TCWG-1037 too depending on upstream progress
* More GlobalISel code reviews
* TCWG-896
* Out of office for EuroLLVM (24 - 29 March)
[TCWG-614] Range extension Thunks
Worked all week on this. I've got a prototype that is nearly feature
complete. It passes the existing tests when run in a single pass. I'm
now trying to get it to run in multiple passes.
Plans
[TCWG-614] Range extension Thunks
Start adding tests for the new functionality and doubtless spending a
lot of time fixing problems. If I'm lucky I may have something that I
can at least in part send upstream for review by the end of the week.
~ Progress ~
* Three days off [6/10]
* TCWG-1050, GDB 8.0 release. [2/10]
Pushed in some patches fixing ARM reverse debugging bug.
Investigating a GDB internal error.
Review Python btrace stuff, still trying to make it more generic.
* Misc, [2/10], catch up emails
~ Plan ~
* TCWG-1050.
* Review IBM linux kernel awareness patches.
--
Yao Qi
The Linaro Toolchain Working Group (TCWG) is pleased to announce the
2017.03 snapshot of the Linaro GCC 6 source package.
This monthly snapshot[1] is based on FSF GCC 6.3+svn246148 and
includes performance improvements and bug fixes backported from
mainline GCC. This snapshot contents will be part of the 2017.05
stable[2] quarterly release.
This snapshot tarball is available on:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.3-2017.03/
Interesting changes in this GCC source package snapshot include:
* Updates to GCC 6.3+svn246148
* Backport of [Bugfix] [AArch64] PR target/71112 ICE with -fpie on
aarch64 ILP32 big-endian
* Backport of [Bugfix] [AArch64] PR target/71727 -O3 -mstrict-align
produces code which assumes unaligned vector accesses work
* Backport of [Bugfix] [AArch64] PR target/78382 ICE when compiling on
aarch64 in ILP32 mode with traditional thread local storage and pic
* Backport of [AArch32] Add vfpv2 and neon-vfpv3
* Backport of [AArch32] Fix assembly comment syntax in -mprint-tune-info
* Backport of [AArch64] Add commandline support for -march=armv8.3-a
* Backport of [AArch64] Expand DImode constant stores to two SImode
stores when profitable
* Backport of [AArch64] Fix aarch64 PGO bootstrap
* Backport of [AArch64] Fix exception handling for ILP32 aarch64
* Backport of [AArch64] Have the verbose cost model output output be
controllable
* Backport of [AArch64] Implement popcount pattern
* Backport of [AArch64] Optimized implementation of search_line_fast
for the CPP lexer
* Backport of [AArch64] Use new target pass registration framework for
FMA steering pass
* Backport of [Testsuite] [AArch32] Add Cortex-A15 tuning to
gcc.dg/uninit-pred-8_a.c
* Backport of [Testsuite] [AArch32] Skip optional_mthumb tests if GCC
has a default mode
* Backport of [Testsuite] [AArch32] Updating testcase unsigned-extend-2.c
* Backport of [Testsuite] [AArch64] Fix
gcc.dg/torture/float32-builtin.c with RTL checking
* Backport of [Testsuite] [AArch64] PR middle-end/78142 more registers
to be used for on gcc.target/aarch64/vector_initialization_nostack.c
* Backport of [Cleanup] [AArch32] Define arm_arch_core_flags in a single file
* Backport of [Cleanup] [AArch32] Remove unimplemented option -macps-float
Subscribe to the important Linaro mailing lists and join our IRC
channels to stay on top of Linaro development.
** Linaro Toolchain Development "mailing list":
http://lists.linaro.org/mailman/listinfo/linaro-toolchain
** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@
* Bug reports should be filed in bugzilla against GCC product:
http://bugs.linaro.org/enter_bug.cgi?product=GCC
* Interested in commercial support? inquire at "Linaro support":
mailto:support@linaro.org
[1]. Source package snapshots are defined when the compiler is only
put through unit-testing and full validation is not performed.
[2]. Stable source package releases are defined as releases where the
full Linaro Toolchain validation plan is executed.
== Progress ==
* 2 days out of office (Thursday & Friday)
* [ARM GlobalISel] Add support for lowering calls [TCWG-1038]
- Committed support for GEPs and 32-bit constants, which enables us
to put call parameters on the stack
- Proposed a fix for an AArch64 issue where the size of the stack
was computed incorrectly if the last parameter was sign- or
zero-extended into a stack slot
* Misc
- Mailing list etc.
== Plan ==
* Connect
2 day week:
== Activity ==
[TCWG-617] Range extension thunks
- rebased patch after coming back from holiday, took some time as
quite a bit had changed, patch still in upstream review.
- Have downstream patches to make inline thunks work with linker
scripts, will post for review next week.
== Plan ==
At linaro connect all next week
== Planned absences ==
Euro LLVM 27-28 March
~ Progress ~
* GDB 8.0 release, TCWG-1050, [5/10].
Release branch will be created on March 15th.
Fixed some instruction decoding in reverse debugging. Tested.
Added a unit test for arm process recording for some instructions.
To be posted upstream.
PR gdb/21165 is fixed.
* SVE GDB patches review, TCWG-1035, [3/10]
SVE patches review. One of Alan's patch is to remove some lines of
code written 19 years ago, which was to fix a bug at that moment.
A lot of archeology. Hopefully the author is still in RedHat, and
get more information on the fix. Alan's patch is correct.
* Upstream patches review. [2/10]
** Some python bindings on intel btrace. Make it more portable,
hopefully these python apis can be used for CoreSight in the
future.
~ Plan ~
* Linaro Connect.
* March 13th -- 15th, holiday.
--
Yao Qi
== Progress ==
* [ARM GlobalISel] Fix atomic loads/stores after r294993 [TCWG-1041] [1/10]
- For the moment we just bail out if we have any atomic loads /
stores. This is better than silently replacing them with non-atomic
operations.
* [ARM GlobalISel] Add support for lowering calls [TCWG-1038] [6/10]
- Committed support for calls with args/returns in registers (ints,
pointers, floating point)
- Found and reported a bug in the AArch64 backend
- Working on lowering stack arguments: committed support for stores,
still working on adding support for GEPs and constants so we can
actually compute the addresses that we have to store to
* Misc [3/10]
- Meetings, mailing lists, code reviews
- Connect slides
- Buildbots (reverted patches with flaky tests, fixed mips-specific
test to run only when mips is built)
== Plan ==
* Out of office on Thursday and Friday
* [ARM GlobalISel] Add support for lowering calls [TCWG-1038]
== Progress ==
* Validation
- more work on use of containers, ssh-agent & jenkins problems
- added an experimental job to prepare the migration to
the new scripts
* misc (conf-calls, meetings, emails, ....)
== Next ==
* Holidays next week
* Connect
Hi Guys,
Could you please let me know which release of toolchain support v8.2-A CPU? How to get it?
https://www.linaro.org/downloads/
Thanks
David
IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.
Oh dear...
Adding linaro-toolchain(a)lists.linaro.org to see what they have to say
(and linaro-uefi, because it's useful information for subscribers of that).
Regards,
Leif
On Tue, Feb 21, 2017 at 08:09:53PM +0000, Evan Lloyd wrote:
> To add to Alexei's comments:
> It seems there is a bug in the newer GCC Pre-processor that messes with the file case.
> (He is currently checking what file system flags might be affecting that, but older versions work fine).
>
> The questions I'd add are:
> Is there someone in Linaro who we might discuss the problem with (on the GCC side)? I think there are Linaro guys involved with it, and they may be able to tell us it is confusion on our part.
> Should we be trying to upstream the fix, or just wait for a new GCC?
>
> Regards,
> Evan
>
>
>
> From: Alexei Fedorov
> Sent: 21 February 2017 16:37
> To: ard.biesheuvel(a)linaro.org; ryan.harkin(a)linaro.org; leif.lindholm(a)linaro.org; Evan Lloyd; Sami Mujawar; Girish Pathak
> Cc: Mitch Ishihara; Alexei Fedorov
> Subject: Problem with building AML file from Dsdt.asl for Juno
>
>
> Hello,
>
>
>
> We are facing a problem when compiling Juno's Dsdt.asl file with the following GCC builds:
>
>
>
> gcc-linaro-5.3.1-2016.05-i686-mingw32_aarch64-elf
>
> gcc-linaro-6.1.1-2016.08-i686-mingw32_aarch64-elf
>
> gcc-linaro-6.2.1-2016.11-i686-mingw32_aarch64-elf
>
> gcc-linaro-6.3.1-2017.02-i686-mingw32_aarch64-elf
>
>
>
> which all show a similar error:
>
>
>
> ...
> Trim --source-code -l -o k:\Build\ArmJuno\DEBUG_GCC5\AARCH64\OpenPlatformPkg\Platforms\ARM\Juno\AcpiTables\AcpiTables\OUTPUT\.\Dsdt.iiii k:\Build\ArmJuno\DEBUG_GCC5\AARCH64\OpenPlatformPkg\Platforms\ARM\Juno\AcpiTables\AcpiTables\OUTPUT\.\Dsdt.iii
> "C:\ASL\iasl" -pk:\Build\ArmJuno\DEBUG_GCC5\AARCH64\OpenPlatformPkg\Platforms\ARM\Juno\AcpiTables\AcpiTables\OUTPUT\.\Dsdt.aml k:\Build\ArmJuno\DEBUG_GCC5\AARCH64\OpenPlatformPkg\Platforms\ARM\Juno\AcpiTables\AcpiTables\OUTPUT\.\Dsdt.iiii
> Error 6126 - Input file does not appear to be an ASL or data table source file
> Intel ACPI Component Architecture
> make: *** [Makefile:325: k:\Build\ArmJuno\DEBUG_GCC5\AARCH64\OpenPlatformPkg\Platforms\ARM\Juno\AcpiTables\AcpiTables\OUTPUT\Dsdt.aml] Error -1
>
>
>
> It looks like the problem is with GCC pre-processor running on Dsdt.i file (created after
>
> Trim --asl-file -o k:\Build\ArmJuno\DEBUG_GCC5\AARCH64\OpenPlatformPkg\Platforms\ARM\Juno\AcpiTables\AcpiTables\OUTPUT\.\Dsdt.i -i k:\Build\ArmJuno\DEBUG_GCC5\AARCH64\OpenPlatformPkg\Platforms\ARM\Juno\AcpiTables\AcpiTables\OUTPUT\inc.lst k:\OpenPlatformPkg\Platforms\ARM\Juno\AcpiTables\Dsdt.asl
>
> )
>
>
>
> See:
>
>
> "C:\gcc-linaro-6.3.1-2017.02-i686-mingw32_aarch64-elf\bin\aarch64-elf-gcc" -x c -E -include AutoGen.h -Ik:\OpenPlatformPkg\Platforms\ARM\Juno\AcpiTables -Ik:\Build\ArmJuno\DEBUG_GCC5\AARCH64\OpenPlatformPkg\Platforms\ARM\Juno\AcpiTables\AcpiTables\DEBUG -Ik:\ArmPkg -Ik:\ArmPkg\Include -Ik:\ArmPlatformPkg -Ik:\ArmPlatformPkg\Include -Ik:\ArmPlatformPkg\ArmVExpressPkg -Ik:\ArmPlatformPkg\ArmVExpressPkg\Include -Ik:\ArmPlatformPkg\ArmJunoPkg -Ik:\ArmPlatformPkg\ArmJunoPkg\Include -Ik:\EmbeddedPkg -Ik:\EmbeddedPkg\Include -Ik:\MdePkg -Ik:\MdePkg\Include -Ik:\MdePkg\Include\AArch64 -Ik:\MdeModulePkg -Ik:\MdeModulePkg\Include -Ik:\OpenPlatformPkg\Platforms\ARM\Juno\AcpiTablesk:\Build\ArmJuno\DEBUG_GCC5AARCH64OpenPlatformPkg\Platforms\ARM\Juno\AcpiTables\AcpiTables\OUTPUT\.\Dsdt.i > k:\Build\ArmJuno\DEBUG_GCC5\AARCH64\OpenPlatformPkg\Platforms\ARM\Juno\AcpiTables\AcpiTables\OUTPUT\.\Dsdt.iii
>
>
>
> For all GCC versions above, the 1st line of Dsdt.iii lists its name & full path in lowercase:
>
> # 1 "k:\\build\\armjuno\\debug_gcc5\\aarch64\\openplatformpkg\\platforms\\arm\\juno\\acpitables\\acpitables\\output\\dsdt.i"
>
>
>
> Compare it with Dsdt.iii after pre-processing by GCC from gcc-linaro-4.9.4-2017.01-i686-mingw32_aarch64-elf release:
>
> # 1 "k:\\Build\\ArmJuno\\DEBUG_GCC49\\AARCH64\\OpenPlatformPkg\\Platforms\\ARM\\Juno\\AcpiTables\\AcpiTables\\OUTPUT\\.\\Dsdt.i"
>
>
>
> For GCC 5.3.1 & above Dsdt.iiii created by
>
> Trim --source-code -l -o k:\Build\ArmJuno\DEBUG_GCC5\AARCH64\OpenPlatformPkg\Platforms\ARM\Juno\AcpiTables\AcpiTables\OUTPUT\.\Dsdt.iiii k:\Build\ArmJuno\DEBUG_GCC5\AARCH64\OpenPlatformPkg\Platforms\ARM\Juno\AcpiTables\AcpiTables\OUTPUT\.\Dsdt.iii
>
>
>
> has 0 length, which causes iASL compiler to fail with:
>
> Error 6126 - Input file does not appear to be an ASL or data table source file
>
>
>
> We've got a workaround solution for that problem which involves modification of \BaseTools\Conf\build_rule.template:
>
>
>
> In ASL section:
> [Acpi-Source-Language-File]
> <InputFile>
> ?.asl, ?.Asl, ?.ASL
>
>
>
> by replacing 3 lines as below:
>
>
> <Command.GCC, Command.GCCLD>
> # Trim --asl-file -o $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.i -i $(INC_LIST) ${src}
> # "$(ASLPP)" $(ASLPP_FLAGS) $(INC) -I${s_path} $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.i > $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.iii
> # Trim --source-code -l -o $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.iiii $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.iii
> "$(ASLPP)" $(ASLPP_FLAGS) $(INC) -I${s_path} ${src} > $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.i
> Trim --source-code -l -o $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.iiii $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.I
>
>
>
> Please share your opinion on that matter.
>
>
>
> Alexei.
>
>
>
>
>
>
>
>
>
> IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.
=== This Week ===
LLDB ARM/AArch64 hardware breakpoints [TCWG-717] [6/10]
-- Test on Arm hardware and fix issues.
-- Wrote breakpoint command based test-cases for multi-thread tests.
-- Wrote RSP packets based test-cases.
-- Code clean-up, formatting and re basing to latest code.
-- Submit final patch for review after adding tests and arm support.
Initial investigation on LLDB watchpoints set on variables [TCWG-1049] [1/10]
GDB Kernel Awareness [1/10]
-- Looked at STM landing team patches and tried setting up test environment.
LLDB BUD17 Presentation [1/10]
-- Spent some time deciding on content and information gathering.
Miscellaneous Activities [1/10]
-- Meetings, Emails etc.
=== Next Week ===
LLDB ARM/AArch64 hardware breakpoints [TCWG-717]
-- Work on review and up streaming.
LLDB BUD17 Presentation
-- Complete slide deck and submit for review.
GDB Kernel Awareness
-- Test submitted patches and develop understanding of project.
Further investigation on LLDB watchpoints set on variables [TCWG-1049]
1 day in office this week
== Activity ==
[TCWG-617] Range extension thunks
- Reworked patch to finalize dynamic content early and resubmitted for
upstream review
- Investigated what I'll need to do to handle linkerscripts
[BUD17]
Uploaded slide deck
== Plan ==
On holiday till Thursday 1st March
Deal with any last minute Linaro Connect stuff
Continue with Range Extension Thunk work.
== Planned absences ==
Holiday 21st Feb to 1st March
Linaro Connect 6th to 10th March
Euro LLVM 27-28 March
~ Progress ~
* AArch64 OpenOCD. TCWG-947 [4/10]
AArch64 support is merged to mainline. Works with one Hikey I
borrowed from Peter G.
Still doesn't work with mine.
* Upstream patch reviews. [2/10]
** Review Peter B.'s disassembly option patch.
** DWARF implicit_pointer big-endian patch.
** Python event before_prompt patch.
* Off on Thur and Fri. [4/10]
~ Plan ~
* Go to London again on Tue for Schengen visa.
* Back to GDB work, think about SVE GDB patches,
8.0 release, etc.
--
Yao Qi
== This Week ==
* gimplefe (5/10)
- Committed patch to add abs_expr
- Committed patch to fix PR79478
- Committed patch to add fma_expr
- Committed patch to fix ICE's in c_parser_gimple_postfix_expression
- Submitted patch to fix incorrect translation for an invalid
test-case, but decided to drop the
patch after discussing with Richard.
* TCWG-1005 (2/10)
- Formatting fixes
- Patch compiles SPEC2K (not benchmarked)
* PR79588 (1/10)
- Fix discussion with Jakub
* Misc (2/10)
- Meetings
- Connect slides
== Next Week ==
- TCWG-1010, TCWG-1005, gimple-fe
== Progress ==
* Validation
- more work on use of containers, ssh-agent & jenkins problem
- good progress
- committed several improvements to the production jobs too
* misc (conf-calls, meetings, emails, ....)
== Next ==
* ABE & Jenkins jobs patches reviews and bug fixes
* Holidays Feb 27th-March 3rd (week before Connect)
The Linaro Binary Toolchain
============================
The Linaro GCC 6.3-2017.02 Release is now available.
The GCC 6 Release series has significant changes from the GCC 5
release series. For an explanation of the changes please see the
following website:
https://gcc.gnu.org/gcc-6/changes.html
For help in porting to GCC 6 please see the following explanation:
https://gcc.gnu.org/gcc-6/porting_to.html
Download release packages from:
(sources)
http://releases.linaro.org/components/toolchain/gcc-linaro/6.3-2017.02/
(binaries)
http://releases.linaro.org/components/toolchain/binaries/6.3-2017.02/
Previous snapshots and release-candidates are at:
http://snapshots.linaro.org/components/toolchain/binaries/
Previous releases are at:
http://releases.linaro.org/components/toolchain/binaries/
Supported Targets
==================
The Linaro binary toolchain is a collection of x86-hosted GNU
cross-toolchains targeting a variety of ARM architecture targets.
Linaro TCWG provides these toolchains as a service to our members.
Due to hardware availability, system-image availability, validation
complexity, and user-base size, not all host and target toolchain
combinations can be validated by Linaro with the same rigor.
The most rigorously validated targets are little-endian and hardfloat
implementations of the 32-bit ARMv7 (arm), 32-bit ARMv8 (armv8), and
64-bit ARMv8 (aarch64) architectures. Linaro recommends those targets
to our members.
A full list of the supported arm and AArch64 target triples can be
found here:
https://collaborate.linaro.org/display/TCWGPUB/ARM+and+AArch64+Target+Tripl…
Host Requirements
==================
Linaro officially supports the current and previous Ubuntu LTS
releases (as of the time of this release). This does not mean that
the toolchain will not work on other/older Linux distributions. See
the following for the life-time of Ubuntu LTS releases.
https://wiki.ubuntu.com/Releases
The host system upon which the cross-compiler will run requires a
minimum of glibc 2.14, because of API changes to glibc's memcpy API.
https://bugs.linaro.org/show_bug.cgi?id=1869
Linaro recommends using the 64-bit x86_64 host toolchains as the
32-bit i686 host toolchains and the 32-bit mingw host toolchains will
only be provided as long as there is sufficient member interest to
justify their continued availability.
Package Versions
=================
Linaro GCC 6.3-2017.02
http://releases.linaro.org/components/toolchain/gcc-linaro/6.3-2017.02/
Linaro glibc 2.23 (linaro/2.23/master)
https://lists.gnu.org/archive/html/info-gnu/2016-02/msg00009.html
Linaro newlib 2.4-2016.03 (linaro_2.4-branch)
https://sourceware.org/ml/newlib/2016/msg00370.html
Linaro binutils 2.27 (linaro_binutils-2_27-branch)
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;a=blob_plain;f=bin…
Linaro GDB 7.12 (gdb-7.12-branch)
https://lists.gnu.org/archive/html/info-gnu/2016-10/msg00007.html
Linaro toolchain package git branches are hosted at:
http://git.linaro.org/toolchain
NEWS for GCC 6 (as of Linaro GCC 6.3-2017.02)
==============================================
* Previous versions of the Linaro GCC 6 toolchain were incorrectly
generating floating-point code for soft-float Linux targets
(arm-linux-gnueabi, and armeb-linux-gnueabi). This escaped detection
until recently because the soft-float targeted toolchains were
configured to use general-purpose registers for passing floating-point
values (which is what you would expect for soft-float toolchains) and
the intra-routine floating-code was not noticed.
The issue would only show up on targets that were run on hardware that
truly didn't have floating-point hardware where the kernel did not
trap and emulate floating-point routines. This has been solved in
Linaro GCC 6.3-2017.02-rc2 by configuring the toolchain (using
--with-float=soft) to generate code without any floating-point
instructions at all (-mfloat-abi=soft).
https://review.linaro.org/#/c/16968/2
This change should not break compatibility between existing binaries
compiled with these toolchains since the float-point parameter passing
ABI is still the same.
* A bug/regression in the compiler has been identified whereby the
target function that is invoked when calling a "weak" function
directly is the "strong" override, whereas when calling the function
via a pointer the "weak" implementation is used. This would be
noticed as inconsistent function invocation when invoking directly vs.
invoking via function pointer. This issue only affected 32-bit arm
targets. This regression has been fixed upstream and backported into
Linaro GCC 6.3-2017.02-rc2.
GCC PR target/78253: [5/6/7 Regression] [ARM] call weak function
instead of strong when called through pointer.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78253
Linaro bugzilla #2562: ARM GCC 5.2 call weak function instead of
strong when called through pointer
https://bugs.linaro.org/show_bug.cgi?id=2562
* MS Windows does not support symlinks and the MS Windows archive
extractor does not properly deep copy the symlink target
files/directories into the symlinked directory structure when
unpacking the toolchain archive. This causes problems with missing
dependencies when using the Linaro mingw toolchains, as identified in
the following bugs:
https://bugs.linaro.org/show_bug.cgi?id=2684https://bugs.linaro.org/show_bug.cgi?id=2192https://bugs.linaro.org/show_bug.cgi?id=2762
This has been solved by copying files rather than using symlinks when
the mingw targeted toolchain archives are created.
https://review.linaro.org/#/c/16415/
* Users of Linaro's toolchain have encountered problems when building
projects with Autotools (specifically libtool):
https://bugs.linaro.org/show_bug.cgi?id=2764
The Linaro binary toolchain release contained files with a .la suffix
as artifacts of the toolchain build process. These .la files are
helper files for libtool, but unlike a gcc install tree, they are not
position independent and contain full paths. Since these artifacts
contain absolute paths they can actually mislead user invocation of
libtool into not finding required libraries (because they reference
the build tree, not the install location) and hence breaking Autotools
builds. These *.la file artifacts have been removed from Linaro
toolchain binaries because they are unnecessary for users.
* The Linaro GCC 6.3-2017.01 snapshot added further enablement for
ARMv8-M and these have been incorporated into this release.
* Compiling and statically linking some SPEC2006int tests against
tcmalloc have been failing due to a problem with glibc's memory
allocator function overrides. This was fixed upstream:
https://sourceware.org/bugzilla/show_bug.cgi?id=20432
Backported into Linaro glibc 2.23:
commit 058b5a41d56b9a8860dede14d97dd443792d064b
Author: Florian Weimer <fweimer(a)redhat.com>
Date: Fri Aug 26 22:40:27 2016 +0200
malloc: Simplify static malloc interposition [BZ #20432]
* Host binaries for x86_64 linux hosts now have symbols and debug
information stripped in order to reduce the size of the toolchain
binary archives. This reduces the archive size from 1.5G to 600M for
aarch64-linux-gnu target with the gcc-6-branch.
* The GDB version was upgraded from GDB 7.11 in the Linaro GCC
6.1-2016.08 release to GDB 7.12 in the Linaro GCC 6.2-2016.11 release.
* The Linaro GCC 6.2-2016.10 snapshot added AArch32 support for ARMv8.2
and ARMv8m, as well as some AArch64 fixes for ARMv8.2, and bug fixes
merged from FSF GCC 6.2. This is available in the binary toolchain as
of Linaro GCC 6.2-2016.11.
* Basic tuning support for the Qualcomm qdf24xx was added to the Linaro
GCC 6.2-2016.10 snapshot and is available in the binary toolchain as
of Linaro GCC 6.2-2016.11.
* IFUNC was disabled for baremetal targets, as it was causing test-suite
failures, and is presently a Linux only feature.
* The gold linker was added to this binary release.
* Backported malloc_lock fix into Linaro newlib 2.4.
commit 2665915cfc46aa6403bb2efd473c523d3167e0cb
Author: Andre Vieira (lists) <Andre.SimoesDiasVieira(a)arm.com>
Date: Thu Jun 16 12:23:51 2016 +0100
Re-enable malloc_lock for newlib-nano
* Backported rawmemchr patch into Linaro newlib 2.4.
commit e7b1ee2ea6aa3ee1da41976407410e6202a098c5
Author: Wilco Dijkstra <Wilco.Dijkstra(a)arm.com>
Date: Thu May 12 16:16:58 2016 +0000
Add rawmemchr
* Backported strlen fix when using Thumb-2 and -Os -marm into Linaro
newlib 2.4.
commit 5c02bcc086a96b174e1b9e1445a4a1770070107a
Author: Thomas Preud'homme <thomas.preudhomme(a)arm.com>
Date: Wed May 11 17:18:48 2016 -0400
Fix strlen using Thumb-2 with -Os -marm
* Backported fix for semihosting ARM when heapinfo not provided by
debugger into Linaro newlib 2.4.
commit 5c9403eaf40951f8a4f55ed65f661b485ff44be7
Author: David Hoover <spm2(a)dangerous.li>
Date: Thu Apr 21 07:12:24 2016 +0200
Fixed semihosting for ARM when heapinfo not provided by debugger.
* Merged latest FSF glibc release/2.23/master into Linaro glibc 2.23.
* Backported __ASSUME_REQUEUE_PI check Linaro glibc 2.23 branch.
commit 2d20c3bf918cd94ebd4106693adb3a5c9272baba
Author: Adhemerval Zanella <adhemerval.zanella(a)linaro.org>
Date: Tue May 17 10:16:39 2016 -0300
Add runtime check for __ASSUME_REQUEUE_PI (BZ# 18463)
* Backported removal of __ASSUME_SET_ROBUST_LIST from Linaro glibc 2.23
branch.
commit bb8f09d72756186a3d82a1f7b2adcf8bc1fbaed1
Author: Adhemerval Zanella <adhemerval.zanella(a)linaro.org>
Date: Mon May 16 19:01:10 2016 -0300
Remove __ASSUME_SET_ROBUST_LIST
* Backported removal of __ASSUME_FUTEX_LOCK_PI from Linaro glibc 2.23
branch.
commit e48b4e7fed0de06dd7832ead48bea8ebc813a204
Author: Adhemerval Zanella <adhemerval.zanella(a)linaro.org>
Date: Mon May 16 10:35:25 2016 -0300
Remove __ASSUME_FUTEX_LOCK_PI
* Merged latest FSF binutils-2_27-branch into
linaro_binutils-2_27-branch.
* The libwinpthread DLL is now copied into the host bin directory to
satisfy mingw package dependencies.
* Backported GNU Linker fix.
commit fbc6c6763e70cb2376e2de990c7fc54c0ee44a59
Author: Nick Clifton <nickc(a)redhat.com>
Date: Tue Aug 23 09:45:11 2016 +0100
Fix seg-fault in ARM linker when trying to parse a binary file.
* Backported GNU Assembler fix for PR 20364
commit 5fe7ebe5ab43750abf8f490b785d99a1e598e7fd
Author: Nick Clifton <nickc(a)redhat.com>
Date: Fri Aug 5 10:37:57 2016 +0100
Fix the generation of alignment frags in code sections for AArch64.
https://sourceware.org/bugzilla/show_bug.cgi?id=20364
* Performance related backports from the following snapshots have been
included: Linaro GCC 6.1-2016.06, Linaro GCC 6.1-2016.07, Linaro GCC
6.1-2016.08, Linaro GCC 6.2-2016.09, Linaro GCC 6.2-2016.10, Linaro
GCC 6.2-2016.11, Linaro GCC 6.2-2016.12, and Linaro GCC 6.3-2017.01.
See the following Linaro GCC snapshots:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.1-2016.06/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.1-2016.07/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.1-2016.08/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.2-2016.09/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.2-2016.10/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.2-2016.11/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.2-2016.12/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.3-2017.01/
Contact Linaro
===============
File bugs at http://bugs.linaro.org
For Linaro member support see http://support.linaro.org
For Linaro community support email linaro-toolchain(a)lists.linaro.org
--
Ryan S. Arnold | Director - Linaro Core Technology and Tools
ryan.arnold(a)linaro.org | ryanarn on #linaro-tcwg @ freenode.irc.net
T: +1-612-424-1861
[TCWG-617] Range extension thunks
- Did some refactoring to allow addresses to be assigned to sections
prior to Thunk creation
-- In upstream review
- Investigated lld's implementation of linkerscripts and found out
that they will need some refactoring as well
-- Need to assign addresses more than once
-- Need to insert some thunks at precise points (Mips equivalent of
inline veneers), need to make sure that linkerscript won't reorder the
sections.
[BUD17]
Gave test run of presentation, cut down a lot of the slides as a result
== Plan ==
In office on Monday only, then Holiday to 1st March
- Finalise slides for connect, and work out how to submit them.
- Work out how to do Thunks and linker scripts cleanly
== Planned absences ==
Holiday 21st Feb to 1st March
Linaro Connect 6th to 10th March
Euro LLVM 27-28 March
== Progress ==
* [ARM GlobalISel] Add support for fp arguments [TCWG-1029] [7/10]
- Committed support for double precision hard float and soft-fp
* [ARM GlobalISel] Fix atomic loads/stores after r294993 [TCWG-1041] [1/10]
- Worked on a patch that I'll probably commit next week
* Misc [2/10]
- Meetings, mailing lists, code reviews
== Plan ==
* More code reviews
* More GlobalISel
Hi Denys,
adding linaro-toolchain ml for ABE related questions.
On 16 February 2017 at 06:12, Denys Dmytriyenko <denis(a)denix.org> wrote:
> Hi,
>
> I was wondering if there was a way to apply local patches to toolchain
> components (gcc, binutils, glibc, etc.) when building with ABE.
>
> The only way I know of right now is to mirror the upstream repository into own
> git tree, patch it and point ABE to it; or check it out locally, patch it and
> pass the resulting tarball to ABE build with --disable update flag.
>
> I know one of ABE's requirement is "Should build all toolchains with no
> custom patches", but it would be nice to be able to do so on top of official
> sources... Thoughts, comments?
>
> --
> Denys
The Linaro Binary Toolchain
============================
The Linaro GCC 6.3-2017.02-rc2 Release-Candidate is now available.
The GCC 6 Release series has significant changes from the GCC 5
release series. For an explanation of the changes please see the
following website:
https://gcc.gnu.org/gcc-6/changes.html
For help in porting to GCC 6 please see the following explanation:
https://gcc.gnu.org/gcc-6/porting_to.html
Download release-candidate packages from:
(sources)
http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.3-2017.02-rc2/
(binaries)
http://snapshots.linaro.org/components/toolchain/binaries/6.3-2017.02-rc2/
Previous snapshots and release-candidates are at:
http://snapshots.linaro.org/components/toolchain/binaries/
Previous releases are at:
http://releases.linaro.org/components/toolchain/binaries/
A description of the arm and Aarch64 target triples can be found at:
https://collaborate.linaro.org/display/TCWGPUB/ARM+and+AArch64+Target+Tripl…
Host Requirements
==================
Linaro officially supports the current and previous Ubuntu LTS
releases (as of the time of this release). This does not mean that
the toolchain will not work on other/older Linux distributions. See
the following for the life-time of Ubuntu LTS releases.
https://wiki.ubuntu.com/Releases
The host system upon which the cross-compiler will run requires a
minimum of glibc 2.14, because of API changes to glibc's memcpy API.
https://bugs.linaro.org/show_bug.cgi?id=1869
Package Versions
=================
Linaro GCC 6.3-2017.02-rc2
http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.3-2017.02-rc2/
Linaro glibc 2.23 (linaro/2.23/master)
https://lists.gnu.org/archive/html/info-gnu/2016-02/msg00009.html
Linaro newlib 2.4-2016.03 (linaro_2.4-branch)
https://sourceware.org/ml/newlib/2016/msg00370.html
Linaro binutils 2.27 (linaro_binutils-2_27-branch)
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;a=blob_plain;f=bin…
Linaro GDB 7.12 (gdb-7.12-branch)
https://lists.gnu.org/archive/html/info-gnu/2016-10/msg00007.html
Linaro toolchain package git branches are hosted at:
http://git.linaro.org/toolchain
NEWS for GCC 6 (as of Linaro GCC 6.3-2017.02-rc2)
==================================================
* Previous versions of the Linaro GCC 6 toolchain were incorrectly
generating floating-point code for soft-float Linux targets
(arm-linux-gnueabi, and armeb-linux-gnueabi). This escaped detection
until recently because the soft-float targeted toolchains were
configured to use general-purpose registers for passing floating-point
values (which is what you would expect for soft-float toolchains) and
the intra-routine floating-code was not noticed.
The issue would only show up on targets that were run on hardware that
truly didn't have floating-point hardware where the kernel did not
trap and emulate floating-point routines. This has been solved in
Linaro GCC 6.3-2017.02-rc2 by configuring the toolchain (using
--with-float=soft) to generate code without any floating-point
instructions at all (-mfloat-abi=soft).
https://review.linaro.org/#/c/16968/2
This change should not break compatibility between existing binaries
compiled with these toolchains since the float-point parameter passing
ABI is still the same.
* A bug/regression in the compiler has been identified whereby the
target function that is invoked when calling a "weak" function
directly is the "strong" override, whereas when calling the function
via a pointer the "weak" implementation is used. This would be
noticed as inconsistent function invocation when invoking directly vs.
invoking via function pointer. This issue only affected 32-bit arm
targets. This regression has been fixed upstream and backported into
Linaro GCC 6.3-2017.02-rc2.
GCC PR target/78253: [5/6/7 Regression] [ARM] call weak function
instead of strong when called through pointer.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78253
Linaro bugzilla #2562: ARM GCC 5.2 call weak function instead of
strong when called through pointer
https://bugs.linaro.org/show_bug.cgi?id=2562
* MS Windows does not support symlinks and the MS Windows archive
extractor does not properly deep copy the symlink target
files/directories into the symlinked directory structure when
unpacking the toolchain archive. This causes problems with missing
dependencies when using the Linaro mingw toolchains, as identified in
the following bugs:
https://bugs.linaro.org/show_bug.cgi?id=2684https://bugs.linaro.org/show_bug.cgi?id=2192https://bugs.linaro.org/show_bug.cgi?id=2762
This has been solved by copying files rather than using symlinks when
the mingw targetted toolchain archives are created.
https://review.linaro.org/#/c/16415/
* Users of Linaro's toolchain have encountered problems when building
projects with Autotools (specifically libtool):
https://bugs.linaro.org/show_bug.cgi?id=2764
The Linaro binary toolchain release contained files with a .la suffix
as artifacts of the toolchain build process. These .la files are
helper files for libtool, but unlike a gcc install tree, they are not
position independent and contain full paths. Since these artifacts
contain absolute paths they can actually mislead user invocation of
libtool into not finding required libraries (because they reference
the build tree, not the install location) and hence breaking Autotools
builds. These *.la file artifacts have been removed from Linaro
toolchain binaries because they are unnecessary for users.
* The Linaro GCC 6.3-2017.01 snapshot added further enablement for
ARMv8-M and these have been incorporated into this release.
* Compiling and statically linking some SPEC2006int tests against
tcmalloc have been failing due to a problem with glibc's memory
allocator function overrides. This was fixed upstream:
https://sourceware.org/bugzilla/show_bug.cgi?id=20432
Backported into Linaro glibc 2.23:
commit 058b5a41d56b9a8860dede14d97dd443792d064b
Author: Florian Weimer <fweimer(a)redhat.com>
Date: Fri Aug 26 22:40:27 2016 +0200
malloc: Simplify static malloc interposition [BZ #20432]
* Host binaries for x86_64 linux hosts now have symbols and debug
information stripped in order to reduce the size of the toolchain
binary archives. This reduces the archive size from 1.5G to 600M for
aarch64-linux-gnu target with the gcc-6-branch.
* The GDB version was upgraded from GDB 7.11 in the Linaro GCC
6.1-2016.08 release to GDB 7.12 in the Linaro GCC 6.2-2016.11 release.
* The Linaro GCC 6.2-2016.10 snapshot added AArch32 support for ARMv8.2
and ARMv8m, as well as some AArch64 fixes for ARMv8.2, and bug fixes
merged from FSF GCC 6.2. This is available in the binary toolchain as
of Linaro GCC 6.2-2016.11.
* Basic tuning support for the Qualcomm qdf24xx was added to the Linaro
GCC 6.2-2016.10 snapshot and is available in the binary toolchain as
of Linaro GCC 6.2-2016.11.
* IFUNC was disabled for baremetal targets, as it was causing test-suite
failures, and is presently a Linux only feature.
* The gold linker was added to this binary release.
* Backported malloc_lock fix into Linaro newlib 2.4.
commit 2665915cfc46aa6403bb2efd473c523d3167e0cb
Author: Andre Vieira (lists) <Andre.SimoesDiasVieira(a)arm.com>
Date: Thu Jun 16 12:23:51 2016 +0100
Re-enable malloc_lock for newlib-nano
* Backported rawmemchr patch into Linaro newlib 2.4.
commit e7b1ee2ea6aa3ee1da41976407410e6202a098c5
Author: Wilco Dijkstra <Wilco.Dijkstra(a)arm.com>
Date: Thu May 12 16:16:58 2016 +0000
Add rawmemchr
* Backported strlen fix when using Thumb-2 and -Os -marm into Linaro
newlib 2.4.
commit 5c02bcc086a96b174e1b9e1445a4a1770070107a
Author: Jeff Johnston <jjohnstn(a)redhat.com>
Date: Wed May 11 17:18:48 2016 -0400
Fix strlen using Thumb-2 with -Os -marm
* Backported fix for semihosting ARM when heapinfo not provided by
debugger into Linaro newlib 2.4.
commit 5c9403eaf40951f8a4f55ed65f661b485ff44be7
Author: David Hoover <spm2(a)dangerous.li>
Date: Thu Apr 21 07:12:24 2016 +0200
Fixed semihosting for ARM when heapinfo not provided by debugger.
* Merged latest FSF glibc release/2.23/master into Linaro glibc 2.23.
* Backported __ASSUME_REQUEUE_PI check Linaro glibc 2.23 branch.
commit 2d20c3bf918cd94ebd4106693adb3a5c9272baba
Author: Adhemerval Zanella <adhemerval.zanella(a)linaro.org>
Date: Tue May 17 10:16:39 2016 -0300
Add runtime check for __ASSUME_REQUEUE_PI (BZ# 18463)
* Backported removal of __ASSUME_SET_ROBUST_LIST from Linaro glibc 2.23
branch.
commit bb8f09d72756186a3d82a1f7b2adcf8bc1fbaed1
Author: Adhemerval Zanella <adhemerval.zanella(a)linaro.org>
Date: Mon May 16 19:01:10 2016 -0300
Remove __ASSUME_SET_ROBUST_LIST
* Backported removal of __ASSUME_FUTEX_LOCK_PI from Linaro glibc 2.23
branch.
commit e48b4e7fed0de06dd7832ead48bea8ebc813a204
Author: Adhemerval Zanella <adhemerval.zanella(a)linaro.org>
Date: Mon May 16 10:35:25 2016 -0300
Remove __ASSUME_FUTEX_LOCK_PI
* Merged latest FSF binutils-2_27-branch into
linaro_binutils-2_27-branch.
* The libwinpthread DLL is now copied into the host bin directory to
satisfy mingw package dependencies.
* Backported GNU Linker fix.
commit fbc6c6763e70cb2376e2de990c7fc54c0ee44a59
Author: Nick Clifton <nickc(a)redhat.com>
Date: Tue Aug 23 09:45:11 2016 +0100
Fix seg-fault in ARM linker when trying to parse a binary file.
* Backported GNU Assembler fix for PR 20364
commit 5fe7ebe5ab43750abf8f490b785d99a1e598e7fd
Author: Nick Clifton <nickc(a)redhat.com>
Date: Fri Aug 5 10:37:57 2016 +0100
Fix the generation of alignment frags in code sections for AArch64.
https://sourceware.org/bugzilla/show_bug.cgi?id=20364
* Performance related backports from the following snapshots have been
included: Linaro GCC 6.1-2016.06, Linaro GCC 6.1-2016.07, Linaro GCC
6.1-2016.08, Linaro GCC 6.2-2016.09, Linaro GCC 6.2-2016.10, Linaro
GCC 6.2-2016.11, Linaro GCC 6.2-2016.12, and Linaro GCC 6.3-2017.01.
See the following Linaro GCC snapshots:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.1-2016.06/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.1-2016.07/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.1-2016.08/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.2-2016.09/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.2-2016.10/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.2-2016.11/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.2-2016.12/http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.3-2017.01/
Contact Linaro
===============
File bugs at http://bugs.linaro.org
For Linaro member support see http://support.linaro.org
For Linaro community support email linaro-toolchain(a)lists.linaro.org
--
Ryan S. Arnold | Director - Linaro Core Technology and Tools
ryan.arnold(a)linaro.org | ryanarn on #linaro-tcwg @ freenode.irc.net
T: +1-612-424-1861
The Linaro Toolchain Working Group (TCWG) is pleased to announce the
2017.02 snapshot of both Linaro GCC 5 and Linaro GCC 6 source
packages.
Linaro GCC 6 monthly snapshot[1] is based on FSF GCC 6.3+svn245201 and
includes performance improvements and bug fixes backported from
mainline GCC. This snapshot contents will be part of the 2017.05
stable[2] quarterly release.
This snapshot tarball is available on:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.3-2017.02/
Interesting changes in this GCC source package snapshot include:
* Updates to GCC 6.3+svn245201
* Linaro BZ #2562: [PR target/78253] Call weak function instead of
strong when called through pointer
* Backport of [Bugfix] [AArch32] PR target/71270 Fix
neon_valid_immediate for big-endian
* Backport of [Bugfix] [AArch32] PR target/77439 Wrong code for
sibcall with longcall, APCS frame and VFP
* Backport of [Bugfix] [AArch32] PR target/78364 Add proper
restrictions to zero and sign_extract patterns operands
* Backport of [Bugfix] [AArch32] PR target/78694 Avoid invalid RTL
sharing in minipool code
* Backport of [Bugfix] [AArch32] PR target/79145 Fix xordi3 expander
for immediate operands in iWMMXt
* Backport of [Bugfix] [AArch64] PR target/78362 Make sure to only
take REGNO of a register
* Backport of [Bugfix] PR rtl-optimization/79121 Incorrect expansion
of extend plus left shift
* Backport of [AArch32] 1/2 Use generic_extra_costs in all remaining
tuning structs
* Backport of [AArch32] 2/2 Remove old rtx costs
* Backport of [AArch32] arm_neon.h: Add artificial and gnu_inline
* Backport of [AArch32] Improve Cortex-a53 integer scheduler
* Backport of [AArch32] Improve Thumb allocation order
* Backport of [AArch32] Merge negdi2 patterns
* Backport of [AArch64] 1/2 Add bfx attribute
* Backport of [AArch64] 2/2 Add bfx attribute
* Backport of [AArch64] Fix bootstrap on aarch64-*-freebsd
* Backport of [AArch64] Improve SHA1 scheduling
* Backport of [AArch64] Purge leftover occurrences of
aarch64_nopcrelative_literal_loads
* Backport of [AArch64] Split X-reg UBFIZ into W-reg LSL when possible
* Backport of [AArch64] Split X-reg UBFX into W-reg LSR when possible
* Backport of [AArch64] Tweak Cortex-A57 vector cost
* Backport of [Testsuite] [AArch64] PR target/77634 some vectorized
testcases fail with -mcpu=thunderx
* Backport of [Testsuite] [AArch64] PR target/77635 load/store pair
testcases need to use -mcpu=generic
* Backport of [Testsuite] Fix format string in AdvSIMD tests
* Backport of [Testsuite] Require shared effective target for some lto.exp tests
Linaro GCC 5 monthly snapshot[1] is based on FSF GCC 5.4+svn245200 and
includes performance improvements and bug fixes backported from
mainline GCC. This snapshot contents will be part of the next
maintenance release.
This snapshot tarball is available on:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.4-2017.02/
Interesting changes in this GCC source package snapshot include:
* Updates to GCC 5.4+svn245200
* Linaro BZ #2785: PR target/66785 Internal compiler error in record_operand_use
* Linaro BZ #2562: [PR target/78253] Call weak function instead of
strong when called through pointer
** Linaro Toolchain Development "mailing list":
http://lists.linaro.org/mailman/listinfo/linaro-toolchain
** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@
* Bug reports should be filed in bugzilla against GCC product:
http://bugs.linaro.org/enter_bug.cgi?product=GCC
* Interested in commercial support? inquire at "Linaro support":
mailto:support@linaro.org
~ Progress ~
* AArch64 OpenOCD. TCWG-947, [2/10]
After asking Peter G. about OpenOCD + Hikey, he sent me his working
Hikey+Cable to me.
* SVE GDB patches review. TCWG-1040, [4/10]
Review some patches, and suggest Alan how to split the patch to easily
make some progress.
Think about the needed change to GDB target description.
* Kernel awareness debugging patch review. [2/10]
Manage to write a small test case so that we can somehow test the new
feature in user space in gdb testsuite.
Think about how does Linaro move on about this project.
* Schengen visa application. [2/10]
Visa application centre doesn't accept my documents because my documents
copy are tow-side printed. Has to book another appointment and go to
London again .
~ Plan ~
* TCWG-947, Try opencod with Peter G.'s board.
* TCWG-1040, prototype of new GDB/GDBserver target description.
--
Yao Qi
== Progress ==
* Validation
- more work on use of containers
* GCC
- reported a few failures upstream
- added a few missing poly64_t intrinsics (arm, aarch64)
* misc (conf-calls, meetings, emails, ....)
== Next ==
* ABE & Jenkins jobs patches reviews and bug fixes
== This Week ==
* gimple-fe (4/10)
a) Add support for abs_expr
b) Add support for fma_expr
* TCWG-1010 (4/10)
- Continue working on prototype, dealing with unexpected ICE's :(
* Misc (2/10)
- Reading up on gcc's inliner
- Meetings
== Next Week ==
- TCWG-1010, TCWG-1005, gimple-fe
- Benchmarking LTO using spec2xxx-utils on tx1/tk1
=== This Week ===
LLDB ARM/AArch64 hardware breakpoints [TCWG-717] [9/10]
-- Submitted AArch64 hardware breakpoint patch for review.
-- Updates after upstream comments.
-- Added Arm hardware breakpoint support code.
-- Testing and debugging of Arm code on android arm device.
Miscellaneous Activities [1/10]
-- Meetings, Emails etc.
=== Next Week ===
LLDB ARM/AArch64 hardware breakpoints [TCWG-717]
-- Write breakpoint command based test-cases.
-- Write RSP packets based test-cases.
-- Submit patch for review after edits and upgrades.
GDB Kernel Awareness
-- Background study and understand existing patches
== Progress ==
[TCWG-617] Upstreamed a patch to make copy relocations use synthetic
sections. This allows us to remove the output section relative dynamic
relocation which is important for range extension Thunks
Did some design work for range extension Thunks.
Did some refactoring to merge PLT and IFunc PLT at maintainers request
[BUD17]
Researched my forthcoming Connect presentation and wrote about 3/5 of the slides
== Plan ==
Finish Connect presentation early next week as I'll be on holiday the
week before Connect.
Start implementing range extension Thunks.
== Progress ==
* [ARM GlobalISel] Add support for fp arguments [TCWG-1029] [5/10]
- Committed support for single precision hard float and soft-fp ABIs
- Work in progress on supporting double precision
* Misc [5/10]
- Meetings, mailing lists, code reviews
- Reverted / fixed a few patches that broke the buildbots
- Tested and uploaded binaries for release candidate 2 on AArch64
== Plan ==
* More GlobalISel
Hi All,
I am working on log10/qsort benchmarks on ARM64 (ARMv8) processor,
I want to check if we have experience with these benchmarks.
Actually i am looking for a compiler version which gives best results with
these benchmarks and specific compiler optimization (in my case is see O3
gives best numbers) ?
I have tried GCC-4.9 and GCC-6.2 with log10 benchmark and my observations
are:
1) With gcc 4.9 - 140 us
2) With GCC 6.2 - 150 us
My compilation flags are "-O3 -ftree-vectorize -funroll-all-loops --param
max-inline-insns-auto=550 --param case-values-threshold=30
-falign-functions=32 -ftracer"
So it seems like gcc-6.2 is better, am i missing something, should i use
some better compiler flags?
Thanks
-Bharat
~ Progress ~
* AArch64 OpenOCD. [6/10]
Solder and desolder the JTAG joint on HiKey. Tried different JTAG
options, but still can't get OpenOCD working.
* Patches review. [3/10]
** ILP32 GDB. Help cavium to reduce fails from 500 to 70.
GDB patch is OK, but there are still some regressions on ilp32
vs. lp64 on aarch64. Steve is still investigating on them.
** SVE GDB. Remove MAX_REGISTER_SIZE. Look people tend to agree
the way removing MAX_REGISTER_SIZE. Looking forward to Alan's
patches :)
** Kernel awareness debugging. Reviewed the cover letter of IBM's
patches. Want to share the common kernel debugging part between
IBM and Linaro.
* Schengen visa. [1/10] Fill in more in application form. Document
preparation.
~ Plan ~
* Kernel awareness debugging. Continue reviewing IBM's patches, and
figure out how to share the code.
* Go to London for visa application on Friday.
--
Yao Qi
