== This week ==
* Bugzilla 69663 - [ARM] Implement overflow arithmetic standard names (3/10)
- Successfully tested SImode add, sub, and neg overflow patterns
- Developed DImode addv and subv patterns
- Debugging failures in DImode overflow patterns
* TCWG 833 - [ARM] Exploit Wide Add operations when appropriate (2/10)
- Made changes corresponding to upstream review
- Rebased to latest trunk
- Resolved issues with new test cases
- Fixed formatting and style issues
- Resubmitted upstream for final review
- previous review gave conditional support for GCC 7
- Successfully retested
- One remaining expected failure on targets with wide add support
(including aarch64)
- Plan to file a upstream bugzilla
* Misc (1/10)
* Vacation (4/10)
== Next week ==
* Bugzilla 69663 - Debug and resolve DImode pattern failures
* Bugzilla 69008 - Restart investigation
== Progress ==
BUGS (8/10)
- PR69708:
* Posted a patch to fix.
- PR69589:
* Posted a patch to fix.
- PR66726:
* Omitted the patch bu that triggered a bootstrap failure for ppc64.
Reverted the patch and looking into it.
- Misc (2/10)
* gcc/bug list
* Undefined behaviors slides for connect
* Meetings
== Plan ==
* LTO
* bugs
== This Week ==
* LTO/IPA (8/10)
- TCWG-528: patch cross-tested on arm*-*-* and aarch64*-*-*
- Submitted patch upstream to add entry for aarch64 to target-supports.exp
- Experimenting with Kugan's ipa-vrp prototype
- Had a look at ipa-comdat
- Connect slides
* benchmarking (1/10)
- issues with deployment (TICKET-259)
- Using Bernie's workaround for the above issue
* Misc (1/10)
- Meetings
== Next Week ==
- LTO/IPA: tcwg-528, benchmarking, look at ipa-comdat enhancements.
- Investigate tcwg-310 with perf
- Finish connect slides
== Progress ==
* Conference (2/10)
- More EuroLLVM paper reviews, discussions
* Support (5/10)
- Looking at PR16275 (review D17141)
* Background (3/10)
- Code review, meetings, discussions, general support, etc.
- Buildbots broken, bisects, debugging
- Defining and posting Job ad (wanna work with us?)
# Progress #
* Support range stepping on arm-linux. TCWG-518. [4/10]
Preparatory patches are pushed in. Patches are being tested.
* Linaro connect. [3/10]
** Slides are done.
** Collect documents for visa application.
* GDB 7.11 release. TCWG-509. [1/10]
Release branch is created. Discuss on issue related to big endian,
but ARM is the only user of that code.
* Patch review, especially arm tracepoint support. [2/10].
# Plan #
* TCWG-518, upstream patches if tests are OK.
* TCWG-172, continue look at test parity between arm and x86_64.
* Go to London on Wed for visa application.
--
Yao
Hi Linaro Toolchain Group,
I have a question on the ldr instruction selection in the aarch64 backend.
Could someone help me in this regards, please?
I am trying to allow only type A instructions while disabling the type B.
Type A example: ldr x4, [x20,x1] ---> allow
Type B example: ldr x1, [x9,x3,lsl #3] ---> disable
Experiment/My Understanding -
aarch64_classify_address() returns true if rtx X is a valid address. If
allow_reg_index_p=true then it calls aarch64_classify_index().
aarch64_classify_index() identify the address mode of second operand (op1)
and accordingly calculate the shift.
If shift=0 then type A is generated otherwise Type B will be generated.
Thus if (shift != 0) then I am returning 'false' from
aarch64_classify_index().
-------------------------patch---------
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -3586,6 +3586,9 @@ aarch64_classify_index (struct aarch64_address_info
*info, rtx x,
if (GET_CODE (index) == SUBREG)
index = SUBREG_REG (index);
+ if (shift != 0)
+ return false;
if ((shift == 0 ||
(shift > 0 && shift <= 3
&& (1 << shift) == GET_MODE_SIZE (mode)))
---------------------------------------
Result -
Before change
ldr x0, [x13,x0,lsl #3]
After Change
lsl x1, x1, #3
ldr x0, [x15,x1]
Question -
How the returning 'false' from aarch64_classify_index() is resulting in the
selection of type A versus type B?
I could not find the function which is taking the decision based on return
from aarch64_classify_address().
Could someone please explain this process or point me to the relevant files
or code?
Please correct me if my understanding is wrong.
Thanks in advance for your time and patience.
--
with regards,
Virendra Kumar Pathak
The Linaro Toolchain Working Group (TCWG) is pleased to announce the
2016.02 snapshot of the Linaro GCC 5 source package.
This monthly snapshot[1] is based on FSF GCC 5.3+svn233233 and
includes performance improvements and bug fixes backported from
mainline GCC. This snapshot contents will be part of the 2016.05
stable [1] quarterly release.
This snapshot tarball is available on:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.3-2016.02/
Interesting changes in this GCC source package snapshot include:
* Updates to GCC 5.3+svn233233
* Backport of [Bugfix] [AArch32] PR target/69135: Mark ARMv8 vcvt
instructions as unconditional
* Backport of [Bugfix] [AArch32] PR target/69187 PR target/65624
* Backport of [Bugfix] [AArch32] PR target/69403: Bug in
thumb2_ior_scc_strict_it pattern
* Backport of [Bugfix] [AArch64] PR rtl-optimization/68796: Add
patterns for QImode and HImode comparison with zero
* Backport of [Bugfix] [AArch64] PR target/69176
* Backport of [Bugfix] PR target/69175
* Backport of [Bugfix] PR tree-optimization/67781
* Backport of [AArch32] Remove neon_reinterpret, use casts
* Backport of [AArch32] [RTEMS] Add Cortex-M7 multilib for FPU support
* Backport of [AArch64] Avoid emitting zero immediate as zero register
* Backport of [AArch64] Fix jit crash on aarch64
* Backport of [AArch64] Fix -mcpu/arch=native support for LSE
* Backport of [AArch64] Handle compare of zero_extract form of
TST-immediate in rtx costs
* Backport of [AArch64] Handle CSEL of zero_extended operands in rtx costs
* Backport of [AArch64] Properly reject invalid attribute strings
* Backport of [AArch64] Remove TODO (redundant type conversions) in arm_neon.h
* Backport of [Testsuite] [AArch32] Fix
gcc.c-torture/execute/loop-2b.c execution failure on cortex-m0
* Backport of [Testsuite] [AArch32] Fix g++.dg/pr67989.C test failure
when running with -march or -mcpu
* Backport of [Doc] Remove outdated text from lto.texi
Subscribe to the important Linaro mailing lists and join our IRC
channels to stay on top of Linaro development.
** Linaro Toolchain Development "mailing list":
http://lists.linaro.org/mailman/listinfo/linaro-toolchain
** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@
* Bug reports should be filed in bugzilla against GCC product:
http://bugs.linaro.org/enter_bug.cgi?product=GCC
* Interested in commercial support? inquire at "Linaro support":
mailto:support@linaro.org
[1]. Stable source package releases are defined as releases where the
full Linaro Toolchain validation plan is executed.
[2]. Source package snapshots are defined when the compiler is only
put through unit-testing and full validation is not performed.
Automated release benchmark Jenkins job - TCWG-348 [2/10]
* Drafted a job, it succeeds in dispatching to the uinstance
* Needs testing
Port to microinstance - TCWG-432 [5/10]
* Almost entirely fixing up the CPU2006 -> LAVA reporting
* Should now be able to report CPU2000 results as well
Misc [3/10]
* Mail/meetings/etc
* Connect slides
=Plan=
If builder is available, convert uinstance jobs to use it
Test release benchmark job
Produce image reports in microinstance
Attempt to finish backport benchmarking
Actually finish documentation
== Progress ==
LLDB development
-- Committed patch fixing return value handling on arm-linux-gnueabihf
[TCWG-228]
-- Finished work on handling aggregate types return values on
arm-linux-gnueabihf ABI. [TCWG-228] [5/10]
-- Submitted single and double precision handlers for upstream review.
[TCWG-228]
-- Started work on vector return values and aggregate types return
values with vector elements. [TCWG-228] [2/10]
Miscellaneous [1/10]
-- Meetings, emails, discussions etc.
Public Holiday [2/10]
-- Friday 5th February 2016
== Plan ==
LLDB development
-- Update and commit aggregate type return values on
arm-linux-gnueabihf ABI patch.
-- Investigate issues while stepping over library functions on
arm-linux-gnueabihf
-- Further work on vector return values on arm-linux-gnueabihf ABI
== Progress ==
o Connect slides (2/10)
* Undefined behavior (slides and review)
o GCC dev. (5/10)
* Remote testing sanitizing: found a solution in dejaGNU and GCC
implementation and test ongoing
* Analysed and closed PR69590
o Misc (3/10)
* Various meetings
* internal discussions
== Plan ==
o Continue on GCC testsuite
o FSF branch merge and 2016.02 snapshot
== This Week ==
* TCWG-319 (1/10)
- Updated patch and re-posted, queued for stage-1
- Regression with armeb for -fvect-cost-model=cheap
* TCWG-528 (1/10)
- speculatively increase alignment for global structs with arrays.
* Backports (3/10)
- committed backport: 232688
- r232631 (partially?) reverts 232330
- modified script to follow git log <file>
* benchmarking (2/10)
- 464.h264ref triggered ICE for -O3 -mfloat-abi=hard -mfpu=neon,
reduced it (PR69282)
- Benchmarking tcwg-310 on SPEC2006 - +0.10%
- Benchmarking INT SPEC2k6 for aarch64 without LTO complete.
* Slides (2/10)
- Read doc and created outline for most of slides,
- expect to be mostly complete by next week
* Misc (1/10)
- Meetings
== Next Week ==
- LTO benchmarking and slides
- TCWG-528
== Progress ==
- LTO and TCWG480 (5/10)
* Started testing with the prototype patch
* Still trying to figure out what is the best way to set_range_info
based on IPA
* i.e., how to find the SSA_NAME initialized with PARM_DECL
- Misc (5/10)
* gcc/bug list
* Undefined behaviors slides for connect
* Meetings
== Plan ==
* LTO
* bugs
== This week ==
* Backports (1/10)
- 232493 - Committed to Linaro branch
- 232727 - Committed to Linaro branch
- 232414 - Committed to Linaro branch
* Bugzilla 69663 - [ARM] Implement overflow arithmetic standard names (5/10)
- Implemented SImode add, sub, and neg overflow patterns
- add overflow patterns pass testing
- debugging failures in subv overflow patterns
* Bugzilla 69008 - gcc emits unneeded memory access when passing trivial
structs by value (ARM) (3/10)
- Investigating Dead Store Elimination pass to determine if code can
be improved
* Misc (1/10)
== Next week ==
* Personal days on February 8th and 9th
* Resolve bugzilla 69663 subv issues and work on DImode patterns
* Bugzilla 69008 - continue investigation
* Investigate test case failure on backport 232600
* Off from Mon. to Wed. [6/10]
# Progress #
* TCWG-518. Support range stepping on arm-linux. Ongoing. [2/10]
First do software single step in GDBserver side.
* TCWG-509. GDB 7.11 release. [1/10]
PR 19474, review Keith's patch. The patch is OK to mainline, but we
don't want to take risk shipping this patch to 7.11 release.
* Misc, register to Linaro Connect BKK16, and get clarifications on my
visa to Thailand. [1/10]
* Monitor the discussions on kenernel awareness upstreams, and comment
on the display of CPSR register.
# Plan #
* Finish Linaro Connect slides.
* TCWG-509. Anything needed for GDB 7.11 release.
* TCWG-518.
--
Yao
== Progress ==
* Validation
- disabled Auto Backport Engine until the patch selection
is improved to avoid saturating the builders with undesirable
builds.
- AArch64 bare metal validation (bug #2011). Submitted a patch
for dejagnu aarch64-fv8.exp, and one for our builders schroots.
Will need another patch, in ABE.
- timeout issues: no progress
* Misc (conf calls, meetings, emails, ....)
- internal discussions
== Next ==
* Validation
- debug timeout issues
- cleanup
== Progress ==
LLDB development
-- Submitted patch fixing return value handling on arm-linux-gnueabihf
[TCWG-228] [5/10]
-- float and double types handled in above patch did some more
investigation for handling structs [TCWG-228] [2/10]
-- Collecting LLDB status data, ran testsuite on different hardware
and minor investigation of fails and xfails [2/10]
Miscellaneous [1/10]
-- Meetings, emails, discussions etc.
== Plan ==
LLDB development
-- Update float/double return value patch after review and commit upstream
-- Submit a fix for handling structs as return types on arm-linux-gnueabihf
Public Holiday
-- Friday 5th February 2016
== Progress ==
- Public Holiday (2/10)
- LTO and TCWG480 (4/10)
* Started with a prototype for VRP
* Experimenting with simple test cases
- Misc (4/10)
* gcc/bug list
* LTO and Undefined behaviors slides for connect
* Meetings
== Plan ==
* LTO
* bugs
Hi,
My ARM target runs glibc 2.13 and I am having a hard time finding a
linaro toolchain for it. It seems like all the ones I have found ship with
glibc 2.15 (even old ones).
Where can I find the binaries for a linux toolchain that targets armhf
with glibc 2.13?
Thanks in advance
Port to microinstance - TCWG-432 [4/10]
* Went a few more rounds with the race condition, finally nailed it
* Tidied up transfer of Coremark results to LAVA
* Added metadata to LAVA results
* Sketched some charts using LAVA reporting
* Improved runtime benchmark logging
Benchmarking infrastructure documentation - TCWG-496 [2/10]
* Most everything drafted, some docs finished
Controlled image builds - TCWG-360 [2/10]
* Reached a better understanding of what a hwpack is
* Generated a few images, none of them booted
Misc [2/10]
=Plan=
Benchmarking-102 slides for Connect
Finish documentation
Backport benchmarking
If builder shows up in microinstance, evaluate stability of its Junos
o Teaching activity (3/10)
== Progress ==
o Infra/Validation (1/10)
* A couple of patches for release script.
o GCC dev. (2/10)
* Remote testing sanitizing: still digging.
o Misc (4/10)
* Various meetings (usual ones and internal ones)
* Backports reviews
== Plan ==
o Continue on GCC testsuite and opened cards.
Port to microinstance - TCWG-432 [2/10]
* More fallout from attempts to fix race condition
* Began cleaning job submission YAML
Controlled image builds - TCWG-360 [1/10]
* (Re)learned how to generate images from hwpack + filesystem
Struck down by flu [7/10]
== This week ==
* Backports (3/10)
- 232493 - Unrelated aarch64 failure and non-thumb asan test on
aarch32 big endian
- 232600 - All tests pass
- 232727 - unrelated non-thumb test failure
asan/deep-thread-stack-1.c asan/deep-thread-stack-1.c)
* Bugzilla 68543 - [AArch64] Implement overflow arithmetic standard
names (3/10)
- Development halted due to submission of related patch by Richard
Henderson:
- https://gcc.gnu.org/ml/gcc-patches/2016-01/txt0WQOxpo0_5.txt
- Began implementation of aarch32 related patch
* Bugzilla 69008 - gcc emits unneeded memory access when passing trivial
structs by value (ARM) (3/10)
- Additional code is being generated in default abi case with
structure alignment equal to 8
- Investigating Dead Store Elimination pass to determine if code can
be improved
* Misc (1/10)
== Next week ==
* Create new bugzilla for aarch32 to implement overflow standard names
and continue implementation
* Bugzilla 69008 - continue investigation
* Work on backports as necessary
== This Week ==
* PR43721 (1/10)
- Submitted upstream.
- GIMPLE parts approved by Richard, wants someone else to approve
rtl-expansion bits.
* benchmarking (1/10)
- benchmarking tcwg-310 on cortex-a53, cortex-a57, r1-a12, cortex-a17
- submitted job for INT benchmarks for SPEC2006 for aarch64
* backports (2/10)
- r232688 automated backport build failed for aarch64-linux-gnu on
tcwg-backport-gerrit:
Unrecognized macro 'GERRIT_PATCHSET_REVISION' in '#664-
${GERRIT_PATCHSET_REVISION,length=8}'
Build successful on tcwg-backport-maxim
- r232737, r232631 have at least 4 dependencies.
- wrote bare bones script to find dependencies for revision
* ccp (2/10)
- enhancement to hoist stmt thru phi with all constant args
- patch: http://people.linaro.org/~prathamesh.kulkarni/ccp-mov.diff
- rejected by Richard, since PRE handles this case when it's
trivially profitable and phiprop does similar transform. In general,
it's not profitable to have this transform included.
* Public Holiday (2/10)
* Misc (2/10)
- Meetings
- Slides: short & long term activities
== Next Week ==
- PR43721: look at using define_expand instead of hook, add test-cases
and few nits
- tcwg-319 - analyse with perf
- LTO INT benchmarking for arm, aarch64 and x86
- LTO Slides
# Progress #
In general, GDB mainline is in a good state. All known bugs are fixed,
but still have some patches pending for review. The release can be
created after these pending patches are in.
* Fix fail in gdb.base/interrupt-noterm.exp. TCWG-517. Done. [2/10]
* Fix fail in gdb.fortran/vla-value.exp. TCWG-521. Done. [1/10]
* PR 19474. [3/10]
Tried different approaches, but still cause regression.
Fortunately get the right maintainer involved. Will discuss with
him on this bug next week.
* Range stepping doesn't work on arm-linux, which slows down stepping
over a line of source. TCWG-518. [2/10]
* Prepare slides for Linaro Connect. [2/10]
# Plan #
* Off on Mon. to Wed.
* Linaro connect slides.
* Thailand visa.
* Other issues on GDB 7.11 release, if any.
--
Yao
The Linaro Toolchain Working Group is pleased to announce the availability
of the Linaro Stable Binary Toolchain GCC 5.2-2015.11-2 Release Archives.
http://releases.linaro.org/components/toolchain/binaries/5.2-2015.11-2/http://releases.linaro.org/components/toolchain/gcc-linaro/5.2-2015.11-2/
These archives provide cross-toolchain executables (compiler, debugger,
linker, etc.) and shared libraries (libstdc++, libc, etc.) that target ARM
or Aarch64 GNU/Linux and bare-metal environments. The cross-toolchain
binaries execute on a Linux or MS Windows (under mingw32) host
operating-system.
Please evaluate this release-candidate for correctness. Linaro will shortly
spin the Linaro GCC 5.2-2015.11-2 release if this release-candidate passes
stakeholder validation.
For bugs related to this release-candidate please email
linaro-toolchain(a)lists.linaro.org or file a bug at
https://bugs.linaro.org/enter_bug.cgi?product=Linux%20Binary%20toolchain
NEWS
* GCC 5.2 2015.11-2
The Linaro GCC 5.2 2015.11-2 binary toolchain release respin is built from
the Linaro GCC-5.2-2015.11-2 release source archive. The Linaro
GCC-5.2-2015.11-2 release source archive is derived from the same sources
as the Linaro GCC-5.2-2015.10 snapshot source archive.
This release includes fixes for the issues specified in the Linaro GCC 5.2
2015.11-2-rc1 release-candidate.
* GCC 5.2 2015.11-2-rc1
The Linaro GCC 5.2 2015.11-2-rc1 binary toolchain release-candidate is
built from the Linaro GCC-5.2-2015.11-2-rc1 release-candidate source
archive. The Linaro GCC-5.2-2015.11-2-rc1 release-candidate source archive
is derived from the same sources as the Linaro GCC-5.2-2015.10 snapshot
source archive.
This release-candidate includes fixes for the following issues:
Linaro bug 1995 identified a problem where the installed sysroot was not in
the place that the compiler expected the sysroot to be located by default.
This is fixed in the Linaro GCC 5.2 2015.11-2-rc1 binary toolchain
release-candidate.
* GCC 5.2 2015.11-1
The Linaro GCC 5.2 2015.11-1 binary toolchain release is built from the
Linaro GCC-5.2-2015.11-1 release source archive. The Linaro
GCC-5.2-2015.11-1 release source archive is derived from the same sources
as the Linaro GCC-5.2-2015.10 snapshot source archive.
This release includes fixes for the issues specified in the Linaro GCC 5.2
2015.11-1-rc1 release-candidate.
* GCC 5.2 2015.11-1-rc1
The Linaro GCC 5.2 2015.11-1-rc1 binary toolchain release-candidate is
built from the Linaro GCC-5.2-2015.11-1-rc1 release-candidate source
archive. The Linaro GCC-5.2-2015.11-1-rc1 release-candidate source archive
is derived from the same sources as the Linaro GCC-5.2-2015.10 snapshot
source archive.
This release-candidate includes fixes for the following issues:
The arm-eabi-none multi-libs are now available in the toolchain sysroot as
a fix for Linaro bug 1920 and Linaro bug 1922 .
Linaro glibc 2.21 now provides ld-linux-aarch64_be.so.1 .
Linux 32-bit host binaries for the ARMv7 Linux hard float cross-toolchain
(arm-linux-gnueabihf triple).
* GCC 5.2 2015.11
The Linaro GCC 5.2 2015.11 binary toolchain release is built from the
Linaro GCC-5.2-2015.11 release source archive. The Linaro GCC-5.2-2015.11
release source archive is derived from the same sources as the Linaro
GCC-5.2-2015.10 snapshot source archive.
* GCC 5.2 2015.11-rc1
The Linaro GCC 5.2 2015.11-rc1 binary toolchain release-candidate is built
from the Linaro GCC-5.2-2015.11 release-candidate source archive. The
Linaro GCC-5.2-2015.11-rc1 release-candidate source archive is derived from
the same sources as the Linaro GCC-5.2-2015.10 snapshot source archive.
--
Ryan S. Arnold
Linaro Toolchain Working Group - Engineering Manager
www.linaro.org
The Linaro Toolchain Working Group is pleased to announce the availability
of the Linaro Stable Binary Toolchain GCC 5.2-2015.11-2-rc1
Release-Candidate Archives.
http://snapshots.linaro.org/components/toolchain/binaries/5.2-2015.11-2-rc1/http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.2-2015.11-2-r…
These archives provide cross-toolchain executables (compiler, debugger,
linker, etc.) and shared libraries (libstdc++, libc, etc.) that target ARM
or Aarch64 GNU/Linux and bare-metal environments. The cross-toolchain
binaries execute on a Linux or MS Windows (under mingw32) host
operating-system.
Please evaluate this release-candidate for correctness. Linaro will shortly
spin the Linaro GCC 5.2-2015.11-2 release if this release-candidate passes
stakeholder validation.
For bugs related to this release-candidate please email
linaro-toolchain(a)lists.linaro.org or file a bug at http://
https://bugs.linaro.org/enter_bug.cgi?product=Linux%20Binary%20toolchain
NEWS
* GCC 5.2 2015.11-2-rc1
The Linaro GCC 5.2 2015.11-2-rc1 binary toolchain release-candidate is
built from the Linaro GCC-5.2-2015.11-2-rc1 release-candidate source
archive. The Linaro GCC-5.2-2015.11-2-rc1 release-candidate source archive
is derived from the same sources as the Linaro GCC-5.2-2015.10 snapshot
source archive.
This release-candidate includes fixes for the following issues:
Linaro bug 1995 identified a problem where the installed sysroot was not in
the place that the compiler expected the sysroot to be located by default.
This is fixed in the Linaro GCC 5.2 2015.11-2-rc1 binary toolchain
release-candidate.
* GCC 5.2 2015.11-1
The Linaro GCC 5.2 2015.11-1 binary toolchain release is built from the
Linaro GCC-5.2-2015.11-1 release source archive. The Linaro
GCC-5.2-2015.11-1 release source archive is derived from the same sources
as the Linaro GCC-5.2-2015.10 snapshot source archive.
This release includes fixes for the issues specified in the Linaro GCC 5.2
2015.11-1-rc1 release-candidate.
* GCC 5.2 2015.11-1-rc1
The Linaro GCC 5.2 2015.11-1-rc1 binary toolchain release-candidate is
built from the Linaro GCC-5.2-2015.11-1-rc1 release-candidate source
archive. The Linaro GCC-5.2-2015.11-1-rc1 release-candidate source archive
is derived from the same sources as the Linaro GCC-5.2-2015.10 snapshot
source archive.
This release-candidate includes fixes for the following issues:
The arm-eabi-none multi-libs are now available in the toolchain sysroot as
a fix for Linaro bug 1920 and Linaro bug 1922 .
Linaro glibc 2.21 now provides ld-linux-aarch64_be.so.1 .
Linux 32-bit host binaries for the ARMv7 Linux hard float cross-toolchain
(arm-linux-gnueabihf triple).
* GCC 5.2 2015.11
The Linaro GCC 5.2 2015.11 binary toolchain release is built from the
Linaro GCC-5.2-2015.11 release source archive. The Linaro GCC-5.2-2015.11
release source archive is derived from the same sources as the Linaro
GCC-5.2-2015.10 snapshot source archive.
* GCC 5.2 2015.11-rc1
The Linaro GCC 5.2 2015.11-rc1 binary toolchain release-candidate is built
from the Linaro GCC-5.2-2015.11 release-candidate source archive. The
Linaro GCC-5.2-2015.11-rc1 release-candidate source archive is derived from
the same sources as the Linaro GCC-5.2-2015.10 snapshot source archive.
--
Ryan S. Arnold
Linaro Toolchain Working Group - Engineering Manager
www.linaro.org
Hi!
When using the linaro-4.9-2015.05 toolchain on the Linux master and on Linux stable releases
I am seeing a build issue below when using the allyesconfig. This does not seem to occur on the 5.2 tool chain.
We cannot move to 5.2 tool chain for our releases as they are based on 4.9.
LD init/built-in.o
arch/arm/kernel/built-in.o:(.text.fixup+0x1d4): relocation truncated to fit: R_ARM_JUMP24 against `.text.unlikely'
arch/arm/kernel/built-in.o:(.text.fixup+0x1e0): relocation truncated to fit: R_ARM_JUMP24 against `.text.unlikely'
arch/arm/kernel/built-in.o:(.text.fixup+0x1ec): relocation truncated to fit: R_ARM_JUMP24 against `.text.unlikely'
drivers/built-in.o: In function `combiner_handle_cascade_irq':
:(.text+0x834): relocation truncated to fit: R_ARM_CALL against symbol `_raw_spin_lock' defined in .spinlock.text section in kernel/built-in.o
:(.text+0x868): relocation truncated to fit: R_ARM_CALL against symbol `_raw_spin_unlock' defined in .spinlock.text section in kernel/built-in.o
drivers/built-in.o: In function `hip04_irq_set_type':
:(.text+0xad0): relocation truncated to fit: R_ARM_CALL against symbol `_raw_spin_lock' defined in .spinlock.text section in kernel/built-in.o
:(.text+0xb10): relocation truncated to fit: R_ARM_CALL against symbol `_raw_spin_unlock' defined in .spinlock.text section in kernel/built-in.o
drivers/built-in.o: In function `hip04_raise_softirq':
:(.text+0xc8c): relocation truncated to fit: R_ARM_CALL against symbol `_raw_spin_lock_irqsave' defined in .spinlock.text section in kernel/built-in.o
:(.text+0xdc8): relocation truncated to fit: R_ARM_CALL against symbol `_raw_spin_unlock_irqrestore' defined in .spinlock.text section in kernel/built-in.o
drivers/built-in.o: In function `hip04_irq_set_affinity':
:(.text+0xefc): relocation truncated to fit: R_ARM_CALL against symbol `_raw_spin_lock' defined in .spinlock.text section in kernel/built-in.o
:(.text+0xf78): additional relocation overflows omitted from the output
make: *** [vmlinux] Error 1
Please advise to how to resolve this issue within the 4.9 Linaro tool chain
Dan
--
------------------
Dan Murphy
== Progress ==
* Support (5/10)
- Bug triage: reviewing the 300+ bugs on ARM
- remaining 220 bugs are all still pertinent
* Release (2/10)
- Woes due to GCC ABI change may delay 3.8.0 release
- Tested on both ARM and AArch64 with old environment, all green.
* Background (3/10)
- Code review, meetings, discussions, general support, etc.
- EuroLLVM, FOSDEM preparations, ARM sync
o Teaching activity (2/10)
== Progress ==
o Linaro GCC (2/10)
* Delivered 2016.01-1 Snapshot respin with fix for Linaro PR #2001
* Gave some support on backports
o Infra/Validation (1/10)
* Compared ABE master results.
o GCC dev. (2/10)
* Identified the way testcases are uploaded on the remote target in
cross validation as the root cause of validation instabilities. Digging
into GCC .exp files and DejaGNU to fix it cleanly.
o Misc (3/10)
* Various meetings
* Start a backport/validation document
== Plan ==
o Continue backports/validation document
o Continue on the ongoing cards opened
== Progress ==
LLDB development
-- Debugging of return value related issue coming up on chromebook ARM
[TCWG-228] [2/10]
-- Setup of Arm testing on AArch64 using chroot on highkey [TCWG-231] [1/10]
-- Investigation of failures when setting watchpoint on vector
variables [TCWG-231] [4/10]
Miscellaneous [3/10]
-- Meetings, emails, discussions etc.
-- Travel for Thailand visa application
== Plan ==
LLDB development
-- Try a fix of return value related issue coming up on chromebook ARM
-- Submit fix for failures when setting watchpoint on vector variables
-- Mark triaged failures with xfail decorators and bug numbers.
== Progress ==
LLDB development
-- Triage testsuite failures on AArch64 highkey [TCWG-231] [5/10]
-- Triage testsuite failures on chromebook (armel) [TCWG-228] [3/10]
Miscellaneous [2/10]
-- Meetings, emails, discussions etc.
-- Documents preparation for Thailand visa
== Plan ==
LLDB development
-- Create chroots for armhf and armel testing on AArch64 highkey board
-- Investigate ABI related issues when returning values on armel and armhf
-- Further bug triage and mark triaged failures with xfail decorators
and bug numbers.
Miscellaneous
-- Travel for Thailand visa application submission.
== This Week ==
* PR43721 (4/10)
- Patch review from Jim
- Bootstrapped and tested on x86, cross-tested with arm-linux-gnueabi
- Looking at regressions with arm-linux-gnueabi
- Wrote test-cases
* Benchmarking (2/10)
- lto spec2006 benchmarking
* Backport (1/10)
- Build successful for r232440 and r232442, failed for r232442
* PR24293 (1/10)
- Addressed comments by Marek and committed to trunk
* Misc (2/10)
- Meetings
- PR69133 - Fixed by Honza. Instead of gating on
lto_file_data as I did in my patch, gating on gimple_has_body_p()
was more suitable.
- Awaiting upstream response for tcwg-319
- Connect Slides outline, read doc on tree-ssa propagation and lto
plugin driver.
== Next Week ==
Continue ongoing tasks
== Progress ==
* Validation
- no progress in timeout issues: still didn't manage to access the logs
- 1st backport workshop successful in the team. We can increase
the difficulty for the next time :)
- initial prototype (naive) of an auto-backporter (using backflip)
when the patch are selected for inclusion
* GCC
- TCWG-485/PR68620: patch under review
- TCWG-484/target attributes testsuite fixes: committed.
- bug #1994: provided woraround to kernel team.
Related to GCC PR63304. Working on a further patch
for GCC.
* Misc (conf calls, meetings, emails, ....)
== Next ==
* Validation:
- debug timeout issues
- extended validation
* GCC:
- bug fixing
# Progress #
* Fix the arm software single step regression. [3/10]. Done.
* TCWG-503 Done.
* TCWG-491, have a patch to avoid GDB crash. Patch is pending for
review.
* TCWG-517. [2/10]
Fix fail in gdb.base/interrupt-noterm.exp. Patch is posted.
* TCWG-514. [3/10]
Fix new fails in foll-exec.exp and foll-vfork.exp. Patch is pending
for review.
* TCWG-509, GDB 7.11 release. [2/10]
GDB is in a good shape to create 7.11 branch except PR 19474. Go
through GDB test results and no ARM or AArch64 specific issues.
# Plan #
* TCWG-509, GDB 7.11 release.
* Upstream patch review.
--
Yao
The Linaro Toolchain Working Group (TCWG) announces the 2016.01-1
snapshot of the Linaro GCC 5 source package.
This package is a respin of 2016.01 source package and contains a fix
for Linaro bugzilla’s PR #2001:
* [AArch64] ICE in final_scan_insn on aarch64-linux-gnu.
This snapshot tarball is available on:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/5.3-2016.01-1/
Original release notes from 2016.01 source package can be find below:
---------------------------------------------------------------------------------------------------------------------
The Linaro Toolchain Working Group (TCWG) is pleased to announce the
2016.01 snapshot of the Linaro GCC 5 source package.
This monthly snapshot[1] is based on FSF GCC 5.3+svn232321 and
includes performance improvements and bug fixes backported from
mainline GCC. This snapshot contents will be part of the 2016.02
stable [1] quarterly release.
Interesting changes in this GCC source package snapshot include:
* Updates to GCC 5.3+svn232321
* Fixes Linaro Bugzillas: #1982, #1980
* Backport of [BugFix] [AArch32] PR 68149 Fix ICE in unaligned_loaddi split
* Backport of [BugFix] [AArch32] PR target/68214: Delete
IP-reg-clobbering call-through-mem patterns
* Backport of [BugFix] [AArch32] PR target/68390
* Backport of [Bugfix] [AArch64] PR rtl-optimization/68796 Add
compare-of-zero_extract pattern
* Backport of [BugFix] [AArch64] PR target/68696 FAIL:
gcc.target/aarch64/vbslq_u64_1.c scan-assembler-times bif\tv 1
* Backport of [BugFix] PR rtl-optimization/68381
* Backport of [ARMv8.1] [AArch32] Add ACLE feature macro for ARMv8.1
instructions
* Backport of [ARMv8.1] [AArch32] Add ACLE intrinsics vqrdmlah and vqrdmlsh
* Backport of [ARMv8.1] [AArch32] Add ACLE intrinsics vqrdmlah_lane
and vqrdmlsh_lane
* Backport of [ARMv8.1] [AArch32] Add patterns for new instructions
* Backport of [ARMv8.1] [AArch32] Add support for ARMv8.1
* Backport of [ARMv8.1] [AArch32] Multilib support for ARMv8.1.
* Backport of [ARMv8.1] [AArch32] Support ARMv8.1 ARM tests
* Backport of [AArch32] [AArch32] Fix armv8.1 support at configure time
* Backport of [AArch32] Add attribute for compatibility with ARM pipeline models
* Backport of [AArch32] Fix vector TYPE_MODE in streaming-out
* Backport of [AArch64] 1/7 Add support for ARMv8.1 Adv.SIMD instructions
* Backport of [AArch64] 2/7 Add sqrdmah, sqrdmsh instructions
* Backport of [AArch64] 3/7 Add builtins for ARMv8.1 Adv.SIMD instructions
* Backport of [AArch64] 4/7 Add ACLE feature macro for ARMv8.1
Adv.SIMD instructions
* Backport of [AArch64] 5/7 Dejagnu support for ARMv8.1 Adv.SIMD
* Backport of [AArch64] 6/7 Add NEON intrinsics vqrdmlah and vqrdmlsh
* Backport of [AArch64] 7/7 Add NEON intrinsics vqrdmlah_lane and vqrdmlsh_lane
* Backport of [AArch64] Documentation fix for -fpic
* Backport of [AArch64] fix 3/7 Add builtins for ARMv8.1 Adv.SIMD instructions
* Backport of [AArch64] Fix a few failures with LSE enabled
* Backport of [AArch64] Improve add immediate expansion
* Backport of [AArch64] Improve comparison with complex immediates
followed by branch/cset
* Backport of [AArch64] Rework ARMv8.1 command line options
* Backport of [AArch64] Update patterns to support FP zero
* Backport of [AArch64] Use aarch64_sync_memory_operand in
atomic_store<mode> pattern
* Backport of [AArch64] Use vector wide add for mixed-mode adds
* Backport of [Misc] Only restrict pure simplification in mult-extend
subst case, allow other substitutions
* Backport of [Testsuite] [AArch64] Skip big-endian as well for
gcc.target/aarch64/got_mem_hoist_1.c
* Backport of [Testsuite] Make stackalign test LTO proof
* Backport of [Testsuite] Testcase for PR rtl-optimization/68381
Feedback and Support
Subscribe to the important Linaro mailing lists and join our IRC
channels to stay on top of Linaro development.
** Linaro Toolchain Development "mailing list":
http://lists.linaro.org/mailman/listinfo/linaro-toolchain
** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@
* Bug reports should be filed in bugzilla against GCC product:
http://bugs.linaro.org/enter_bug.cgi?product=GCC
* Interested in commercial support? inquire at "Linaro support":
mailto:support@linaro.org
[1]. Stable source package releases are defined as releases where the
full Linaro Toolchain validation plan is executed.
[2]. Source package snapshots are defined when the compiler is only
put through unit-testing and full validation is not performed.
Folks,
I'd like to know the general opinion on this:
https://llvm.org/bugs/show_bug.cgi?id=23529
>From past experience, and my limited point of view, it seems that the
GCC community decided to change the ABI, plotted some runes, conjured
up a broken implementation (whose bugs people will exploit and GCC
will end up keeping them) and pushed distros to follow.
I don't know how much distros were involved in the original design.
Did they request the changes? Or was that an internal change? How do
you guys get to decide when to break the world?
I also don't know how will be your policy towards the bugs that people
started "using". Are you going to force them moving to a more sane
implementation (by issuing compiler/linker errors) or are you going to
support as legacy for the decades to come?
Is there a detailed document describing all the changes, and is the
GCC implementation following that to the letter, or are there still
bugs in the current version? I'm not talking about an email thread,
but an actual document on GCC's docs pages.
All I know is that people in the Clang community waited until GCC's
implementation was stable, but somehow Debian based distros started
moving as if there was something unholy about the previous ABI, and
we've been getting segmentation faults on Hello World!
I don't know much about the changes myself, nor I was involved in the
discussion, but this is now a major pain for release 3.8.0 and I
thought it would be better if I sent an email to Linaro folks and
members (which form most of the ARM GNU developers) instead of going
on the main lists.
That also gives me a bit more freedom to be more candid. I wouldn't
send those questions as they are to the GCC/binutils lists, or people
would kill me. I don't mean any of them as an offence, they are
genuine questions from someone that is not on top of that issue.
cheers,
--renato
Hi Linaro Toochain Group,
I have few questions on glibc+libm w.r.t aarch64.
If possible, please provide some insight, otherwise kindly redirect me to
the concerned person/forum.
1.It seems from the community patches that ARM/Linaro is optimizing glibc
functions such as memcpy/memmove, string for aarch64.
However, looks like some of these (e.g. memcpy/memmov) patches are still
not merged in glibc. Any comment on their availability in glibc?
e.g. https://www.sourceware.org/ml/libc-alpha/2015-12/msg00341.html
2. On the same note, is there any plan for optimizing/tuning libm functions
(e.g. trigonometric) for aarch64?
I could find any matching patches on review board. Please correct me if I
am wrong.
3. Looks like ARM have released an independent version of libm for certain
trigonometric functions.
https://github.com/ARM-software/optimized-routines.
Any plan of these optimization going in glibc's libm? Any comment on its
performance improvement over GNU libm ?
Thanks in advance for your time.
--
with regards,
Virendra Kumar Pathak
== Progress ==
- LTO and TCWG480 (6/10)
* Read and experimented with GCC's LTO codebase.
* Setup archlinux on chromebook and ran coremark with perf
* Read referenced publications
- PR66726 (2/10)
* Rebased the patch
* Regression tested on x86_64 and using Chritsope's setup
* getting ready to post upstream
- Misc (2/10)
* gcc/bug list
* abstract for connect presentation
* Meetings
== Plan ==
* LTO
* bugs
o Teaching activity (2/10)
== Progress ==
o Linaro GCC (4/10)
* Completed backports for 2016.01
* Merged FSF 5 branch into Linaro 5 one
* Delivered 2016.01 Snapshot
* Try to reproduce Linaro PR #1988 with 2016.01.
issue not reproducible
o GCC dev. (3/10)
* Fix armv8.1-a handling at configure time
patch committed upstream in trunk and backported in our branch.
* Investigate TCWG-128 (Thumb2 branch out of range with LTO)
o Misc (1/10)
* Various meetings
== Plan ==
o Look at diff between ABE branches in our validation context
o Continue on-going tasks
Port to microinstance - TCWG-432 [3/10]
* Fallout from attempts to fix race condition
* Various minor fixes - simplifications, better reporting
Backport benchmarking - TCWG-352 [1/10]
* Decoupled 'target triple' from 'toolchain' name
** Immediately, to let me benchmark with Juno-built native gcc
** But this has been causing minor pain for a while
Benchmarking infrastructure documentation - TCWG-496 [1/10]
* Finished drafts of LAVA wrapper and microinstance access docs
Unexpected 1/2 day off [1/10]
Misc [4/10]
* Unusual number of meetings
* Fiddling with my git workflow
* Some thinking about Benchmark-102 for Connect
* Figured out why our SPEC objects were disappearing
== This week ==
* Bugzilla 68543 - [AArch64] Implement overflow arithmetic standard
names (6/10)
- Re-implementing using sign/zero extends as this was not clear from
the documentation
* Bugzilla 69008 - gcc emits unneeded memory access when passing trivial
structs by value (1/10)
- Determined to be structure alignment issue
* Code review of patch posted for Bugzilla 68532 (1/10)
- Completed code review and successfully tested with my vaddw patches
* Bugzilla 67323 - Tested patch for TCWG-318 (non-unit stride loads) (1/10)
- Patch did not generated vld3 so the bug has been reopened
* TCWG-317 - No review feedback yet
* Misc (1/10)
== Next week ==
* Bugzilla 68543 - Complete re-implementation with zero/sign extends and
test
* Bugzilla 69008 - Determine where in compiler issue should be addressed
* USA Holiday (January 18th, MLK Day)
== Progress ==
* Support (5/10)
- Bug triage: reviewing the 300+ bugs on ARM
- closing fixed ones (+35)
- adding deps for meta bugs (kernel, android, ias, chromium) (~15)
- moving to ARM/AArch64 components, etc. (~30)
- Checking a few more kernel patches for Clang support with Arnd
* Plan (3/10)
- Still planning roadmap for 2016/2017
* Background (2/10)
- Code review, meetings, discussions, general support, etc.
# Progress #
* Estimate the effort of GDB kernel-awareness work. Give comments
on formal slides. [1/10]
* GDB inserts breakpoints on the wrong place if these files'
basename is the same. TCWG-491. At least, post a patch to avoid
GDB crash. Reproduced with a simpler case, open PR 19474. [3/10]
* Update document about input interrupt. [1/10]
Done. Patch is committed.
* TCWG-503, fix GDB test case by @progbits -> %progbits. Patch is
posted. [1/10]
* Clean up arm software single step code. [3/10]
In progress. Some patches are committed, but some are still in my
queue. The recent arm software single step change causes a
regression on stepping out of signal handler.
* Think about the GDB slides for Linaro Connect [1/10]
# Plan #
* Look into the arm software single step regression.
* Post the rest of patches for arm software single step clean up.
--
Yao
== Progress ==
* Validation
- a couple of fixes in the validation jobs
- looking at timeouts problems with buildfarm-master
* GCC
- TCWG-485/PR68620: sent patch for review
- TCWG-484/target attributes problems in the testsuite
Rebased, but need more pending updates from Christian
* Misc (conf calls, meetings, emails, ...)
== Next ==
* Validation: more debug. Hopefully start extending validation scope
* GCC:
- bug fixing
- check trunk regressions reported during the holidays
