Back full time
== Progress ==
* resumed 1:1 calls with Zhenqiang, Venkat, Charles.
* GCC trunk cross-validation (2/10):
- monitored results
- a few improvements/cleanups
* Neon-intrinsics tests (5/10)
- continuing conversion
- needs to add support AArch64 Neon overflow flag
* Misc (meetings, conf-call, ..) (3/10)
* Successfully tried OpenNX setup put in place by Maxim
(on office computer, despite firewall and no root access)
== Next ==
* GCC trunk cross-validation:
- monitor and report results
- use this system to pre-validate a patch from Kugan
- share scripts with Kugan
* Neon intrinsics tests:
- continue conversion
- hopefully push a preliminary version upstream
== Progress==
lowlevellock performance bugs - TCWG-435 [3/10]
* Trying to build/test aarch64 on a foundation model
cbuild benchmarking - TCWG-360 [4/10]
* Integrating Maxim's spec scripts into Kugan's benchmarking branch
* Began modifying the branch to use existing cbuild functions where possible
Meetings/mail/etc [3/10]
== Plan ==
Holiday next week (w/c 26th May)
This week:
* Try testing glibc on system qemu rather than foundation model
* Carry on with cbuild benchmarking
* If time, put together some more experimental memset implementations
== Progress ==
* GDB arm v8 record/replay
-- Bug fixing: Improve gdb.reverse testsuite results on armv8
[TCWG-451] [2/10]
-- core files issue submitted bfd patch upstream [TCWG-451]
-- Support for recording Data processing - Advanced SIMD and
Cryptographic [TCWG-405] [TCWG-407] [3/10]
-- Support for recording A64 Data processing - Floating point
instructions [TCWG-404] [TCWG-406] [2/10]
* Miscellaneous
-- UK visa application submission [3/10]
== Plan ==
* Continue work on issues related to GDB arm v8 record/replay
The Linaro Toolchain Working Group (TCWG) is pleased to announce the 2014.05
stable release of the Linaro GCC 4.9 source package.
Linaro GCC 4.9 2014.05 is the second Linaro GCC source package release in the
4.9 series. It is based on FSF GCC 4.9.1+svn210052 and includes performance
improvements and bug fixes.
With the imminent release of ARMv8 hardware and the recent release of the
GCC 4.9 compiler the Linaro TCWG will be focusing on stabilization and
performance of the compiler as the FSF GCC compiler approaches version 4.9.1.
The Linaro TCWG will provide monthly stable[1] source package releases until
FSF GCC 4.9.1 is released. At that point Linaro GCC 4.9 will merge in
FSF GCC 4.9.1 and, release Linaro GCC 4.9.1, and then return to a schedule of
stable quarterly releases and monthly engineering[2] releases.
Interesting changes in this GCC source package release include:
* Updates to GCC 4.9.1+svn210052
* Backport of the Ada AArch64 support
Feedback and Support
Subscribe to the important Linaro mailing lists and join our IRC channels to
stay on top of Linaro development.
** Linaro Toolchain Development "mailing list":
http://lists.linaro.org/mailman/listinfo/linaro-toolchain
** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@
* Bug reports should be filed in Launchpad against "Linaro GCC project":
http://bugs.launchpad.net/gcc-linaro/+filebug.
* Questions? "ask Linaro":
http://ask.linaro.org/.
* Interested in commercial support? inquire at "Linaro support":mailto:
support(a)linaro.org
[1] Stable source package releases are defined as releases where the full Linaro
Toolchain validation plan is executed.
[2] Engineering source package releases are defined as releases where the
compiler is only put through unit-testing and full validation is not
performed.
== Progress ==
* Reload - IRA bug fix (5/10)
- In thumb2 mode, we get a pattern "*ior_scc_scc" for the third
argument expression by the combiner pass.
- Expression Class:foo(x,0,((y==x)||(z==x))) x gets register r1 and second r2 .
- The class object this pointer is passed in r0. r7 is used for stack pointer.
- The pattern "*ior_scc_scc" demands more LO_REGISTERS. It needs 5
LO_registers for destination and 4 source operands. But we are left
with r3,r4,r5,r6 only.
- Such situation is handled for Thumb1 only using
TARGET_CLASS_LIKELY_SPILLED_P. Thumb2 should accept HI registers also.
- Changing the pattern to accept general registers for destination
operation is also not helping.
- Need to explore secondary reload macros.
* Misc
- AMD meetings and internal tasks (2/10)
- 1-1 meetings (Ryan, Christophe and Maxim) (1/10)
* Testing: Installed packages and ran GCC Linaro compiler 4.8
correctness tests on hardware. Completed running SPEC 2006 for -O3
-mcpu=cortex-a57 flag (2/10).
== Plan ==
* Continue bug fixing.
* LTO bootstrap failure
* Testing GCC Linaro compiler on hardware.
* New laptop install ubuntu, set up chroot and migrate to toolchain
64 environment.
* UK VISA processing.
== Progress ==
* TCWG-413 (8/10) sha1 performance
- Looked at IRA dumps and aarch64 target hooks.
- GCC now uses FP registers as register class and this results in lots
of fmovs for the test-case.
- Discussed in list and tried spill_class hook for aarch64. This helps
sha1.
- Regression tested the change.
- Ran Spec2000 with the changes and 168.wupwise, 187.facerec are failing.
- Investigation continues.
* TCWG-468 (1/10)
- Continuing with benchmarking.
* Set-up NX and started using it (1/10)
== Plan ==
* Benchmarking.
* Upstream zero/sign extension elimination activities.
* sha1 performance.
== Issue ==
* None.
== Progress ==
* Commit three patches to enhance shrink-wrap for loop. But community
reports an ICE in dwarf info with the patches. (TCWG-133, 5/10)
* Update/test shrink-wrap for apcs patch according to comments (TCWG-482, 2/10)
* Loop-invariant heuristic tuning (TCWG-763, 2/10).
* Investigate Linaro crosstool-ng gdb build fail for 2014.05 config.
But have not find an easy way to fix lsbcc build fail. (1/10).
== Plans ==
* Fix the ICE triggered by shrink-wrap changes.
* gdb build fail issue if Linaro still use crosstool-ng for release
* Continue loop-invariant heuristic tuning
== Planned leaves ==
* June 2.
== Week of May 12th ==
- Rolled out TCWG development environment. (TCWG-483, 4/10)
-- https://collaborate.linaro.org/display/TCWG/TCWG+Development+Environment
-- Demo'ed it both inside and outside TCWG.
-- Finished up configuration of environment and setup backups.
- STREAM performance regression (TCWG-388, 2/10)
-- Prepared first batch of patches for upstream submission
- Various discussions, including ... (4/10)
-- register allocation and reload with Venkat
-- register allocation with Kugan
-- benchmarking with Kugan
--
Maxim Kuvyrkov
www.linaro.org
== Week of May 5th ==
- Worked on standardized development environment (TCWG-483, 8/10)
-- Deployed it on toolchain64.lava and maximk.linaro.org.
-- Demoed and got early feedback from several people.
- Various discussions, including ... (2/10)
-- GCC debugging and var-tracking pass with Michael.
--
Maxim Kuvyrkov
www.linaro.org
== Progress ==
* Kernel (CARD-1246 5/10)
- Named register support in Clang
* http://reviews.llvm.org/D3797
* Toolchain (CARD-862 3/10)
- Testing libc++abi on ARM, now that it has EHABI
- Setting up Chromebook library buildbot (FAILED)
- One of the bots had a battery failure, needs to be replaced
- Which means we won't have the lib bot soon :(
* Background (2/10)
- Code review, meetings, discussions, etc.
== Plan ==
* Follow up named register patch upstream
* Help LLVMLinux with moving current code to conform to global named regs
* Help LLVMLinux with LAVA bots
* Replace the failing buildbot
* Set up a temporary (local) library buildbot on the spare Chromebook
* Try other hardware to replace all Chromebooks
== Progress ==
* Various patch review and followup (2/10)
* Helping diagnose an aarch64 linker crash in buildroot (1/10)
* Failed attempt to update kernel on Chromebook (1/10)
* Analyze and benchmark cortex-strings to find the oustanding work (1/10)
* Get docker setup with cgroups to measure memory usage (4/10, TCWG-441)
* Trying to get NX working on Fedora 20 (1/10)
== Issues ==
* None
== Plan ==
* Get postgresql and hopefully others working with new benchmark setup
* Figure out how to make NX work
--
Will Newton
Toolchain Working Group, Linaro
Hi All,
AAarch64 back-end defines GENERAL_REGS and CORE_REGS with the same set
of register. Is there any reason why we need this?
target hooks like aarch64_register_move_cost doesn’t handle CORE_REGS.
In addition, IRA cost calculation also has logics like make common class
biggest of best and alternate; this might get confused with this.
Attached RFC patch removes it. regression tested for
aarch64-none-linux-gnu on qemu-aarch64 with now new regression. Is this OK ?
Thanks,
Kugan
gcc/
2014-05-14 Kugan Vivekanandarajah <kuganv(a)linaro.org>
* config/aarch64/aarch64.c (aarch64_regno_regclass) : Change CORE_REGS
to GENERAL_REGS.
(aarch64_secondary_reload) : LikeWise.
(aarch64_class_max_nregs) : Remove CORE_REGS.
* config/aarch64/aarch64.h (enum reg_class) : Remove CORE_REGS.
(REG_CLASS_NAMES) : Likewise.
(REG_CLASS_CONTENTS) : LikeWise.
(INDEX_REG_CLASS) : Change CORE_REGS to GENERAL_REGS.
== Progress ==
* Reload - IRA bug fix (5/10)
- Expression foo(a,0,((b==a)||(c==a))) a gets register r1 and second
a gets register r6, but third a not able to reuse r6 or r1 and spill
failure.
- Debugging the IRA dumps and reload dumps
- Getting Maxim help
* TCWG-180 (3/10)
- GCC bootstrap fails with compare errors.
- comparing the dis assembly.
* Misc (2/10)
- AMD meetings
- 1-1 meetings
- looked at 1 x86 related bug
== Plan ==
* Continue bug fixing.
* LTO bootstrap failure
Short week, 2 days off (4/10)
== Issues ==
* None
== Progress ==
* CARD-1162 : Linaro GCC 4.9 (6/10)
- Prepared FSF 4.9 branch merge in Linaro one.
- Backported Zhenqiang upstream patches.
- Iterate with rob on various jenkins issues
- Looked at gerrit for the backport reviews
* Misc:
o Cbuildv1 baby-sitting
== Next ==
* Continue on Linaro GCC 4.9 release.
== Progress ==
* TCWG-413 (5/10)
- Rebuild FSF 4.8, Linaro 4.8 and Linaro 4.9 releases for aarch64 with
crosstool-ng (Kept all the dependencies same and used different gcc).
- Lost all the config for running benchmark on the test-machine and set
it up again.
- Re-ran spec2k benchmarking and results.
* TCWG-468 (5/10)
- Looked in detail IRA dumps and cost models.
- Also looked at IRA and LRA code to get better understanding of the
algorithms.
- Costs dumped seems odd and looking further.
== Plan ==
* Benchmarking.
* Upstream zero/sign extension elimination activities.
* sha1 performance.
== Progress ==
* GDB arm v8 record/replay: core files issue [TCWG-451] [6/10]
-- Add bfd support for missing aarch64 core file handlers.
-- Added regset caching functions for aarch64 linux gdb.
* GDB arm v8 record/replay: Support for recording A64 Data processing
- Floating point instructions [TCWG-404] [3/10]
* Miscellaneous [1/10]
-- Meetings
-- Browse through Linaro training resources.
-- UK visa documents preparation.
== Plan ==
* Continue work to support GDB arm v8 record/replay
-- Support for recording A64 Data processing - Floating point
instructions [TCWG-404]
-- Support for recording syscalls, signals etc [TCWG-409]
* UK visa application submission.
= Progress ==
* Continue improving LAVA support in DejaGnu. (TCWG 455 - 1/10)
* More work on regression test analysis and reporting. (TCWG 448 - 4/10)
- Did builds of 4.8, 4.9, and master to establish baseline test
results.
- Worked on test analysis script.
- Jenkins matrix builds & test runs are working, and copying results to
toolchain64.
* Meetings and Misc (5/10)
- Fixing various Cbuildv2 bugs found by yroux dealing with git.
- Fixed bug where the GDB build was polluting the destdir with
binutils.
- Installed OpenNX chroot on toolchain64 with maxim.
- Fixed disk on toolchain64 with maxim to access all 4TB. Use GPT...
- Added more config triplets to Jenkins, so now it builds everything
we support.
== Plan ==
* Install lava-tool and get it working on all the tcwgbuild* machines.
* Continue improving LAVA support in DejaGnu. (TCWG 455)
* More work on regression test analysis and reporting. (TCWG 448)
- Do diffs of new builds test runs from the baseline, not the previous
build.
* Try to look at the LLVM branch of Cbuildv2, do some testing of it.
== Issues ==
* Jenkins needs to be able to see LAVA slaves as online, but not
booted..
* The skiing is good, but the avalanche danger is high, so limits
accessibility.
* We need a backup plan for toolchain64.
* Google groups have problems, so had to setup test results list on
one of my servers instead. (ask me if you want to be on the list) The
new beta release of GNU Mailman looks very nice.
* The chromebooks in our build farm can't build GCC native.
- rob -
== Issue ==
* None.
== Progress ==
* Identify a build environment issue for linux64 gdb binaries "Symbol
format `elf32-littlearm' unknown".
* Send out shrink-wrap related patches from community review (TCWG-133, 2/10)
* Move-loop-invariant heuristic tuning (TCWG-469, 8/10).
- Update heuristic according to benchmark testing.
== Plan ==
* Update shrink-wrap patches according to comments.
* Continue on move-loop-invariants heuristic tune.
== Planned leaves ==
* June 2.
== Progress==
Holiday [2/10]
Fixing performance bugs in lowlevellock - TCWG-435 [4/10]
* Initial patch for lowlevellock.h largely done, awaiting an aarch64 test run
* About 1/2 of the lowlevellock.h's remain post-patch, need to ask
some questions about them
cortex-strings memset - TCWG-156 [1/10]
* Fixed an alternative implementation, a little more benchmarking investigation
cbuild benchmarking branch [1/10]
* Hunting for correct benchmark source, added a little more error checking
Meetings/mail/etc [2/10]
== Plan ==
More of the same -
* Post lowlevellock.h patch and ask some questions
* Finish exploring memset alternatives and work out how to benchmark them
* Carry on with cbuild benchmarking branch
Holiday 26th - 30th May
== Progress ==
* Kernel (CARD-1246 3/10)
- Committed Named Register LLVM change
- Working on the Clang part
- Helping LLVMLinux to set up bots/LAVA tests
* Tests/CBuild2 (CARD-716 2/10)
- Submitted CBuild2 LLVM patch, waiting for review
- Implemented sqrt to pacify GCC on sphereflake
* Background (3/10)
- Code review, meetings, discussions, etc.
* Bank Holiday Monday (2/10)
== Plan ==
* Continue named registers on Clang
* Continue LLVMLinux hardware test bot
* Run some benchmarks on AArch64
* Check CBuild2 progress, try builds live
== Progress ==
* Bank Holiday Monday (2/10)
* glibc patch review and followup (1/10)
* Started investigating malloc intensive applications (3/10, TCWG-440)
* Investigate a couple of linker issues (1/10)
* Figure out how to benchmark postgresql (3/10, TCWG-441)
== Issues ==
* None
== Plan ==
* Develop a good general way to measure memory usage of complex applications
--
Will Newton
Toolchain Working Group, Linaro
== Progress ==
Bank holiday [2/10]
Investigated using D01 board [1/10]
Retested and pinged division patch - TCWG-293 [2/10]
Added post-index addressing to NEON memory access for ARM -TCWG-430 [5/10]
* wrote patch
* makes useful improvement to libvpx performance
== Progress ==
Holiday [3/10]
Post-indexed addressing for NEON on Aarch64 - TCWG-430 [3/10]
* needs much more work than for ARM
Revisited apparent NEON scheduling problem in libvpx - TCWG-429 [2/10]
* it transpires that this was an incorrect analysis
* the assembler code didn't conform to the ABI
* upstream has now fixed this
Received review for division patch - TCWG-293 [2/10]
* needs a rewrite
(Resending to correct address)
== Progress==
TCWG-435 needless busy-wait in lowlevellock.c (0/10)
* Patches for lowlevellock.c sent to list
* Patch for lowlevellock.h still to do
TCWG-156 cortex-strings memset (5/10)
* Dug through a bunch of docs and fiddled with the source
Looking at the cbuild benchmarking branch (2/10)
* Some back and forth around getting access to lava lab
* Poked around the code, made some small improvements
== Misc ==
Meetings/mail/etc 3/10
== Plan ==
(Public) holiday on Monday
Put together lowlevellock.h patch
Do something more substantial with cbuild
Finish fiddling with the memset source
== Week of April 28th ==
- Made a prototype rootfs for benchmarking (CARD-1413, 2/10)
-- Got a tutorial from Fathi on how to build openembedded rootfs.
-- Wrote up notes at https://collaborate.linaro.org/display/TCWG/How+to+build+openembedded+rootf…
- More benchmarking setup (TCWG-413, 2/10)
- Various discussions (3/10)
-- 1-on-1 with Venkat (NX setup and GCC reload problem)
-- 1-on-1 with Kugan (benchmarking handover)
-- 1-on-1 with Michael (var-tracking investigation)
-- 1-on-1 with Rob (command-line access to LAVA and job submission)
- Made NX/schroot rootfs (3/10)
-- This can be deployed on Linaro [build] servers and provide standardized development environment for toolchain work.
-- More details to follow.
- Misc
-- Reported a kernel oops related to networking on vexpress64.
- Tyler Baker of the LAVA team deserve a special mention for answering all the questions about LAVA from the toolchain group!
--
Maxim Kuvyrkov
www.linaro.org
== Week of April 21st ==
- Setup SPEC benchmarking runs in LAVA environment (TCWG-413, 5/10).
-- Built SPEC cpu2000/cpu2006 tools for armv7a/armv8
-- Added SPEC CPU2006 support to spec2xxx-utils.
- Various discussions (1/10)
- Short week due to public holidays (4/10)
--
Maxim Kuvyrkov
www.linaro.org
== This week ==
- Investigated infinite loop bug [TCWG-290][6/10]
- Narrowed bug down to data flow analysis of micro operation in
variable tacking pass
- Created bugzilla report
- Still debugging to determine cause of infinite loop
== Next week ==
- Attend ARM Big Picture conference, May 5th-7th
- Resolve infinite loop bug
== Future ==
== Progress ==
* More work on regression test analysis and reporting. (TCWG 448 - 2/10)
* Started adding LAVA support to DejaGnu. (TCWG 455 - 4/10)
* Meetings and Misc (4/10)
- Fixed various bit-rot bugs in the cbuildv2 testsuite.
- Figured out how to add SSH keys to our launchpad account.
== Plan ==
* Continue improving LAVA support in DejaGnu. (TCWG 455)
* More work on regression test analysis and reporting. (TCWG 448)
== Progress ==
* GDB reverse debugging on aarch64
-- Further progress on decoding of aarch64 load store instructions.
[TCWG-401] [1/10]
* Investigated and progressed towards fix for GDB unable to read core files
[TCWG-451] [6/10]
* Public Holiday on 1st May [2/10]
* Miscellaneous [1/10]
-- Meetings
-- UK visa documents attestation
-- LCU14 registration and travel booking
== Plan ==
* GDB unable to read core files [TCWG-451]
-- Fix aarch64 linux regset functions
-- Add support for writing aarch64 regset in aarch64 core file.
* Miscellaneous
-- UK visa application
-- LCU14 finalize bookings.
== Progress ==
* TCWG-447 (5/10)
* Re-spin few versions of the patches and posted after testing based
on reviews.
* http://gcc.gnu.org/ml/gcc-patches/2014-04/msg01743.html
* http://gcc.gnu.org/ml/gcc-patches/2014-04/msg01744.html
* TCWG-413 Spec2006 (5/10)
* Updated the scripts to deploy libraries and to run cross spec
benchmarking with them.
* Experimented with open embedded image generation for benchmarking-
still finding some issues even with a trusty chroot.
* Started benchmarking and variance analysis.
== Plan ==
* Benchmarking.
* Upstream zero/sign extension elimination activities.
* Start with literal pool merging.
Very short week (3 half days)
== Progress ==
* GCC trunk cross-validation (2/10):
- monitored results, and reported some regressions/new fails
- moved away from Jenkins
- as commit rate has decreased, there is no backlog in validations
* Neon-intrinsics test (1/10):
- Continuing conversion for inclusion in the GCC testsuite.
- Preparing an additional Makefile, simpler than the current one,
to help using the testsuite for various GCC variants until
conversion is complete.
== Next ==
* Continue to closely monitor GCC trunk validations
* Neon intrinsics tests
* Off Thursday/Friday
Short week, Labor day (2/10)
== Issues ==
* None
== Progress ==
* Launchpad bugs: (4/10)
o LP #1307197 : gcc-4.9 miscompiles linux kernel zlib for armv3
- This an LRA issue for architectures < armv4 withi movhi
- Investigation ongoing
o LP #1169164 : including signal.h exposes various PSR_MODE #defines
- The proposed patch fix the issue
- Still need some validation before upstream submission
* Test new backport workflow and Cbuild2 (2/10)
- Some troubles to access the build farm.
* Misc:
o Cbuildv1 baby-sitting (1/10)
o Various meetings (1/10).
== Next ==
- Two days off
- FSF branch merge + backports
== Issues ==
* None
== Progress ==
* May 1-2: Laybor day holiday
* Commit fcsel support patch for aarch64 @r209889.
* Tuning move-loop-invariants heuristics for -fira-loop-pressure:
- Record register pressure for each invariant other than a max for all.
- Take register pressure into account when selecting the best candidate.
== Plan ==
* Tuning move-loop-invariants heuristics
* Ping pending patches.
== Planned leaves ==
* June 2.
* -fno-sched-interblock
* loop-inv
> Hello,
> I have a problem building gcc-linaro-arm-linux-gnueabihf
> toolchain for my x86_64 system. I download crosstool-ng (v1.13) and
> toolchain source code (4.8-2014.03) from
> http://releases.linaro.org/14.03/components/toolchain/binaries. I use
> the example configuration linaro-arm-linux-gnueabihf (obtained from
> ct-ng list-samples) and modify some entries using menuconfig option,
> like the local tarballs directory (pointing to downloaded toolchains
> source code directory) and the prefix directory (custom directory output).
>
> This is the problem during the execution of "ct-ng build" command:
>
> =================================================================
>
> [INFO ] Installing final compiler
>
> [EXTRA] Configuring final compiler
>
> [EXTRA] Building final compiler
>
> [EXTRA] AFMOYA: EMPIEZA A EJECUTARSE make jobsflags all
>
> [EXTRA] -j5
>
> [EXTRA] /home/afmoya/Descargas/build/.build/arm-linux-gnueabihf/build/build-cc
>
> [ERROR] configure: error: Link tests are not allowed after GCC_NO_EXECUTABLES.
>
> [ERROR] make[2]: *** [configure-zlib] Error 1
>
> [ERROR] make[1]: *** [all] Error 2
>
> [ERROR]
>
> [ERROR] >>
>
> [ERROR] >> Error happened in: main[scripts/crosstool-NG.sh]
>
> [ERROR] >>
>
> [ERROR] >> For more info on this error, look at the file: 'build.log'
>
> [ERROR] >> There is a list of known issues, some with workarounds, in:
>
> [ERROR] >> '/opt/cross-linaro/share/doc/ct-ng-linaro-1.13.1-4.8-2014.03/B - Known issues.txt'
>
> [ERROR]
>
> [ERROR] Build failed in step 'Extracting and patching toolchain components'
>
> [ERROR]
>
> [ERROR] (elapsed: 11:18.57)
>
> make: *** [build] Error 2
>
>
> Highlighted in green some entries added for me in attemp to understand
> the execution secuence.
>
> The error is triggered in the "configure-zlib" target of
> "${CT_TOP_DIR}/.build/arm-linux-gnueabihf/build/build-cc/Makefile". The
> "configure.log" of the
> "${CT_TOP_DIR}/.build/arm-linux-gnueabihf/build/build-cc/zlib/"
> directory shows some errors (I don't know if the are significants):
>
> LINE 83: Thread model: posix
>
> LINE 84: gcc version 4.7.2 (Debian 4.7.2-5)
>
> LINE 85: configure:3234: $? = 0
>
> LINE 86: configure:3223: x86_64-build_unknown-linux-gnu-gcc -V >&5
>
> LINE 87: gcc: error: unrecognized command line option '-V'
>
> LINE 88: gcc: fatal error: no input files
>
> LINE 89: compilation terminated.
>
> LINE 90: configure:3234: $? = 4
>
> LINE 91: configure:3223: x86_64-build_unknown-linux-gnu-gcc -qversion >&5
>
> LINE 92: gcc: error: unrecognized command line option '-qversion'
>
> LINE 93: gcc: fatal error: no input files
>
> LINE 94: compilation terminated.
>
> ...
>
> LINE 188: configure:6661: x86_64-build_unknown-linux-gnu-gcc -E conftest.c
>
> LINE 189: conftest.c:11:28: fatal error: ac_nonexistent.h: No such file or directory
>
> LINE 190: compilation terminated.
>
> ...
>
> LINE 207: configure:6720: x86_64-build_unknown-linux-gnu-gcc -E conftest.c
>
> LINE 208: conftest.c:11:28: fatal error: ac_nonexistent.h: No such file or directory
>
> LINE 209: compilation terminated.
>
> ...
>
> LINE 318: configure:10852: x86_64-build_unknown-linux-gnu-gcc -E conftest.c
>
> LINE 319: conftest.c:23:28: fatal error: ac_nonexistent.h: No such file or directory
>
> LINE 320: compilation terminated.
>
> Some idea of what's the problem?
>
> This is my system info:
> Linux afmoya-pc 3.2.0-4-amd64 #1 SMP Debian 3.2.57-3 x86_64 GNU/Linux
>
> and some tools version installed in my system:
> gcc (Debian 4.7.2-5) 4.7.2
> GNU Make 3.81
> GNU Awk 4.0.1
> ...
>
> Best regards:
> Alexis Fajardo Moya.
I have removed the "zlib" folder from "gcc-linaro-4.8-2014.03.tar.xz" tarball, the compiler is also using zlib-1.2.5 statically linked, and thats permit compile the Linaro toolchain.
Best regards
Lic. Reinier Millo Sánchez
Centro de Estudios de Informática
Universidad Central "Marta Abreu" de Las Villas
-----
"...hay locuras que son la locura
personales locuras de dos...
hay locuras sin nombre
sin fecha sin cura
que no vale la pena curar...
que una de ellas será mi morir."
Lic. Reinier Millo Sánchez
Centro de Estudios de Informática
Universidad Central "Marta Abreu" de Las Villas
Hello,
I have a problem building gcc-linaro-arm-linux-gnueabihf
toolchain for my x86_64 system. I download crosstool-ng (v1.13) and
toolchain source code (4.8-2014.03) from
http://releases.linaro.org/14.03/components/toolchain/binaries. I use
the example configuration linaro-arm-linux-gnueabihf (obtained from
ct-ng list-samples) and modify some entries using menuconfig option,
like the local tarballs directory (pointing to downloaded toolchains
source code directory) and the prefix directory (custom directory output).
This is the problem during the execution of "ct-ng build" command:
=================================================================
[INFO ] Installing final compiler
[EXTRA] Configuring final compiler
[EXTRA] Building final compiler
[EXTRA] AFMOYA: EMPIEZA A EJECUTARSE make jobsflags all
[EXTRA] -j5
[EXTRA] /home/afmoya/Descargas/build/.build/arm-linux-gnueabihf/build/build-cc
[ERROR] configure: error: Link tests are not allowed after GCC_NO_EXECUTABLES.
[ERROR] make[2]: *** [configure-zlib] Error 1
[ERROR] make[1]: *** [all] Error 2
[ERROR]
[ERROR] >>
[ERROR] >> Error happened in: main[scripts/crosstool-NG.sh]
[ERROR] >>
[ERROR] >> For more info on this error, look at the file: 'build.log'
[ERROR] >> There is a list of known issues, some with workarounds, in:
[ERROR] >> '/opt/cross-linaro/share/doc/ct-ng-linaro-1.13.1-4.8-2014.03/B - Known issues.txt'
[ERROR]
[ERROR] Build failed in step 'Extracting and patching toolchain components'
[ERROR]
[ERROR] (elapsed: 11:18.57)
make: *** [build] Error 2
Highlighted in green some entries added for me in attemp to understand
the execution secuence.
The error is triggered in the "configure-zlib" target of
"${CT_TOP_DIR}/.build/arm-linux-gnueabihf/build/build-cc/Makefile". The
"configure.log" of the
"${CT_TOP_DIR}/.build/arm-linux-gnueabihf/build/build-cc/zlib/"
directory shows some errors (I don't know if the are significants):
LINE 83: Thread model: posix
LINE 84: gcc version 4.7.2 (Debian 4.7.2-5)
LINE 85: configure:3234: $? = 0
LINE 86: configure:3223: x86_64-build_unknown-linux-gnu-gcc -V >&5
LINE 87: gcc: error: unrecognized command line option '-V'
LINE 88: gcc: fatal error: no input files
LINE 89: compilation terminated.
LINE 90: configure:3234: $? = 4
LINE 91: configure:3223: x86_64-build_unknown-linux-gnu-gcc -qversion >&5
LINE 92: gcc: error: unrecognized command line option '-qversion'
LINE 93: gcc: fatal error: no input files
LINE 94: compilation terminated.
...
LINE 188: configure:6661: x86_64-build_unknown-linux-gnu-gcc -E conftest.c
LINE 189: conftest.c:11:28: fatal error: ac_nonexistent.h: No such file or directory
LINE 190: compilation terminated.
...
LINE 207: configure:6720: x86_64-build_unknown-linux-gnu-gcc -E conftest.c
LINE 208: conftest.c:11:28: fatal error: ac_nonexistent.h: No such file or directory
LINE 209: compilation terminated.
...
LINE 318: configure:10852: x86_64-build_unknown-linux-gnu-gcc -E conftest.c
LINE 319: conftest.c:23:28: fatal error: ac_nonexistent.h: No such file or directory
LINE 320: compilation terminated.
Some idea of what's the problem?
This is my system info:
Linux afmoya-pc 3.2.0-4-amd64 #1 SMP Debian 3.2.57-3 x86_64 GNU/Linux
and some tools version installed in my system:
gcc (Debian 4.7.2-5) 4.7.2
GNU Make 3.81
GNU Awk 4.0.1
...
Best regards:
Alexis Fajardo Moya.
== Progress ==
* Prototype scripting for macro-benchmarks for malloc (4/10, TCWG-441)
* glibc single thread optimization work (3/10, TCWG-436)
* Built releases of eglibc, gdb and binutils (2/10)
* glibc patch review and followup (1/10)
* Misc admin (expenses, LCU travel)
== Issues ==
* None
== Plan ==
* Various bits of patch followup
* More malloc macro-benchmark work
* See how single thread optimization discussion goes
* glibc benchmark graphing?
--
Will Newton
Toolchain Working Group, Linaro
== Progress ==
* Named Register (CARD-1246 2/10)
- Changing type of intrinsics, rebasing patch
* Build & Benchmark (CARD-716 6/10)
- Adding Clang+LLVM builds to CBuild2
- Re-setting APM's testing environment after replacement
* Background (2/10)
- Code review, etc.
- EuroLLVM 2014 outcome analysis, plans for 2015
== Plan ==
* Get Clang+LLVM in CBuild2
* Get Named registers in, then try Clang's parser
* Try SPEC on APM
hi,
For building arm64 kernel, I tried all toolchain released from
http://releases.linaro.org/latest/components/toolchain/binaries/
But it complained about some instructions bad:
/home/work/linux/arch/arm64/include/asm/irqflags.h: Assembler
messages:
/home/work/linux/arch/arm64/include/asm/irqflags.h:49: Error: no
such instruction: `msr daifset,'
/home/work/linux/arch/arm64/include/asm/irqflags.h:68: Error: no
such instruction: `mrs %rax,daif//arch_local_save_flags'
/home/work/linux/arch/arm64/include/asm/irqflags.h:49: Error: no
such instruction: `msr daifset,'
/home/work/linux/arch/arm64/include/asm/irqflags.h:68: Error: no
such instruction: `mrs %rax,daif//arch_local_save_flags'
/home/work/linux/arch/arm64/include/asm/irqflags.h:40: Error: no
such instruction: `msr daifclr,'
/home/work/linux/arch/arm64/include/asm/irqflags.h:68: Error: no
such instruction: `mrs %rax,daif//arch_local_save_flags'
/home/work/linux/arch/arm64/include/asm/irqflags.h:40: Error: no
such instruction: `msr daifclr,'
Could anyone tell how to solve it? thanks!
== Progress==
TCWG-435 needless busy-wait in lowlevellock.c (3/10)
* Patches ready, testing a bit slow & fiddly
TCWG-156 cortex-strings memset (3/10)
* Worried about noisy benchmarks
* Learned to use Lava
* Found some helpful internal docs
* Managed to tweak the code slightly
== Misc ==
Meetings/mail/etc 2/10
(Public) holiday 2/10
== Plan ==
Stop worrying and follow the general curve of the noisy benchmarks
(But also try to convince Maxim's spec scripts + lava to generate some
less noisy results)
Another public holiday next Monday
== Progress ==
* GDB reverse debugging on aarch64
-- Complete decoding of aarch64 data processing immediate instructions.
[TCWG-399] [1/10]
-- Complete decoding of aarch64 data processing register instructions.
[TCWG-402] [1/10]
-- Completed decoding of aarch64 exception and system instructions.
[TCWG-400] [2/10]
-- Further progress on decoding of aarch64 load store instructions.
[TCWG-401] [2/10]
-- Started implementation of aarch64 syscall record/replay. [TCWG-409]
[2/10]
* Sick Day Off on Monday [2/10]
== Plan ==
* GDB reverse debugging on aarch64
-- Further progress on decoding of aarch64 load store instructions.
[TCWG-401]
-- Further progress on aarch64 syscall record/replay. [TCWG-409]
* Public Holiday on 1st May.
Short week, Easter Monday + child care (3/10)
== Issues ==
* Toolchain64 disk still full every 2 days
== Progress ==
* Linaro GCC 4.9 2014.04 release (3/10)
- Branch merge with FSF 4.9.1
- Release tarball available on releases.linaro.org
- Announcement will follow
* Launchpad bugs: (2/10)
o LP #1169164 : including signal.h exposes various PSR_MODE #defines
- Discussed and implemented a fix
- Validation on-going
* Misc:
o Cbuildv1 baby-sitting (1/10)
o Various meetings (1/10).
o Resolved cards :
- TCWG-343. Make LRA the default for the ARM backend
- TCWG-422. LP-bug 1296676 : ICE in assign_by_spills building linux
btrfs module
== Next ==
- One day off (Labor day)
- Submit patch for LP #1169164
- TCWG-345. Analyse performance of LRA for ARM
== Progress ==
PGO - AArch64 (TCWG-179) (4/10)
* Completed SPEC2006 runs ( -O3 + PGO) in chroot + qemu-arm64-saucy
with Linaro branch(4.9).
* Perlbench train run failed, issue with qemu.
* DealII train runs failed due to system libstdc++.so.6 not compatible
with GCC 4.9.
Changing the LD_LIBRARY_PATH to point to the libstdc++.so.6 that
gets built along with GCC 4.9 solves the problem.
* CPU2000 runs are completed my maxim so functional testing of PGO for
spec benchmarks completed.
* Wating on Arm64 hardware to benchmark SPEC2000 and SPEC2006 and
compare against the PGO runs for x86.
Misc (2/10)
* Setup arm64-trusty chroot and built GCC 4.9 compiler
* Maxim 1-1 discussions and set up opennx client
* Checked libssp patch upstream status
* Read about gcc debug counters.
* Upgrade laptop to Ubuntu 14.04 LTS
Short week (22nd and 23rd leave (4/10))
== Plan ==
* Bug fixing.
== Issues==
* Waiting on hardware to Benchmark SPEC2006 PGO runs in hardware.
== Issue ==
* None
== Progress ==
* More tests on shrink-wrap changes (TCWG-133, 6/10).
- Cortex-m3 tests exposes a data flow issue: New BB created after
dfinit does not have correct df_lr info.
- Collect Spec2k benchmarks on X86-64 and ARM.
* Linaro 4.9 binaries release (2/10).
- Update Linaro crosstool-ng config and samples to support 4.9.
- Disable parallel build for gcc manual (pdf & html).
- Prebuild binaries for aarch64:
http://cbuild.validation.linaro.org/binaries/4.9-prerelease-2014.04
* Ping aarch64 fcel patch. But still no comments.
* Fix a trunk build fail issue @r209556.
* One day off (2/10).
== Plans ==
* Send the shrink-wrap related patches for review.
* PING the pending patches.
* Investigate move-loop-invariants heuristics.
== Planed leaves ==
* May 1-3: Labour day holiday.
== Progress ==
* Got Jenkins working with matrix builds so we can utilize all LAVA
slaves. (TCWG 1387 - 3/10)
* Write script to take a list of revisions and then build and test
them all and diff the results. (TCWG 448 - 4/10)
* More experimenting with Kugan's benchmarking branch. (1/10)
* Meetings and Misc (2/10)
== Plan ==
* More work on matrix builds. (TCWG 1387)
* More work on regression test analysis and reporting. (TCWG 448)
== Progress ==
* Short week (21st and 25th are public holidays) (4/10)
* TCWG-447 (5/10)
* Implemented and tested fenv target hooks, necessary built-ins and md
patterns
* Posted RFC patches for review for both arm and aarch64
* http://gcc.gnu.org/ml/gcc-patches/2014-04/msg01743.html
* http://gcc.gnu.org/ml/gcc-patches/2014-04/msg01744.html
* TCWG-413 Spec2006 (1/10)
* Finished the set-up
* On hold for now
== Plan ==
* upstream zero/sign extension elimination activities
* start with literal pool merging
== Progress ==
* Holidays (3 days)
- Clearing emails/tasks backlog
- Some post-trip illness
* AArch64 vs. ARM64
- Comparing performance of both back-ends
* Named Register
- Re-implementing after code review
- http://reviews.llvm.org/D3261
* Time
- CARD-1246 4/10
- Others 6/10
== Plan ==
* Finish named register in LLVM, check Clang
* Continue testing and benchmarking ARM64 back-end
* Have a try at CBuildv2
== Progress ==
* Back to work part-time (50%) for the next 3 weeks
* Easter Monday (1/5)
* (No Jira card - 2/5)
Analyzed at GCC trunk validations and reported some regressions.
The current commit rate is very high since stage1, and our compute
farm isn't fast enough. Should be OK after the week-end.
Modified my scripts so that I move these validations out of Jenkins.
* (No Jira card - 2/5)
Continued converting Neon intrinsics tests for inclusion in GCC testsuite.
To make the review easier, I now believe that it would be better that
I convert most of the testsuite first, and rework the patches order.
* Meetings and conf calls(1/5)
== Next ==
* Continue to closely monitor GCC trunk validations
* Neon intrinsics tests
* Off Thursday/Friday next week