On 29 November 2010 00:18, Michael Hope
<michael.hope@linaro.org> wrote:
To add to the mix:
Some ideas that are logged as blueprints:
Using ARMv5 saturated instructions
(https://blueprints.launchpad.net/gcc-linaro/+spec/armv5-saturated-ops)
Using ARMv6 SIMD instructions
(https://blueprints.launchpad.net/gcc-linaro/+spec/armv6-simd)
Those are quite nice instructions; certainly they seem useful for string ops of various types
if misued creatively.
Using ARMv7 unaligned accesses
(https://blueprints.launchpad.net/gcc-linaro/+spec/unaligned-accesses)
Changing the built-in memcpy to use unaligned
(https://blueprints.launchpad.net/gcc-linaro/+spec/unaligned-memcpy)
The interesting challenge here is figuring out how expensive unaligned's are and if the cost trade offs are the same on different chips.
The following areas have been suggested. I don't know if they're still valid:
Register allocator: The register allocator is designed around the
needs of architectures with a low register count and restrictive
register classes. The ARM architecture has many general purpose
registers. Different assumptions may give better code.
Conditional instructions: The ARM and, to a lesser extent, Thumb-2
ISAs allow conditional execution of instructions. This can be used in
many situations to eliminate an expensive branch. The middle end
expands and transforms branches. The ARM backend tries to recombine
the RTL back into conditional instructions, but often can't due to the
middle end transforms.
GCC is quite creative in avoiding branches by doing lots of masking and logic;
it'll be interesting how much this has to gain.
Dave