Index: config/arm/neon.md
===================================================================
--- config/arm/neon.md  (revision 168987)
+++ config/arm/neon.md  (working copy)
@@ -143,7 +143,11 @@
    (UNSPEC_VZIP2               204)
    (UNSPEC_MISALIGNED_ACCESS   205)
    (UNSPEC_VCLE                        206)
-   (UNSPEC_VCLT                        207)])
+   (UNSPEC_VCLT                        207)
+   (UNSPEC_EXTEVEN              208)
+   (UNSPEC_EXTODD               209)
+   (UNSPEC_INTERHI              210)
+   (UNSPEC_INTERLO              211)])

 ;; Attribute used to permit string comparisons against <VQH_mnem> in
@@ -5469,3 +5473,76 @@
   emit_insn (gen_neon_vec_pack_trunc_<V_double> (operands[0], tempreg));
   DONE;
 })
+
+(define_expand "vec_extract_even<mode>"
+ [(set (match_operand:VDQW 0 "register_operand" "")
+        (unspec:VDQW [(match_operand:VDQW 1 "register_operand" "")
+                      (match_operand:VDQW 2 "register_operand" "")]
+                      UNSPEC_EXTEVEN))]
+ "TARGET_NEON"
+{
+  rtx tmp = gen_reg_rtx (<MODE>mode);
+
+  if (BYTES_BIG_ENDIAN)
+    emit_insn (gen_neon_vuzp<mode>_internal (tmp, operands[1], operands[0],
+                                             operands[2]));
+  else
+    emit_insn (gen_neon_vuzp<mode>_internal (operands[0], operands[1], tmp,
+                                             operands[2]));
+  DONE;
+})
+
+(define_expand "vec_extract_odd<mode>"
+ [(set (match_operand:VDQW 0 "register_operand" "")
+        (unspec:VDQW [(match_operand:VDQW 1 "register_operand" "")
+                      (match_operand:VDQW 2 "register_operand" "")]
+                      UNSPEC_EXTODD))]
+ "TARGET_NEON"
+{
+  rtx tmp = gen_reg_rtx (<MODE>mode);
+
+  if (BYTES_BIG_ENDIAN)
+    emit_insn (gen_neon_vuzp<mode>_internal (operands[0], operands[1], tmp,
+                                             operands[2]));
+  else
+    emit_insn (gen_neon_vuzp<mode>_internal (tmp, operands[1], operands[0],
+                                             operands[2]));
+  DONE;
+})
+
+(define_expand "vec_interleave_high<mode>"
+ [(set (match_operand:VDQW 0 "register_operand" "")
+        (unspec:VDQW [(match_operand:VDQW 1 "register_operand" "")
+                      (match_operand:VDQW 2 "register_operand" "")]
+                      UNSPEC_INTERHI))]
+ "TARGET_NEON"
+{
+  rtx tmp = gen_reg_rtx (<MODE>mode);
+
+  if (BYTES_BIG_ENDIAN)
+    emit_insn (gen_neon_vzip<mode>_internal (operands[0], operands[1], tmp,
+                                             operands[2]));
+  else
+    emit_insn (gen_neon_vzip<mode>_internal (tmp, operands[1], operands[0],
+                                             operands[2]));
+  DONE;
+})
+
+(define_expand "vec_interleave_low<mode>"
+ [(set (match_operand:VDQW 0 "register_operand" "")
+        (unspec:VDQW [(match_operand:VDQW 1 "register_operand" "")
+                      (match_operand:VDQW 2 "register_operand" "")]
+                      UNSPEC_INTERLO))]
+ "TARGET_NEON"
+{
+  rtx tmp = gen_reg_rtx (<MODE>mode);
+
+  if (BYTES_BIG_ENDIAN)
+    emit_insn (gen_neon_vzip<mode>_internal (tmp, operands[1], operands[0],
+                                             operands[2]));
+  else
+    emit_insn (gen_neon_vzip<mode>_internal (operands[0], operands[1], tmp,
+                                             operands[2]));
+  DONE;
+})
+