Hi Heyi,
The write to GICC_EOIR clears corresponding bit in GICD_ISACTIVER0 and the following update of CNTP_CVAL will clear bit in CICD_ISPENDR0 register, so there
shouldn’t be any issue with this order.
By the way call to ArmGenericTimerEnableTimer() is obsolete because timer is enabled and doesn’t get disabled in TimerInterruptHandler().
From: Linaro-uefi [mailto:linaro-uefi-bounces@lists.linaro.org]
On Behalf Of Heyi Guo
Sent: 02 August 2016 02:28
To: Ard Biesheuvel
Cc: Linaro UEFI Mailman List
Subject: Re: [Linaro-uefi] [linaro-uefi] Two write to EOIR in a single interrupt
Hi Leif and Ard,
There might be another issue in timer interrupt handler. Timer interrupt seems to be level triggered, so is it OK to write EOIR before clearing the interrupt source, i.e. updating compare value register?
Heyi
On 29 July 2016 at 15:11, Ard Biesheuvel <ard.biesheuvel@linaro.org> wrote:
On 29 July 2016 at 09:09, Ard Biesheuvel <ard.biesheuvel@linaro.org> wrote:
> On 29 July 2016 at 03:23, Heyi Guo <heyi.guo@linaro.org> wrote:
>> In timer interrupt handler, we can see the comment that "Signal end of
>> interrupt early to help avoid losing subsequent ticks from long duration
>> handlers".
>>
>> So, if we want to fix this, shall we remove EOIR writing in GIC IRQ handler
>> (move it to unregistered interrupt branch only) and keep the one in timer
>> interrupt handler, and declare that EOIR should be taken care by each
>> interrupt handler itself, rather than by GIC driver?
>>
>
> Can we use priority drop instead?
Reply to self: probably not. I suppose the whole point is to allow
nested timer interrupts.
In any case, we need to get rid of the double EOIR write. I would
prefer not to change the contract with existing interrupt handlers,
though.