Jan
W dniu środa, 4 maja 2016 Ard Biesheuvel <ard.biesheuvel@linaro.org> napisał(a):

On 4 May 2016 at 18:52, Ard Biesheuvel <ard.biesheuvel@linaro.org> wrote:
> On 4 May 2016 at 18:42, Jan Dąbroś <jsd@semihalf.com> wrote:
>> Hi Ard,
>>
>> I am working on support for AHCI controller for my ARMv8 platform and
>> I decide to use PciEmulation approach. I was able to run XHCI via
>> PciEmulation without problems, but unfortunately with AHCI it isn't
>> working.
>>
>> Controller is compatible with AHCI specification. It isn't
>> dma-coherent and I think that problem lies here.
>> Initialization timeouts in below part of code:
>>
>> //
>> // Enable FIS Receive DMA engine for the first D2H FIS.
>> //
>> Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH +
>> EFI_AHCI_PORT_CMD;
>> AhciOrReg (PciIo, Offset, EFI_AHCI_PORT_CMD_FRE);
>> Status = AhciWaitMmioSet (
>> PciIo,
>> Offset,
>> EFI_AHCI_PORT_CMD_FR,
>> EFI_AHCI_PORT_CMD_FR,
>> EFI_AHCI_PORT_CMD_FR_CLEAR_TIMEOUT
>> );
>> if (EFI_ERROR (Status)) {
>> continue;
>> }
>>
>> Where do you think may be problem?
>> Do you have any tips what should I try to do?
>>
>
> Are you using DmaLib? If you are, it is simply a matter of using
> ArmDmaLib, which uses uncached memory and/or explicit cache
> maintenance to perform non-coherent DMA. Basically, you need to
> implement the Allocate, free, map and unmap functions in the PCI I/O
> protocol using DmaLib methods, so you can use either coherent or
> non-coherent DMA depending on which version of the library you bind
> your driver to.

Also, make sure you set any I/O align fields in the protocol
structures according to the CWG (max cacheline size) of your SoC. This
will result in fewer cases where ArmDmaLib needs to use bounce
buffering for streaming DMA.