What do these hardcoded array sizes signify?> +
> +#ifndef __MVHWDESCLIB_H__
> +#define __MVHWDESCLIB_H__
> +
> +#include <Library/NonDiscoverableDeviceRegistrat ionLib.h>
> +
> +//
> +// Platform storage description
> +//
> +typedef struct {
> + // XHCI
> + UINT8 XhciDevCount;
> + UINTN XhciBaseAddresses[4];
> + UINTN XhciMemSize[4];
> + NON_DISCOVERABLE_DEVICE_DMA_TYPE XhciDmaType[4];
> + // AHCI
> + UINT8 AhciDevCount;
> + UINTN AhciBaseAddresses[4];
> + UINTN AhciMemSize[4];
> + NON_DISCOVERABLE_DEVICE_DMA_TYPE AhciDmaType[4];
> + // SDHCI
> + UINT8 SdhciDevCount;
> + UINTN SdhciBaseAddresses[4];
> + UINTN SdhciMemSize[4];
> + NON_DISCOVERABLE_DEVICE_DMA_TYPE SdhciDmaType[4];
> +} MVHW_STORAGE_DESC;
What makes 4 guaranteed future-proof?
> +
> +#define DECLARE_A7K8K_STORAGE_TEMPLATE \
Is XHCI "storage"?
> +STATIC MVHW_STORAGE_DESC mA7k8kStorageDescTemplate = {\
> + 4, /* XHCI */\
> + { 0xF2500000, 0xF2510000, 0xF4500000, 0xF4510000 },\
These addresses would be a lot nicer as #defines.
> + { SIZE_16KB, SIZE_16KB, SIZE_16KB, SIZE_16KB },\
> + { NonDiscoverableDeviceDmaTypeCoherent, NonDiscoverableDeviceDmaTypeCo Insert sorted, please.herent,\
> + NonDiscoverableDeviceDmaTypeCoherent, NonDiscoverableDeviceDmaTypeCo herent },\
> + 2, /* AHCI */\
> + { 0xF2540000, 0xF4540000 },\
> + { SIZE_8KB, SIZE_8KB },\
> + { NonDiscoverableDeviceDmaTypeCoherent, NonDiscoverableDeviceDmaTypeCo herent },\
> + 2, /* SDHCI */\
> + { 0xF06E0000, 0xF2780000 },\
> + { SIZE_1KB, SIZE_1KB },\
> + { NonDiscoverableDeviceDmaTypeCoherent, NonDiscoverableDeviceDmaTypeCo herent }\
> +}
> +
> +#endif /* __MVHWDESCLIB_H__ */
> diff --git a/Platforms/Marvell/PciEmulation/PciEmulation.c b/Platforms/Marvell/ PciEmulation/PciEmulation.c
> index 491b886..ffefffb 100644
> --- a/Platforms/Marvell/PciEmulation/PciEmulation.c
> +++ b/Platforms/Marvell/PciEmulation/PciEmulation.c
> @@ -34,47 +34,13 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
>
> #include <PiDxe.h>
>
> +#include <Library/MvHwDescLib.h>