From 1b5d3b2e8614879f7f612bf033df182baf0b20c8 Mon Sep 17 00:00:00 2001 From: Olivier Martin Date: Tue, 25 Mar 2014 12:38:30 +0000 Subject: [PATCH 04/14] ArmPkg/ArmGic: Make the GicDxe driver depends on ArmGicLib ... and also rename the ArmGicLib sources to use an explicit 'Lib' suffix. Change-Id: I41a06d2ef32de96c7e070489854d577b88df8b2c --- ArmPkg/Drivers/ArmGic/ArmGic.c | 60 -------------- ArmPkg/Drivers/ArmGic/ArmGicDxe.inf | 5 +- ArmPkg/Drivers/ArmGic/ArmGicLib.c | 60 ++++++++++++++ ArmPkg/Drivers/ArmGic/ArmGicLib.inf | 4 +- ArmPkg/Drivers/ArmGic/ArmGicNonSec.c | 44 ----------- ArmPkg/Drivers/ArmGic/ArmGicNonSecLib.c | 44 +++++++++++ ArmPkg/Drivers/ArmGic/ArmGicSec.c | 133 -------------------------------- ArmPkg/Drivers/ArmGic/ArmGicSecLib.c | 133 ++++++++++++++++++++++++++++++++ ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf | 4 +- 9 files changed, 243 insertions(+), 244 deletions(-) delete mode 100644 ArmPkg/Drivers/ArmGic/ArmGic.c create mode 100644 ArmPkg/Drivers/ArmGic/ArmGicLib.c delete mode 100644 ArmPkg/Drivers/ArmGic/ArmGicNonSec.c create mode 100644 ArmPkg/Drivers/ArmGic/ArmGicNonSecLib.c delete mode 100644 ArmPkg/Drivers/ArmGic/ArmGicSec.c create mode 100644 ArmPkg/Drivers/ArmGic/ArmGicSecLib.c diff --git a/ArmPkg/Drivers/ArmGic/ArmGic.c b/ArmPkg/Drivers/ArmGic/ArmGic.c deleted file mode 100644 index ee35190..0000000 --- a/ArmPkg/Drivers/ArmGic/ArmGic.c +++ /dev/null @@ -1,60 +0,0 @@ -/** @file -* -* Copyright (c) 2011-2013, ARM Limited. All rights reserved. -* -* This program and the accompanying materials -* are licensed and made available under the terms and conditions of the BSD License -* which accompanies this distribution. The full text of the license may be found at -* http://opensource.org/licenses/bsd-license.php -* -* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -* -**/ - -#include -#include -#include -#include - -UINTN -EFIAPI -ArmGicGetMaxNumInterrupts ( - IN INTN GicDistributorBase - ) -{ - return 32 * ((MmioRead32 (GicDistributorBase + ARM_GIC_ICDICTR) & 0x1F) + 1); -} - -VOID -EFIAPI -ArmGicSendSgiTo ( - IN INTN GicDistributorBase, - IN INTN TargetListFilter, - IN INTN CPUTargetList, - IN INTN SgiId - ) -{ - MmioWrite32 (GicDistributorBase + ARM_GIC_ICDSGIR, ((TargetListFilter & 0x3) << 24) | ((CPUTargetList & 0xFF) << 16) | SgiId); -} - -UINTN -EFIAPI -ArmGicAcknowledgeInterrupt ( - IN UINTN GicInterruptInterfaceBase - ) -{ - // Read the Interrupt Acknowledge Register - return MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR); -} - -RETURN_STATUS -EFIAPI -ArmGicEndOfInterrupt ( - IN UINTN GicInterruptInterfaceBase, - IN UINTN Source - ) -{ - MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCEIOR, Source); - return RETURN_SUCCESS; -} diff --git a/ArmPkg/Drivers/ArmGic/ArmGicDxe.inf b/ArmPkg/Drivers/ArmGic/ArmGicDxe.inf index 3974f3c..04927e0 100644 --- a/ArmPkg/Drivers/ArmGic/ArmGicDxe.inf +++ b/ArmPkg/Drivers/ArmGic/ArmGicDxe.inf @@ -1,7 +1,7 @@ #/** @file # # Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.
-# Copyright (c) 2012 - 2013, ARM Ltd. All rights reserved.
+# Copyright (c) 2012 - 2014, ARM Ltd. All rights reserved.
# # This program and the accompanying materials # are licensed and made available under the terms and conditions of the BSD License @@ -22,9 +22,7 @@ ENTRY_POINT = InterruptDxeInitialize - [Sources.common] - ArmGic.c ArmGicDxe.c [Packages] @@ -33,6 +31,7 @@ ArmPkg/ArmPkg.dec [LibraryClasses] + ArmGicLib BaseLib UefiLib UefiBootServicesTableLib diff --git a/ArmPkg/Drivers/ArmGic/ArmGicLib.c b/ArmPkg/Drivers/ArmGic/ArmGicLib.c new file mode 100644 index 0000000..ee35190 --- /dev/null +++ b/ArmPkg/Drivers/ArmGic/ArmGicLib.c @@ -0,0 +1,60 @@ +/** @file +* +* Copyright (c) 2011-2013, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include +#include +#include +#include + +UINTN +EFIAPI +ArmGicGetMaxNumInterrupts ( + IN INTN GicDistributorBase + ) +{ + return 32 * ((MmioRead32 (GicDistributorBase + ARM_GIC_ICDICTR) & 0x1F) + 1); +} + +VOID +EFIAPI +ArmGicSendSgiTo ( + IN INTN GicDistributorBase, + IN INTN TargetListFilter, + IN INTN CPUTargetList, + IN INTN SgiId + ) +{ + MmioWrite32 (GicDistributorBase + ARM_GIC_ICDSGIR, ((TargetListFilter & 0x3) << 24) | ((CPUTargetList & 0xFF) << 16) | SgiId); +} + +UINTN +EFIAPI +ArmGicAcknowledgeInterrupt ( + IN UINTN GicInterruptInterfaceBase + ) +{ + // Read the Interrupt Acknowledge Register + return MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR); +} + +RETURN_STATUS +EFIAPI +ArmGicEndOfInterrupt ( + IN UINTN GicInterruptInterfaceBase, + IN UINTN Source + ) +{ + MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCEIOR, Source); + return RETURN_SUCCESS; +} diff --git a/ArmPkg/Drivers/ArmGic/ArmGicLib.inf b/ArmPkg/Drivers/ArmGic/ArmGicLib.inf index dab29b9..d5223df 100644 --- a/ArmPkg/Drivers/ArmGic/ArmGicLib.inf +++ b/ArmPkg/Drivers/ArmGic/ArmGicLib.inf @@ -20,8 +20,8 @@ LIBRARY_CLASS = ArmGicLib [Sources] - ArmGic.c - ArmGicNonSec.c + ArmGicLib.c + ArmGicNonSecLib.c [LibraryClasses] IoLib diff --git a/ArmPkg/Drivers/ArmGic/ArmGicNonSec.c b/ArmPkg/Drivers/ArmGic/ArmGicNonSec.c deleted file mode 100644 index 55ff56e..0000000 --- a/ArmPkg/Drivers/ArmGic/ArmGicNonSec.c +++ /dev/null @@ -1,44 +0,0 @@ -/** @file -* -* Copyright (c) 2011, ARM Limited. All rights reserved. -* -* This program and the accompanying materials -* are licensed and made available under the terms and conditions of the BSD License -* which accompanies this distribution. The full text of the license may be found at -* http://opensource.org/licenses/bsd-license.php -* -* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -* -**/ - -#include -#include -#include - - -VOID -EFIAPI -ArmGicEnableInterruptInterface ( - IN INTN GicInterruptInterfaceBase - ) -{ - /* - * Enable the CPU interface in Non-Secure world - * Note: The ICCICR register is banked when Security extensions are implemented - */ - MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR, 0x1); -} - -VOID -EFIAPI -ArmGicEnableDistributor ( - IN INTN GicDistributorBase - ) -{ - /* - * Enable GIC distributor in Non-Secure world. - * Note: The ICDDCR register is banked when Security extensions are implemented - */ - MmioWrite32 (GicDistributorBase + ARM_GIC_ICDDCR, 0x1); -} diff --git a/ArmPkg/Drivers/ArmGic/ArmGicNonSecLib.c b/ArmPkg/Drivers/ArmGic/ArmGicNonSecLib.c new file mode 100644 index 0000000..55ff56e --- /dev/null +++ b/ArmPkg/Drivers/ArmGic/ArmGicNonSecLib.c @@ -0,0 +1,44 @@ +/** @file +* +* Copyright (c) 2011, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include +#include +#include + + +VOID +EFIAPI +ArmGicEnableInterruptInterface ( + IN INTN GicInterruptInterfaceBase + ) +{ + /* + * Enable the CPU interface in Non-Secure world + * Note: The ICCICR register is banked when Security extensions are implemented + */ + MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR, 0x1); +} + +VOID +EFIAPI +ArmGicEnableDistributor ( + IN INTN GicDistributorBase + ) +{ + /* + * Enable GIC distributor in Non-Secure world. + * Note: The ICDDCR register is banked when Security extensions are implemented + */ + MmioWrite32 (GicDistributorBase + ARM_GIC_ICDDCR, 0x1); +} diff --git a/ArmPkg/Drivers/ArmGic/ArmGicSec.c b/ArmPkg/Drivers/ArmGic/ArmGicSec.c deleted file mode 100644 index f249eac..0000000 --- a/ArmPkg/Drivers/ArmGic/ArmGicSec.c +++ /dev/null @@ -1,133 +0,0 @@ -/** @file -* -* Copyright (c) 2011-2013, ARM Limited. All rights reserved. -* -* This program and the accompanying materials -* are licensed and made available under the terms and conditions of the BSD License -* which accompanies this distribution. The full text of the license may be found at -* http://opensource.org/licenses/bsd-license.php -* -* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -* -**/ - -#include -#include -#include -#include -#include -#include - -/* - * This function configures the all interrupts to be Non-secure. - * - */ -VOID -EFIAPI -ArmGicSetupNonSecure ( - IN UINTN MpId, - IN INTN GicDistributorBase, - IN INTN GicInterruptInterfaceBase - ) -{ - UINTN InterruptId; - UINTN CachedPriorityMask; - UINTN Index; - - CachedPriorityMask = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR); - - // Set priority Mask so that no interrupts get through to CPU - MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0); - - InterruptId = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR); - - // Only try to clear valid interrupts. Ignore spurious interrupts. - while ((InterruptId & 0x3FF) < ArmGicGetMaxNumInterrupts (GicDistributorBase)) { - // Some of the SGI's are still pending, read Ack register and send End of Interrupt Signal - ArmGicEndOfInterrupt (GicInterruptInterfaceBase, InterruptId); - - // Next - InterruptId = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR); - } - - // Only the primary core should set the Non Secure bit to the SPIs (Shared Peripheral Interrupt). - if (ArmPlatformIsPrimaryCore (MpId)) { - // Ensure all GIC interrupts are Non-Secure - for (Index = 0; Index < (ArmGicGetMaxNumInterrupts (GicDistributorBase) / 32); Index++) { - MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4), 0xffffffff); - } - } else { - // The secondary cores only set the Non Secure bit to their banked PPIs - MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR, 0xffffffff); - } - - // Ensure all interrupts can get through the priority mask - MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, CachedPriorityMask); -} - -/* - * This function configures the interrupts set by the mask to be secure. - * - */ -VOID -EFIAPI -ArmGicSetSecureInterrupts ( - IN UINTN GicDistributorBase, - IN UINTN* GicSecureInterruptMask, - IN UINTN GicSecureInterruptMaskSize - ) -{ - UINTN Index; - UINT32 InterruptStatus; - - // We must not have more interrupts defined by the mask than the number of available interrupts - ASSERT(GicSecureInterruptMaskSize <= (ArmGicGetMaxNumInterrupts (GicDistributorBase) / 32)); - - // Set all the interrupts defined by the mask as Secure - for (Index = 0; Index < GicSecureInterruptMaskSize; Index++) { - InterruptStatus = MmioRead32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4)); - MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4), InterruptStatus & (~GicSecureInterruptMask[Index])); - } -} - -VOID -EFIAPI -ArmGicEnableInterruptInterface ( - IN INTN GicInterruptInterfaceBase - ) -{ - // Set Priority Mask to allow interrupts - MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0x000000FF); - - // Enable CPU interface in Secure world - // Enable CPU interface in Non-secure World - // Signal Secure Interrupts to CPU using FIQ line * - MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR, - ARM_GIC_ICCICR_ENABLE_SECURE | - ARM_GIC_ICCICR_ENABLE_NS | - ARM_GIC_ICCICR_SIGNAL_SECURE_TO_FIQ); -} - -VOID -EFIAPI -ArmGicDisableInterruptInterface ( - IN INTN GicInterruptInterfaceBase - ) -{ - UINT32 ControlValue; - - // Disable CPU interface in Secure world and Non-secure World - ControlValue = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR); - MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR, ControlValue & ~(ARM_GIC_ICCICR_ENABLE_SECURE | ARM_GIC_ICCICR_ENABLE_NS)); -} - -VOID -EFIAPI -ArmGicEnableDistributor ( - IN INTN GicDistributorBase - ) -{ - // Turn on the GIC distributor - MmioWrite32 (GicDistributorBase + ARM_GIC_ICDDCR, 1); -} diff --git a/ArmPkg/Drivers/ArmGic/ArmGicSecLib.c b/ArmPkg/Drivers/ArmGic/ArmGicSecLib.c new file mode 100644 index 0000000..f249eac --- /dev/null +++ b/ArmPkg/Drivers/ArmGic/ArmGicSecLib.c @@ -0,0 +1,133 @@ +/** @file +* +* Copyright (c) 2011-2013, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include +#include +#include +#include +#include +#include + +/* + * This function configures the all interrupts to be Non-secure. + * + */ +VOID +EFIAPI +ArmGicSetupNonSecure ( + IN UINTN MpId, + IN INTN GicDistributorBase, + IN INTN GicInterruptInterfaceBase + ) +{ + UINTN InterruptId; + UINTN CachedPriorityMask; + UINTN Index; + + CachedPriorityMask = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR); + + // Set priority Mask so that no interrupts get through to CPU + MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0); + + InterruptId = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR); + + // Only try to clear valid interrupts. Ignore spurious interrupts. + while ((InterruptId & 0x3FF) < ArmGicGetMaxNumInterrupts (GicDistributorBase)) { + // Some of the SGI's are still pending, read Ack register and send End of Interrupt Signal + ArmGicEndOfInterrupt (GicInterruptInterfaceBase, InterruptId); + + // Next + InterruptId = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR); + } + + // Only the primary core should set the Non Secure bit to the SPIs (Shared Peripheral Interrupt). + if (ArmPlatformIsPrimaryCore (MpId)) { + // Ensure all GIC interrupts are Non-Secure + for (Index = 0; Index < (ArmGicGetMaxNumInterrupts (GicDistributorBase) / 32); Index++) { + MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4), 0xffffffff); + } + } else { + // The secondary cores only set the Non Secure bit to their banked PPIs + MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR, 0xffffffff); + } + + // Ensure all interrupts can get through the priority mask + MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, CachedPriorityMask); +} + +/* + * This function configures the interrupts set by the mask to be secure. + * + */ +VOID +EFIAPI +ArmGicSetSecureInterrupts ( + IN UINTN GicDistributorBase, + IN UINTN* GicSecureInterruptMask, + IN UINTN GicSecureInterruptMaskSize + ) +{ + UINTN Index; + UINT32 InterruptStatus; + + // We must not have more interrupts defined by the mask than the number of available interrupts + ASSERT(GicSecureInterruptMaskSize <= (ArmGicGetMaxNumInterrupts (GicDistributorBase) / 32)); + + // Set all the interrupts defined by the mask as Secure + for (Index = 0; Index < GicSecureInterruptMaskSize; Index++) { + InterruptStatus = MmioRead32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4)); + MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4), InterruptStatus & (~GicSecureInterruptMask[Index])); + } +} + +VOID +EFIAPI +ArmGicEnableInterruptInterface ( + IN INTN GicInterruptInterfaceBase + ) +{ + // Set Priority Mask to allow interrupts + MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0x000000FF); + + // Enable CPU interface in Secure world + // Enable CPU interface in Non-secure World + // Signal Secure Interrupts to CPU using FIQ line * + MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR, + ARM_GIC_ICCICR_ENABLE_SECURE | + ARM_GIC_ICCICR_ENABLE_NS | + ARM_GIC_ICCICR_SIGNAL_SECURE_TO_FIQ); +} + +VOID +EFIAPI +ArmGicDisableInterruptInterface ( + IN INTN GicInterruptInterfaceBase + ) +{ + UINT32 ControlValue; + + // Disable CPU interface in Secure world and Non-secure World + ControlValue = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR); + MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR, ControlValue & ~(ARM_GIC_ICCICR_ENABLE_SECURE | ARM_GIC_ICCICR_ENABLE_NS)); +} + +VOID +EFIAPI +ArmGicEnableDistributor ( + IN INTN GicDistributorBase + ) +{ + // Turn on the GIC distributor + MmioWrite32 (GicDistributorBase + ARM_GIC_ICDDCR, 1); +} diff --git a/ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf b/ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf index bb7f242..b888eb5 100644 --- a/ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf +++ b/ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf @@ -20,8 +20,8 @@ LIBRARY_CLASS = ArmGicLib [Sources] - ArmGic.c - ArmGicSec.c + ArmGicLib.c + ArmGicSecLib.c [Packages] ArmPkg/ArmPkg.dec -- 1.8.5