On 12/20/19 4:51 PM, Dan Williams wrote:
On Fri, Dec 20, 2019 at 4:41 PM John Hubbard jhubbard@nvidia.com wrote:
On 12/20/19 4:33 PM, Dan Williams wrote: ...
I believe there might be also a different solution for this: For transparent huge pages, we could find a space in 'struct page' of the second page in the huge page for proper pin counter and just account pins there so we'd have full width of 32-bits for it.
That would require THP accounting for dax pages. It is something that was probably going to be needed, but this would seem to force the issue.
Thanks for mentioning that, it wasn't obvious to me yet.
How easy is it for mere mortals outside of Intel, to set up a DAX (nvdimm?) test setup? I'd hate to go into this without having that coverage up and running. It's been sketchy enough as it is. :)
You too can have the power of the gods for the low low price of a kernel command line parameter, or a qemu setup.
Details here:
https://nvdimm.wiki.kernel.org/how_to_choose_the_correct_memmap_kernel_param... https://nvdimm.wiki.kernel.org/pmem_in_qemu
Sweeeet! Now I can really cause some damage. :)
thanks,