[PATCH 6.17 136/563] arm64: dts: rockchip: Fix network on rk3576 evb1 board

6.17-stable review patch. If anyone has any objections, please let me know.

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From: Sebastian Reichel sebastian.reichel@collabora.com

[ Upstream commit 843367c7ed196bd0806c8776cba108aaf6923b82 ]

The RK3576 EVB1 has a RTL8211F PHY for each GMAC interface with a dedicated reset line and the 25MHz clock provided by the SoC. The current description results in non-working Ethernet as the clocks are only enabled by the PHY driver, but probing the right PHY driver currently requires that the PHY ID register can be read for automatic identification.

This fixes up the network description to get the network functionality working reliably and cleans up usage of deprecated DT properties while at it.

Fixes: f135a1a07352 ("arm64: dts: rockchip: Add rk3576 evb1 board") Signed-off-by: Sebastian Reichel sebastian.reichel@collabora.com Link: https://lore.kernel.org/r/20250910-rk3576-evb-network-v1-1-68ed4df272a2@coll... Signed-off-by: Heiko Stuebner heiko@sntech.de Signed-off-by: Sasha Levin sashal@kernel.org --- .../boot/dts/rockchip/rk3576-evb1-v10.dts | 38 ++++++++++++++----- 1 file changed, 28 insertions(+), 10 deletions(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts index 3007e0179611b..012c21b58a5a1 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts @@ -275,9 +275,6 @@ &eth0m0_rx_bus2 &eth0m0_rgmii_clk &eth0m0_rgmii_bus &ethm0_clk0_25m_out>; - snps,reset-gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 20000 100000>; tx_delay = <0x21>; status = "okay"; }; @@ -293,9 +290,6 @@ &eth1m0_rx_bus2 &eth1m0_rgmii_clk &eth1m0_rgmii_bus &ethm0_clk1_25m_out>; - snps,reset-gpio = <&gpio3 RK_PA3 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 20000 100000>; tx_delay = <0x20>; status = "okay"; }; @@ -715,18 +709,32 @@ hym8563: rtc@51 { };

&mdio0 { - rgmii_phy0: phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; + rgmii_phy0: ethernet-phy@1 { + compatible = "ethernet-phy-id001c.c916"; reg = <0x1>; clocks = <&cru REFCLKO25M_GMAC0_OUT>; + assigned-clocks = <&cru REFCLKO25M_GMAC0_OUT>; + assigned-clock-rates = <25000000>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_phy0_rst>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>; }; };

&mdio1 { - rgmii_phy1: phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; + rgmii_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-id001c.c916"; reg = <0x1>; clocks = <&cru REFCLKO25M_GMAC1_OUT>; + assigned-clocks = <&cru REFCLKO25M_GMAC1_OUT>; + assigned-clock-rates = <25000000>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_phy1_rst>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_LOW>; }; };

@@ -772,6 +780,16 @@ rtc_int: rtc-int { }; };

+ network { + rgmii_phy0_rst: rgmii-phy0-rst { + rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + rgmii_phy1_rst: rgmii-phy1-rst { + rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + pcie0 { pcie0_rst: pcie0-rst { rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;