From 03dae1c2ccc49d26de939b0f20ed3d5287eba06f Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Mon, 29 May 2023 11:19:19 +0300 Subject: [PATCH 04/12] drm/msm/a5xx: delay devfreq resumtion Dekay resuming of devfreq so that main GDSC / regulators are started up with the highest possible freq. Signed-off-by: Dmitry Baryshkov --- kernel/drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 5 ++++- kernel/drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 4 +++- kernel/drivers/gpu/drm/msm/msm_gpu.c | 17 ++++++++++++++--- kernel/drivers/gpu/drm/msm/msm_gpu.h | 1 + 4 files changed, 22 insertions(+), 5 deletions(-) diff --git a/kernel/drivers/gpu/drm/msm/adreno/a4xx_gpu.c b/kernel/drivers/gpu/drm/msm/adreno/a4xx_gpu.c index 501b1b899cce..e1f6caf8991f 100644 --- a/kernel/drivers/gpu/drm/msm/adreno/a4xx_gpu.c +++ b/kernel/drivers/gpu/drm/msm/adreno/a4xx_gpu.c @@ -574,7 +574,7 @@ static int a4xx_pm_resume(struct msm_gpu *gpu) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); int ret; - ret = msm_gpu_pm_resume(gpu); + ret = msm_gpu_pm_resume_no_devfreq(gpu); if (ret) return ret; @@ -587,6 +587,9 @@ static int a4xx_pm_resume(struct msm_gpu *gpu) { reg = gpu_read(gpu, REG_A4XX_RBBM_POWER_STATUS); } while (!(reg & A4XX_RBBM_POWER_CNTL_IP_SP_TP_PWR_ON)); } + + msm_devfreq_resume(gpu); + return 0; } diff --git a/kernel/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/kernel/drivers/gpu/drm/msm/adreno/a5xx_gpu.c index 1264f4eff6e8..6cb33af3612f 100644 --- a/kernel/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +++ b/kernel/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -1395,7 +1395,7 @@ static int a5xx_pm_resume(struct msm_gpu *gpu) } /* Turn on the core power */ - ret = msm_gpu_pm_resume(gpu); + ret = msm_gpu_pm_resume_no_devfreq(gpu); if (ret) return ret; @@ -1432,6 +1432,8 @@ static int a5xx_pm_resume(struct msm_gpu *gpu) DRM_ERROR("%s: timeout waiting for SP GDSC enable\n", gpu->name); + msm_devfreq_resume(gpu); + return ret; } diff --git a/kernel/drivers/gpu/drm/msm/msm_gpu.c b/kernel/drivers/gpu/drm/msm/msm_gpu.c index ff274da3aef4..829554b2b76b 100644 --- a/kernel/drivers/gpu/drm/msm/msm_gpu.c +++ b/kernel/drivers/gpu/drm/msm/msm_gpu.c @@ -94,7 +94,7 @@ static int disable_axi(struct msm_gpu *gpu) return 0; } -int msm_gpu_pm_resume(struct msm_gpu *gpu) +int msm_gpu_pm_resume_no_devfreq(struct msm_gpu *gpu) { int ret; @@ -113,13 +113,24 @@ int msm_gpu_pm_resume(struct msm_gpu *gpu) if (ret) return ret; - msm_devfreq_resume(gpu); - gpu->needs_hw_init = true; return 0; } +int msm_gpu_pm_resume(struct msm_gpu *gpu) +{ + int ret; + + ret = msm_gpu_pm_resume_no_devfreq(gpu); + if (ret) + return ret; + + msm_devfreq_resume(gpu); + + return 0; +} + int msm_gpu_pm_suspend(struct msm_gpu *gpu) { int ret; diff --git a/kernel/drivers/gpu/drm/msm/msm_gpu.h b/kernel/drivers/gpu/drm/msm/msm_gpu.h index ed1684650932..25abc3e9fe46 100644 --- a/kernel/drivers/gpu/drm/msm/msm_gpu.h +++ b/kernel/drivers/gpu/drm/msm/msm_gpu.h @@ -466,6 +466,7 @@ static inline void gpu_write64(struct msm_gpu *gpu, u32 lo, u32 hi, u64 val) int msm_gpu_pm_suspend(struct msm_gpu *gpu); int msm_gpu_pm_resume(struct msm_gpu *gpu); +int msm_gpu_pm_resume_no_devfreq(struct msm_gpu *gpu); int msm_submitqueue_init(struct drm_device *drm, struct msm_file_private *ctx); struct msm_gpu_submitqueue *msm_submitqueue_get(struct msm_file_private *ctx, -- 2.39.2