From 2f931a7edee430c95f8759cad94f40ec4662139e Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Mon, 29 May 2023 11:16:03 +0300 Subject: [PATCH 02/12] clk: cpu-8996: upgrad APCS/CPU clocks programming sequences Signed-off-by: Dmitry Baryshkov --- kernel/drivers/clk/qcom/clk-cpu-8996.c | 42 ++++++++++++++++++++++---- 1 file changed, 36 insertions(+), 6 deletions(-) diff --git a/kernel/drivers/clk/qcom/clk-cpu-8996.c b/kernel/drivers/clk/qcom/clk-cpu-8996.c index 1c00eb629b61..592c7c3cdeb7 100644 --- a/kernel/drivers/clk/qcom/clk-cpu-8996.c +++ b/kernel/drivers/clk/qcom/clk-cpu-8996.c @@ -60,6 +60,8 @@ #include #include +#include + #include "clk-alpha-pll.h" #include "clk-regmap.h" #include "clk-regmap-mux.h" @@ -76,10 +78,16 @@ enum _pmux_input { #define PWRCL_REG_OFFSET 0x0 #define PERFCL_REG_OFFSET 0x80000 #define MUX_OFFSET 0x40 +#define CLK_CTL_OFFSET 0x44 +#define CLK_CTL_AUTO_CLK_SEL BIT(8) #define ALT_PLL_OFFSET 0x100 #define SSSCTL_OFFSET 0x160 +#define PSCTL_OFFSET 0x164 #define PMUX_MASK 0x3 +#define MUX_AUTO_CLK_SEL_ALWAYS_ON_MASK GENMASK(5, 4) +#define MUX_AUTO_CLK_SEL_ALWAYS_ON_GPLL0_SEL \ + FIELD_PREP(MUX_AUTO_CLK_SEL_ALWAYS_ON_MASK, 0x03) static const u8 prim_pll_regs[PLL_OFF_MAX_REGS] = { [PLL_OFF_L_VAL] = 0x04, @@ -128,7 +136,7 @@ static struct clk_alpha_pll pwrcl_pll = { .name = "pwrcl_pll", .parent_data = pll_parent, .num_parents = ARRAY_SIZE(pll_parent), - .ops = &clk_alpha_pll_huayra_ops, + .ops = &clk_alpha_pll_hwfsm_ops, }, }; @@ -140,7 +148,7 @@ static struct clk_alpha_pll perfcl_pll = { .name = "perfcl_pll", .parent_data = pll_parent, .num_parents = ARRAY_SIZE(pll_parent), - .ops = &clk_alpha_pll_huayra_ops, + .ops = &clk_alpha_pll_hwfsm_ops, }, }; @@ -432,26 +440,47 @@ static int qcom_cpu_clk_msm8996_register_clks(struct device *dev, { int i, ret; - /* Select GPLL0 for 300MHz for the both clusters */ + /* Select GPLL0 for 300MHz for both clusters */ regmap_write(regmap, PERFCL_REG_OFFSET + MUX_OFFSET, 0xc); regmap_write(regmap, PWRCL_REG_OFFSET + MUX_OFFSET, 0xc); /* Ensure write goes through before PLLs are reconfigured */ udelay(5); + /* Set the auto clock sel always-on source to GPLL0/2 (300MHz) */ + regmap_update_bits(regmap, PWRCL_REG_OFFSET + MUX_OFFSET, + MUX_AUTO_CLK_SEL_ALWAYS_ON_MASK, + MUX_AUTO_CLK_SEL_ALWAYS_ON_GPLL0_SEL); + regmap_update_bits(regmap, PERFCL_REG_OFFSET + MUX_OFFSET, + MUX_AUTO_CLK_SEL_ALWAYS_ON_MASK, + MUX_AUTO_CLK_SEL_ALWAYS_ON_GPLL0_SEL); + clk_alpha_pll_configure(&pwrcl_pll, regmap, &hfpll_config); clk_alpha_pll_configure(&perfcl_pll, regmap, &hfpll_config); clk_alpha_pll_configure(&pwrcl_alt_pll, regmap, &altpll_config); clk_alpha_pll_configure(&perfcl_alt_pll, regmap, &altpll_config); /* Wait for PLL(s) to lock */ - udelay(50); + udelay(50); + + /* Enable auto clock selection for both clusters */ + regmap_update_bits(regmap, PWRCL_REG_OFFSET + CLK_CTL_OFFSET, + CLK_CTL_AUTO_CLK_SEL, CLK_CTL_AUTO_CLK_SEL); + regmap_update_bits(regmap, PERFCL_REG_OFFSET + CLK_CTL_OFFSET, + CLK_CTL_AUTO_CLK_SEL, CLK_CTL_AUTO_CLK_SEL); + + /* Ensure write goes through before muxes are switched */ + udelay(5); qcom_cpu_clk_msm8996_acd_init(regmap); + /* Pulse swallower and soft-start settings */ + regmap_write(regmap, PWRCL_REG_OFFSET + PSCTL_OFFSET, 0x00030005); + regmap_write(regmap, PERFCL_REG_OFFSET + PSCTL_OFFSET, 0x00030005); + /* Switch clusters to use the ACD leg */ - regmap_write(regmap, PWRCL_REG_OFFSET + MUX_OFFSET, 0x2); - regmap_write(regmap, PERFCL_REG_OFFSET + MUX_OFFSET, 0x2); + regmap_write(regmap, PWRCL_REG_OFFSET + MUX_OFFSET, 0x32); + regmap_write(regmap, PERFCL_REG_OFFSET + MUX_OFFSET, 0x32); for (i = 0; i < ARRAY_SIZE(cpu_msm8996_hw_clks); i++) { ret = devm_clk_hw_register(dev, cpu_msm8996_hw_clks[i]); @@ -542,6 +571,7 @@ static int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event, if (cnd->new_rate < DIV_2_THRESHOLD && cnd->old_rate > DIV_2_THRESHOLD) clk_cpu_8996_pmux_set_parent(&cpuclk->clkr.hw, ACD_INDEX); + break; default: break; } -- 2.39.2