From bbdcaea66db40e4a90cd6ea99505ccdb7c21076f Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Mon, 29 May 2023 11:30:59 +0300 Subject: [PATCH 09/12] icc: msm8996: split the mnoc into mnoc and mnoc_ahb The mnoc consits of two major parts: memory and configuration ones. Split the device bindings. Signed-off-by: Dmitry Baryshkov --- kernel/drivers/interconnect/qcom/msm8996.c | 53 +++++++++++++------ .../dt-bindings/interconnect/qcom,msm8996.h | 47 ++++++++-------- 2 files changed, 62 insertions(+), 38 deletions(-) diff --git a/kernel/drivers/interconnect/qcom/msm8996.c b/kernel/drivers/interconnect/qcom/msm8996.c index 5c77f53a9d9a..d5ea193738c2 100644 --- a/kernel/drivers/interconnect/qcom/msm8996.c +++ b/kernel/drivers/interconnect/qcom/msm8996.c @@ -24,7 +24,14 @@ static const char * const bus_mm_clocks[] = { "bus", "bus_a", - "iface" + "mmagic", "mmagic-cfg", + "mmagic-mdss", "mmagic-mdss-cfg", + "mmagic-camss", "mmagic-camss-cfg", + "mmagic-videoss", "mmagic-videoss-cfg", +}; + +static const char * const bus_mm_ahb_clocks[] = { + "iface", }; static const char * const bus_a0noc_clocks[] = { @@ -1968,10 +1975,31 @@ static struct qcom_icc_node *mnoc_nodes[] = { [MASTER_VFE] = &mas_vfe, [MASTER_SNOC_VMEM] = &mas_snoc_vmem, [MASTER_VIDEO_P0_OCMEM] = &mas_venus_vmem, - [MASTER_CNOC_MNOC_MMSS_CFG] = &mas_cnoc_mnoc_mmss_cfg, [SLAVE_MNOC_BIMC] = &slv_mnoc_bimc, [SLAVE_VMEM] = &slv_vmem, [SLAVE_SERVICE_MNOC] = &slv_srvc_mnoc, +}; + +static const struct regmap_config msm8996_mnoc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x1c000, + .fast_io = true +}; + +static const struct qcom_icc_desc msm8996_mnoc = { + .type = QCOM_ICC_NOC, + .nodes = mnoc_nodes, + .num_nodes = ARRAY_SIZE(mnoc_nodes), + .clocks = bus_mm_clocks, + .num_clocks = ARRAY_SIZE(bus_mm_clocks), + .num_rate_clocks = 2, + .regmap_cfg = &msm8996_mnoc_regmap_config +}; + +static struct qcom_icc_node *mnoc_ahb_nodes[] = { + [MASTER_CNOC_MNOC_MMSS_CFG] = &mas_cnoc_mnoc_mmss_cfg, [SLAVE_MMAGIC_CFG] = &slv_mmagic_cfg, [SLAVE_CPR_CFG] = &slv_cpr_cfg, [SLAVE_MISC_CFG] = &slv_misc_cfg, @@ -1995,21 +2023,13 @@ static struct qcom_icc_node *mnoc_nodes[] = { [SLAVE_SMMU_VFE_CFG] = &slv_smmu_vfe_cfg }; -static const struct regmap_config msm8996_mnoc_regmap_config = { - .reg_bits = 32, - .reg_stride = 4, - .val_bits = 32, - .max_register = 0x1c000, - .fast_io = true -}; - -static const struct qcom_icc_desc msm8996_mnoc = { +static const struct qcom_icc_desc msm8996_mnoc_ahb = { .type = QCOM_ICC_NOC, - .nodes = mnoc_nodes, - .num_nodes = ARRAY_SIZE(mnoc_nodes), - .clocks = bus_mm_clocks, - .num_clocks = ARRAY_SIZE(bus_mm_clocks), - .num_rate_clocks = 3, + .nodes = mnoc_ahb_nodes, + .num_nodes = ARRAY_SIZE(mnoc_ahb_nodes), + .clocks = bus_mm_ahb_clocks, + .num_clocks = ARRAY_SIZE(bus_mm_ahb_clocks), + .num_rate_clocks = 1, .regmap_cfg = &msm8996_mnoc_regmap_config }; @@ -2100,6 +2120,7 @@ static const struct of_device_id qnoc_of_match[] = { { .compatible = "qcom,msm8996-bimc", .data = &msm8996_bimc}, { .compatible = "qcom,msm8996-cnoc", .data = &msm8996_cnoc}, { .compatible = "qcom,msm8996-mnoc", .data = &msm8996_mnoc}, + { .compatible = "qcom,msm8996-mnoc-ahb", .data = &msm8996_mnoc_ahb}, { .compatible = "qcom,msm8996-pnoc", .data = &msm8996_pnoc}, { .compatible = "qcom,msm8996-snoc", .data = &msm8996_snoc}, { } diff --git a/kernel/include/dt-bindings/interconnect/qcom,msm8996.h b/kernel/include/dt-bindings/interconnect/qcom,msm8996.h index a0b7c0ec7bed..8ee5ec98c19b 100644 --- a/kernel/include/dt-bindings/interconnect/qcom,msm8996.h +++ b/kernel/include/dt-bindings/interconnect/qcom,msm8996.h @@ -86,31 +86,34 @@ #define MASTER_VFE 7 #define MASTER_SNOC_VMEM 8 #define MASTER_VIDEO_P0_OCMEM 9 -#define MASTER_CNOC_MNOC_MMSS_CFG 10 +/* #define MASTER_CNOC_MNOC_MMSS_CFG 10 - removed */ #define SLAVE_MNOC_BIMC 11 #define SLAVE_VMEM 12 #define SLAVE_SERVICE_MNOC 13 -#define SLAVE_MMAGIC_CFG 14 -#define SLAVE_CPR_CFG 15 -#define SLAVE_MISC_CFG 16 -#define SLAVE_VENUS_THROTTLE_CFG 17 -#define SLAVE_VENUS_CFG 18 -#define SLAVE_VMEM_CFG 19 -#define SLAVE_DSA_CFG 20 -#define SLAVE_MMSS_CLK_CFG 21 -#define SLAVE_DSA_MPU_CFG 22 -#define SLAVE_MNOC_MPU_CFG 23 -#define SLAVE_DISPLAY_CFG 24 -#define SLAVE_DISPLAY_THROTTLE_CFG 25 -#define SLAVE_CAMERA_CFG 26 -#define SLAVE_CAMERA_THROTTLE_CFG 27 -#define SLAVE_GRAPHICS_3D_CFG 28 -#define SLAVE_SMMU_MDP_CFG 29 -#define SLAVE_SMMU_ROT_CFG 30 -#define SLAVE_SMMU_VENUS_CFG 31 -#define SLAVE_SMMU_CPP_CFG 32 -#define SLAVE_SMMU_JPEG_CFG 33 -#define SLAVE_SMMU_VFE_CFG 34 + +/* MNOC_AHB */ +#define MASTER_CNOC_MNOC_MMSS_CFG 0 +#define SLAVE_MMAGIC_CFG 1 +#define SLAVE_CPR_CFG 2 +#define SLAVE_MISC_CFG 3 +#define SLAVE_VENUS_THROTTLE_CFG 4 +#define SLAVE_VENUS_CFG 5 +#define SLAVE_VMEM_CFG 6 +#define SLAVE_DSA_CFG 7 +#define SLAVE_MMSS_CLK_CFG 8 +#define SLAVE_DSA_MPU_CFG 9 +#define SLAVE_MNOC_MPU_CFG 10 +#define SLAVE_DISPLAY_CFG 11 +#define SLAVE_DISPLAY_THROTTLE_CFG 12 +#define SLAVE_CAMERA_CFG 13 +#define SLAVE_CAMERA_THROTTLE_CFG 14 +#define SLAVE_GRAPHICS_3D_CFG 15 +#define SLAVE_SMMU_MDP_CFG 16 +#define SLAVE_SMMU_ROT_CFG 17 +#define SLAVE_SMMU_VENUS_CFG 18 +#define SLAVE_SMMU_CPP_CFG 19 +#define SLAVE_SMMU_JPEG_CFG 20 +#define SLAVE_SMMU_VFE_CFG 21 /* PNOC */ #define MASTER_SNOC_PNOC 0 -- 2.39.2