diff --git a/kernel/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi b/kernel/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
index 0b01bc9a0531..0bf3e84baeef 100644
--- a/kernel/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
+++ b/kernel/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
@@ -1014,7 +1014,7 @@ &pmi8994_spmi_regulators {
 	vdd_gfx: s2@1700 {
 		reg = <0x1700 0x100>;
 		regulator-name = "VDD_GFX";
-		regulator-min-microvolt = <400000>;
+		regulator-min-microvolt = <980000>;
 		regulator-max-microvolt = <1015000>;
 	};
 };
@@ -1418,8 +1418,3 @@ &wcd9335 {
 	vdd-rx-supply = <&vreg_s4a_1p8>;
 	vdd-io-supply = <&vreg_s4a_1p8>;
 };
-
-&cpr3_gfx {
-	status = "okay";
-	vdd-supply = <&vdd_gfx>;
-};
diff --git a/kernel/arch/arm64/boot/dts/qcom/msm8996.dtsi b/kernel/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 7ff03ff3cbf9..c3dfdb00bd3c 100644
--- a/kernel/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/kernel/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -1070,6 +1070,8 @@ mmcc: clock-controller@8c0000 {
 			#reset-cells = <1>;
 			#power-domain-cells = <1>;
 			reg = <0x008c0000 0x40000>;
+			power-domains = <&rpmpd MSM8996_VDDMX>;
+			required-opps = <&rpmpd_opp7>;
 			assigned-clocks = <&mmcc MMPLL9_PLL>,
 					  <&mmcc MMPLL1_PLL>,
 					  <&mmcc MMPLL3_PLL>,
@@ -1318,8 +1320,8 @@ gpu: gpu@b00000 {
 			interconnects = <&bimc MASTER_GRAPHICS_3D &bimc SLAVE_EBI_CH0>;
 			interconnect-names = "gfx-mem";
 
-			power-domains = <&mmcc GPU_GX_GDSC>, <&cpr3_gfx 0>, <&rpmpd MSM8996_VDDMX>;
-			power-domain-names = "gx", "cpr", "mx";
+			power-domains = <&mmcc GPU_GX_GDSC>;
+			power-domain-names = "gx";
 			iommus = <&adreno_smmu 0>;
 
 			nvmem-cells = <&speedbin_efuse>;
@@ -1346,37 +1348,30 @@ gpu_opp_table: opp-table {
 				opp-624000000 {
 					opp-hz = /bits/ 64 <624000000>;
 					opp-supported-hw = <0x09>;
-					required-opps = <&cpr3_gfx_opp7 &rpmpd_opp7>;
 				};
 				opp-560000000 {
 					opp-hz = /bits/ 64 <560000000>;
 					opp-supported-hw = <0x0d>;
-					required-opps = <&cpr3_gfx_opp6 &rpmpd_opp7>;
 				};
 				opp-510000000 {
 					opp-hz = /bits/ 64 <510000000>;
 					opp-supported-hw = <0xFF>;
-					required-opps = <&cpr3_gfx_opp5 &rpmpd_opp5>;
 				};
 				opp-401800000 {
 					opp-hz = /bits/ 64 <401800000>;
 					opp-supported-hw = <0xFF>;
-					required-opps = <&cpr3_gfx_opp4 &rpmpd_opp5>;
 				};
 				opp-315000000 {
 					opp-hz = /bits/ 64 <315000000>;
 					opp-supported-hw = <0xFF>;
-					required-opps = <&cpr3_gfx_opp3 &rpmpd_opp4>;
 				};
 				opp-214000000 {
 					opp-hz = /bits/ 64 <214000000>;
 					opp-supported-hw = <0xFF>;
-					required-opps = <&cpr3_gfx_opp2 &rpmpd_opp4>;
 				};
 				opp-133000000 {
 					opp-hz = /bits/ 64 <133000000>;
 					opp-supported-hw = <0xFF>;
-					required-opps = <&cpr3_gfx_opp1 &rpmpd_opp4>;
 				};
 			};
 
diff --git a/kernel/arch/arm64/configs/db820c_defconfig b/kernel/arch/arm64/configs/db820c_defconfig
index bc9fb4ec97d0..78bcad2d236c 100644
--- a/kernel/arch/arm64/configs/db820c_defconfig
+++ b/kernel/arch/arm64/configs/db820c_defconfig
@@ -794,6 +794,7 @@ CONFIG_QCOM_SPM=y
 CONFIG_QCOM_WCNSS_CTRL=y
 CONFIG_QCOM_APR=y
 CONFIG_SOC_TI=y
+CONFIG_DEVFREQ_GOV_PERFORMANCE=y
 CONFIG_DEVFREQ_GOV_USERSPACE=m
 CONFIG_EXTCON_PTN5150=m
 CONFIG_EXTCON_USB_GPIO=y
diff --git a/kernel/drivers/gpu/drm/msm/msm_gpu_devfreq.c b/kernel/drivers/gpu/drm/msm/msm_gpu_devfreq.c
index 9990d15858db..e6b3ba479a75 100644
--- a/kernel/drivers/gpu/drm/msm/msm_gpu_devfreq.c
+++ b/kernel/drivers/gpu/drm/msm/msm_gpu_devfreq.c
@@ -41,6 +41,8 @@ static int msm_devfreq_target(struct device *dev, unsigned long *freq,
 
 	trace_msm_gpu_freq_change(dev_pm_opp_get_freq(opp));
 
+	if (*freq != clk_get_rate(gpu->core_clk))
+		dev_info(dev, "GPU setting to %ld\n", *freq);
 	if (gpu->funcs->gpu_set_freq)
 		gpu->funcs->gpu_set_freq(gpu, opp);
 	else
@@ -132,7 +134,7 @@ void msm_devfreq_init(struct msm_gpu *gpu)
 	msm_devfreq_profile.max_state = 0;
 
 	gpu->devfreq.devfreq = devm_devfreq_add_device(&gpu->pdev->dev,
-			&msm_devfreq_profile, DEVFREQ_GOV_SIMPLE_ONDEMAND,
+			&msm_devfreq_profile, DEVFREQ_GOV_PERFORMANCE,
 			&gpu_data);
 
 	if (IS_ERR(gpu->devfreq.devfreq)) {
@@ -173,41 +175,11 @@ void msm_devfreq_suspend(struct msm_gpu *gpu)
 void msm_devfreq_active(struct msm_gpu *gpu)
 {
 	struct msm_gpu_devfreq *df = &gpu->devfreq;
-	struct devfreq_dev_status status;
-	unsigned int idle_time;
-	unsigned long target_freq = df->idle_freq;
 
 	if (!df->devfreq)
 		return;
 
-	/*
-	 * Hold devfreq lock to synchronize with get_dev_status()/
-	 * target() callbacks
-	 */
-	mutex_lock(&df->devfreq->lock);
-
-	idle_time = ktime_to_ms(ktime_sub(ktime_get(), df->idle_time));
-
-	/*
-	 * If we've been idle for a significant fraction of a polling
-	 * interval, then we won't meet the threshold of busyness for
-	 * the governor to ramp up the freq.. so give some boost
-	 */
-	if (idle_time > msm_devfreq_profile.polling_ms/2) {
-		target_freq *= 2;
-	}
-
-	df->idle_freq = 0;
-
-	msm_devfreq_target(&gpu->pdev->dev, &target_freq, 0);
-
-	/*
-	 * Reset the polling interval so we aren't inconsistent
-	 * about freq vs busy/total cycles
-	 */
-	msm_devfreq_get_dev_status_int(&gpu->pdev->dev, &status);
-
-	mutex_unlock(&df->devfreq->lock);
+	update_devfreq(df->devfreq);
 }
 
 void msm_devfreq_idle(struct msm_gpu *gpu)
