Tcwg-commits September 2019

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14312 discussions

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-lts-allyesconfig updated (1e8c0850b1f -> 317d991fa51)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-lts-allyesconfig in repository toolchain/ci/llvm-project. from 1e8c0850b1f For now, disallow lifetime-extended temporaries with non-tr [...] adds 9bc1c6ecc56 [cxx_status] Mark P0784R7 as partially complete. adds 120a5e9a745 [ARM] Cortex-M4 schedule additions adds 72b544e656b [PowerPC] Fix conditions of assert in PPCAsmPrinter adds 83476b813e2 [clang-format] Reference qualifiers in member templates cau [...] adds 8b1eeafb913 [SLP] Fix for PR31847: Assertion failed: (isLoopInvariant(O [...] adds d30093bb8a3 [DivRemPairs] Don't assert that we won't ever get expanded- [...] adds c5133606627 [MC] Emit unused undefined symbol even if its binding is not set adds eb78dea4ccd [Docs] Moves article links to new pages adds a6d9d31279c [LLVM-C][Ocaml] Add MergeFunctions and DCE pass adds aabf8cbfca8 Add test case peeking through vector concat when combining [...] adds 0e3f6591371 [X86] Add custom isel logic to match VPTERNLOG from 2 logic ops. adds 00966d1791f Don't crash if a variable with a constexpr destructor has a [...] adds 1069c019241 [X86] Remove -x86-experimental-vector-widening-legalization [...] adds 6c320b22cd2 [X86] Fix -Wunused-variable in -DLLVM_ENABLE_ASSERTIONS=off [...] adds 9a5e3d39f69 Undef the macros after their use adds 1b0ea0a12e7 [X86] Split v16i32/v8i64 bitreverse on avx512f targets with [...] adds 4006434ed1d [ELF][test] Change llvm-readobj --arm-attributes to --arch- [...] adds 34f9e98aaec [test] Change llvm-readobj --arm-attributes to --arch-speci [...] adds 317d991fa51 AMDGPU/GlobalISel: Fix select for v2s16 and/or/xor No new revisions were added by this update. Summary of changes: clang/lib/Format/TokenAnnotator.cpp | 25 +- clang/lib/Sema/SemaDeclCXX.cpp | 3 +- clang/test/SemaCXX/constant-expression-cxx2a.cpp | 9 + clang/unittests/Format/FormatTest.cpp | 68 + clang/www/cxx_status.html | 2 +- lld/test/ELF/arm-attributes.s | 6 +- lld/test/ELF/ppc64-abs64-dyn.s | 8 +- lld/test/ELF/ppc64-relocs.s | 4 +- llvm/bindings/ocaml/transforms/ipo/ipo_ocaml.c | 6 + llvm/bindings/ocaml/transforms/ipo/llvm_ipo.ml | 3 + llvm/bindings/ocaml/transforms/ipo/llvm_ipo.mli | 5 + .../transforms/scalar_opts/llvm_scalar_opts.ml | 3 + .../transforms/scalar_opts/llvm_scalar_opts.mli | 5 + .../transforms/scalar_opts/scalar_opts_ocaml.c | 5 + llvm/docs/ProgrammingDocumentation.rst | 5 + llvm/docs/Reference.rst | 24 +- llvm/docs/SubsystemDocumentation.rst | 28 +- llvm/docs/_templates/indexsidebar.html | 2 + llvm/docs/index.rst | 3 - llvm/include/llvm-c/Transforms/IPO.h | 3 + llvm/include/llvm-c/Transforms/Scalar.h | 3 + llvm/include/llvm/MC/MCLinkerOptimizationHint.h | 2 + .../llvm/Transforms/Vectorize/SLPVectorizer.h | 9 +- llvm/lib/MC/ELFObjectWriter.cpp | 3 - llvm/lib/Target/AMDGPU/VOP2Instructions.td | 32 +- llvm/lib/Target/ARM/ARMInstrFormats.td | 1 + llvm/lib/Target/ARM/ARMInstrInfo.td | 18 +- llvm/lib/Target/ARM/ARMInstrThumb2.td | 3 +- llvm/lib/Target/ARM/ARMInstrVFP.td | 11 +- llvm/lib/Target/ARM/ARMScheduleM4.td | 24 +- llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp | 2 +- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp | 80 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 1330 +++----------------- llvm/lib/Target/X86/X86TargetTransformInfo.cpp | 86 +- llvm/lib/Transforms/IPO/IPO.cpp | 4 + llvm/lib/Transforms/Scalar/DivRemPairs.cpp | 2 - llvm/lib/Transforms/Scalar/Scalar.cpp | 4 + llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp | 152 ++- .../CodeGen/AMDGPU/GlobalISel/inst-select-and.mir | 30 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-or.mir | 30 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-xor.mir | 30 +- .../CodeGen/ARM/ParallelDSP/complex_dot_prod.ll | 6 +- .../CodeGen/ARM/ParallelDSP/multi-use-loads.ll | 52 +- .../CodeGen/ARM/ParallelDSP/unroll-n-jam-smlad.ll | 1 - .../ARM/build-attributes-optimization-minsize.ll | 6 +- .../ARM/build-attributes-optimization-mixed.ll | 6 +- .../ARM/build-attributes-optimization-optnone.ll | 6 +- .../ARM/build-attributes-optimization-optsize.ll | 6 +- .../CodeGen/ARM/build-attributes-optimization.ll | 6 +- llvm/test/CodeGen/X86/avx512-cvt.ll | 17 +- llvm/test/CodeGen/X86/avx512-gfni-intrinsics.ll | 144 +-- llvm/test/CodeGen/X86/machine-combiner-int-vec.ll | 117 +- llvm/test/CodeGen/X86/midpoint-int-vec-128.ll | 12 +- llvm/test/CodeGen/X86/midpoint-int-vec-256.ll | 24 +- llvm/test/CodeGen/X86/midpoint-int-vec-512.ll | 84 +- llvm/test/CodeGen/X86/sadd_sat_vec.ll | 57 +- llvm/test/CodeGen/X86/ssub_sat_vec.ll | 57 +- llvm/test/CodeGen/X86/vec_int_to_fp.ll | 16 +- llvm/test/CodeGen/X86/vector-bitreverse.ll | 100 +- llvm/test/CodeGen/X86/vector-fshl-256.ll | 9 +- llvm/test/CodeGen/X86/vector-fshl-512.ll | 56 +- llvm/test/CodeGen/X86/vector-fshl-rot-256.ll | 20 +- llvm/test/CodeGen/X86/vector-fshl-rot-512.ll | 42 +- llvm/test/CodeGen/X86/vector-fshr-256.ll | 29 +- llvm/test/CodeGen/X86/vector-fshr-512.ll | 154 ++- llvm/test/CodeGen/X86/vector-fshr-rot-256.ll | 20 +- llvm/test/CodeGen/X86/vector-fshr-rot-512.ll | 82 +- llvm/test/CodeGen/X86/vector-idiv-sdiv-512.ll | 6 +- llvm/test/CodeGen/X86/vector-rotate-128.ll | 77 +- llvm/test/CodeGen/X86/vector-rotate-256.ll | 69 +- llvm/test/CodeGen/X86/vector-rotate-512.ll | 92 +- llvm/test/CodeGen/X86/vector-shift-ashr-128.ll | 3 +- llvm/test/CodeGen/X86/vector-shift-ashr-256.ll | 18 +- llvm/test/CodeGen/X86/vector-shift-ashr-512.ll | 18 +- llvm/test/CodeGen/X86/vector-shift-ashr-sub128.ll | 9 +- llvm/test/CodeGen/X86/vector-shuffle-combining.ll | 71 ++ llvm/test/MC/ARM/directive-arch-armv2.s | 2 +- llvm/test/MC/ARM/directive-arch-armv2a.s | 2 +- llvm/test/MC/ARM/directive-arch-armv3.s | 2 +- llvm/test/MC/ARM/directive-arch-armv3m.s | 2 +- llvm/test/MC/ARM/directive-arch-armv4.s | 2 +- llvm/test/MC/ARM/directive-arch-armv4t.s | 2 +- llvm/test/MC/ARM/directive-arch-armv5.s | 2 +- llvm/test/MC/ARM/directive-arch-armv5t.s | 2 +- llvm/test/MC/ARM/directive-arch-armv5te.s | 2 +- llvm/test/MC/ARM/directive-arch-armv6-m.s | 2 +- llvm/test/MC/ARM/directive-arch-armv6.s | 2 +- llvm/test/MC/ARM/directive-arch-armv6k.s | 2 +- llvm/test/MC/ARM/directive-arch-armv6t2.s | 2 +- llvm/test/MC/ARM/directive-arch-armv6z.s | 2 +- llvm/test/MC/ARM/directive-arch-armv7-a.s | 2 +- llvm/test/MC/ARM/directive-arch-armv7-m.s | 2 +- llvm/test/MC/ARM/directive-arch-armv7-r.s | 2 +- llvm/test/MC/ARM/directive-arch-armv7.s | 2 +- llvm/test/MC/ARM/directive-arch-armv7a.s | 2 +- llvm/test/MC/ARM/directive-arch-armv7e-m.s | 2 +- llvm/test/MC/ARM/directive-arch-armv7em.s | 2 +- llvm/test/MC/ARM/directive-arch-armv7m.s | 2 +- llvm/test/MC/ARM/directive-arch-armv7r.s | 2 +- llvm/test/MC/ARM/directive-arch-armv8-a.s | 2 +- llvm/test/MC/ARM/directive-arch-armv8.2-a.s | 2 +- llvm/test/MC/ARM/directive-arch-armv8a.s | 2 +- llvm/test/MC/ARM/directive-arch-iwmmxt.s | 2 +- llvm/test/MC/ARM/directive-arch-iwmmxt2.s | 2 +- .../MC/ARM/directive-eabi_attribute-overwrite.s | 2 +- llvm/test/MC/ARM/directive-eabi_attribute.s | 2 +- llvm/test/MC/ARM/directive-fpu-multiple.s | 2 +- llvm/test/MC/ARM/directive-object_arch-2.s | 2 +- llvm/test/MC/ARM/directive-object_arch.s | 2 +- llvm/test/MC/ELF/undef.s | 22 + llvm/test/MC/ELF/weakref.s | 9 + .../DivRemPairs/X86/div-expanded-rem-pair.ll | 36 + .../SLPVectorizer/AArch64/gather-root.ll | 102 +- .../Transforms/SLPVectorizer/AArch64/horizontal.ll | 16 - .../SLPVectorizer/AArch64/spillcost-di.ll | 4 +- llvm/test/Transforms/SLPVectorizer/X86/PR31847.ll | 153 +++ .../test/Transforms/SLPVectorizer/X86/PR35628_1.ll | 13 +- .../test/Transforms/SLPVectorizer/X86/PR35628_2.ll | 5 - llvm/test/Transforms/SLPVectorizer/X86/PR39774.ll | 72 +- llvm/test/Transforms/SLPVectorizer/X86/PR40310.ll | 16 - .../Transforms/SLPVectorizer/X86/bad-reduction.ll | 28 - .../SLPVectorizer/X86/horizontal-list.ll | 354 +----- .../SLPVectorizer/X86/horizontal-minmax.ll | 476 ++----- .../Transforms/SLPVectorizer/X86/horizontal.ll | 148 --- .../Transforms/SLPVectorizer/X86/long_chains.ll | 8 +- .../SLPVectorizer/X86/reassociated-loads.ll | 31 - .../SLPVectorizer/X86/reduction_loads.ll | 24 - .../SLPVectorizer/X86/reduction_unrolled.ll | 35 +- .../Transforms/SLPVectorizer/X86/remark_horcost.ll | 4 - .../SLPVectorizer/X86/reorder_repeated_ops.ll | 22 - .../Transforms/SLPVectorizer/X86/undef_vect.ll | 10 - .../SLPVectorizer/X86/used-reduced-op.ll | 529 ++++++++ .../SLPVectorizer/X86/vectorize-reorder-reuse.ll | 42 - 133 files changed, 2370 insertions(+), 3420 deletions(-) create mode 100644 llvm/test/Transforms/SLPVectorizer/X86/PR31847.ll create mode 100644 llvm/test/Transforms/SLPVectorizer/X86/used-reduced-op.ll -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-lts-allyesconfig updated (d3d81a9a -> 7dbf2bb1)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-lts-allyesconfig in repository toolchain/ci/base-artifacts. discards d3d81a9a 0: update: llvm-linux: 16 new 7dbf2bb1 0: update: llvm-linux: 16 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (d3d81a9a) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-master-arm-l [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 162 +- 02-build_llvm/console.log | 12212 ++++++++++++++++++------------------ 03-build_linux/console.log | 836 +-- console.log | 13210 +++++++++++++++++++-------------------- jenkins/manifest.sh | 8 +- 5 files changed, 13214 insertions(+), 13214 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-next-allyesconfig updated (8ee0996558f -> ed76597323f)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-next-allyesconfig in repository toolchain/ci/gcc. from 8ee0996558f 2019-09-28 Jerry DeLisle <jvdelisle(a)gcc.ngu.org> adds 49f75e008c0 This patch is to add the support for float from/to long con [...] adds 56f22142aba gcc/ChangeLog adds e9eb6ea5605 PR bootstrap/90543 * optc-save-gen.awk: Fix up printing s [...] adds e020479cd65 2019-09-29 Paul Thomas <pault(a)gcc.gnu.org> adds a3310563550 2019-09-29 Steven G. Kargl <kargl(a)gcc.gnu.org> adds 0c7c01cf936 [Darwin, PPC, Mode Iterators 5/n] Update macho_low. adds ef6064d4ff4 2019-09-29 Steven G. Kargl <kargl(a)gcc.gnu.org> adds ed76597323f Daily bump. No new revisions were added by this update. Summary of changes: gcc/ChangeLog | 26 +++++++++++++ gcc/DATESTAMP | 2 +- gcc/config/darwin.c | 4 +- gcc/config/rs6000/darwin.md | 29 ++------------ gcc/config/rs6000/rs6000.c | 8 +++- gcc/config/rs6000/vsx.md | 45 ++++++++++++++++++++++ gcc/fortran/ChangeLog | 30 ++++++++++++++- gcc/fortran/check.c | 9 ++++- gcc/fortran/decl.c | 22 ++++++++++- gcc/fortran/resolve.c | 4 ++ gcc/fortran/trans-array.c | 3 +- gcc/fortran/trans-expr.c | 23 +++++++++-- gcc/fortran/trans-stmt.c | 36 +++++++++++++++++ gcc/fortran/trans.h | 1 + gcc/optc-save-gen.awk | 2 +- gcc/testsuite/ChangeLog | 21 ++++++++++ .../gcc.target/powerpc/conv-vectorize-1.c | 37 ++++++++++++++++++ .../gcc.target/powerpc/conv-vectorize-2.c | 37 ++++++++++++++++++ gcc/testsuite/gfortran.dg/coarray_poly_9.f90 | 38 ++++++++++++++++++ gcc/testsuite/gfortran.dg/dec_type_print_3.f90 | 4 +- gcc/testsuite/gfortran.dg/pr91641.f90 | 7 ++++ gcc/testsuite/gfortran.dg/pr91714.f90 | 10 +++++ 22 files changed, 357 insertions(+), 41 deletions(-) create mode 100644 gcc/testsuite/gcc.target/powerpc/conv-vectorize-1.c create mode 100644 gcc/testsuite/gcc.target/powerpc/conv-vectorize-2.c create mode 100644 gcc/testsuite/gfortran.dg/coarray_poly_9.f90 create mode 100644 gcc/testsuite/gfortran.dg/pr91641.f90 create mode 100644 gcc/testsuite/gfortran.dg/pr91714.f90 -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-next-allyesconfig updated (e6ae6cb0 -> c3901a4b)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-next-allyesconfig in repository toolchain/ci/base-artifacts. discards e6ae6cb0 2: update: binutils-663f67df1e8a7ac0ab8c8c577817067ca32ea4be: 18087 new c3901a4b 2: update: gcc-ed76597323f2005730596f3a85583691621aa616: 18087 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (e6ae6cb0) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-master-arm-ne [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 220 +- 02-prepare_abe/console.log | 428 +- 03-build_abe-binutils/console.log | 11077 ++++++------ 04-build_abe-stage1/console.log | 19848 ++++++++++----------- 05-build_linux/console.log | 1956 +-- 07-check_regression/console.log | 8 +- 08-update_baseline/console.log | 22 +- console.log | 33193 ++++++++++++++++++------------------ jenkins/manifest.sh | 8 +- 9 files changed, 33357 insertions(+), 33403 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[toolchain/ci/linux] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-mainline-allnoconfig updated (02dc96ef6c25 -> 97f9a3c4eee5)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-mainline-allnoconfig in repository toolchain/ci/linux. from 02dc96ef6c25 Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net adds 34c0989c0531 iommu/amd: Fix pages leak in free_pagetable() adds 6ccb72f8374e iommu/amd: Fix downgrading default page-sizes in alloc_pte() adds 7f1f1683c1e2 iommu/amd: Introduce first_pte_l7() helper adds cc449541f2a8 iommu/amd: Unmap all L7 PTEs when downgrading page-sizes adds 0b15e02f0cc4 iommu/amd: Wait for completion of IOTLB flush in attach_device adds f15d9a992f90 iommu/amd: Remove domain->updated adds 3a11905b69eb iommu/amd: Remove amd_iommu_devtable_lock adds f6c0bfce271b iommu/amd: Take domain->lock for complete attach/detach path adds 45e528d9c479 iommu/amd: Check for busy devices earlier in attach_device() adds ab7b2577f0d1 iommu/amd: Lock dev_data in attach/detach code paths adds 2a78f9962565 iommu/amd: Lock code paths traversing protection_domain->dev_list adds 4d2af08ed08c Merge tag 'iommu-fixes-5.4-rc1' of git://git.kernel.org/pu [...] adds 127068abe85b i2c: qcom-geni: Disable DMA processing on the Lenovo Yoga C630 adds a71e2ac1f320 i2c: riic: Clear NACK in tend isr adds fd4b204a0971 i2c: i801: Bring back Block Process Call support for certa [...] adds 11af27f49408 i2c: slave-eeprom: Add read only mode adds 9ecb3e10a9f2 Merge branch 'i2c/for-next' of git://git.kernel.org/pub/sc [...] adds dd89d82e7514 thermal: thermal_mmio: remove some dead code adds cb063a83ca32 thermal: db8500: Finalize device tree conversion adds 3de9e4dff889 thermal: db8500: Use dev helper variable adds 6c375eccded4 thermal: db8500: Rewrite to be a pure OF sensor adds 939ca9f1751d Merge branch 'linus' of git://git.kernel.org/pub/scm/linux [...] adds a6f197f889ce powerpc/book3s64: Export has_transparent_hugepage() relate [...] adds f537669978a7 libnvdimm/dax: Pick the right alignment default when creat [...] adds 86aa66687442 libnvdimm: Fix endian conversion issues adds cf387d9644d8 libnvdimm/altmap: Track namespace boundaries in altmap adds 59f08896f058 libnvdimm/nfit_test: Fix acpi_handle redefinition adds c42adf87e4e7 libnvdimm/region: Initialize bad block for volatile namespaces adds 674f31a352da libnvdimm: prevent nvdimm from requesting key when securit [...] adds 4c806b897d60 libnvdimm/region: Enable MAP_SYNC for volatile regions adds a3c0e7b1fe1f Merge tag 'libnvdimm-fixes-5.4-rc1' of git://git.kernel.or [...] adds 50ee7529ec45 random: try to actively add entropy rather than passively [...] adds 02f03c4206c1 Revert "Revert "ext4: make __ext4_get_inode_loc plug"" adds 3f2dc2798b81 Merge branch 'entropy' adds 7e7db86c7e10 smb3: allow decryption keys to be dumped by admin for debugging adds d2f15428d6a0 smb3: fix leak in "open on server" perf counter adds 388962e8e9ce fs/cifs/smb2pdu.c: Make SMB2_notify_init static adds 8559ad8e8918 fs/cifs/sess.c: Remove set but not used variable 'capabilities' adds 63d37fb4ce5a CIFS: fix max ea value size adds 131ea1ed3322 smb3: Add missing reparse tags adds c3ca78e21744 smb3: pass mode bits into create calls adds ff3ee62a5586 smb3: missing ACL related flags adds a016e2794fc3 CIFS: Fix oplock handling for SMB 2.1+ protocols adds 7edee5229c8f Merge tag '5.4-rc-smb3-fixes' of git://git.samba.org/sfren [...] adds a92c7ba982e3 fs/handle.c - fix up kerneldoc adds 473ef57ad8ed afs dynroot: switch to simple_dir_operations adds 1eb80d6ffb17 Merge branch 'work.misc' of git://git.kernel.org/pub/scm/l [...] adds 38c7a30a9d5f Documentation/process: Volunteer as the ambassador for Intel adds dc925a36060e Documentation/process: Clarify disclosure rules adds 97f9a3c4eee5 Merge tag 'char-misc-5.4-rc1' of git://git.kernel.org/pub/ [...] No new revisions were added by this update. Summary of changes: .../process/embargoed-hardware-issues.rst | 42 +- arch/powerpc/include/asm/book3s/64/radix.h | 8 +- arch/powerpc/mm/book3s64/hash_pgtable.c | 2 + arch/powerpc/mm/book3s64/radix_pgtable.c | 7 - arch/powerpc/mm/init_64.c | 17 +- drivers/char/random.c | 62 ++- drivers/i2c/busses/i2c-i801.c | 1 + drivers/i2c/busses/i2c-qcom-geni.c | 12 +- drivers/i2c/busses/i2c-riic.c | 1 + drivers/i2c/i2c-slave-eeprom.c | 14 +- drivers/iommu/amd_iommu.c | 229 ++++++---- drivers/iommu/amd_iommu_types.h | 4 +- drivers/mfd/db8500-prcmu.c | 53 +-- drivers/nvdimm/btt.c | 8 +- drivers/nvdimm/bus.c | 2 +- drivers/nvdimm/namespace_devs.c | 7 +- drivers/nvdimm/nd.h | 6 +- drivers/nvdimm/pfn_devs.c | 77 +++- drivers/nvdimm/region.c | 4 +- drivers/nvdimm/region_devs.c | 7 +- drivers/nvdimm/security.c | 4 + drivers/thermal/Kconfig | 2 +- drivers/thermal/db8500_thermal.c | 486 +++++---------------- drivers/thermal/thermal_mmio.c | 7 - fs/afs/dynroot.c | 7 - fs/afs/inode.c | 2 +- fs/afs/internal.h | 1 - fs/cifs/cifs_ioctl.h | 9 + fs/cifs/cifsacl.h | 81 +++- fs/cifs/cifsglob.h | 6 +- fs/cifs/cifsproto.h | 3 +- fs/cifs/cifssmb.c | 3 +- fs/cifs/inode.c | 3 +- fs/cifs/ioctl.c | 29 ++ fs/cifs/sess.c | 3 +- fs/cifs/smb2inode.c | 34 +- fs/cifs/smb2ops.c | 10 + fs/cifs/smb2pdu.c | 23 +- fs/cifs/smb2proto.h | 3 +- fs/cifs/smbfsctl.h | 11 + fs/cifs/xattr.c | 2 +- fs/ext4/inode.c | 3 + fs/fhandle.c | 2 +- include/linux/huge_mm.h | 7 +- include/linux/memremap.h | 1 + include/linux/platform_data/db8500_thermal.h | 29 -- tools/testing/nvdimm/test/nfit_test.h | 4 +- 47 files changed, 678 insertions(+), 660 deletions(-) delete mode 100644 include/linux/platform_data/db8500_thermal.h -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-mainline-allnoconfig updated (1e8c0850b1f -> 5951e3f8134)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-mainline-allnoconfig in repository toolchain/ci/llvm-project. from 1e8c0850b1f For now, disallow lifetime-extended temporaries with non-tr [...] adds 9bc1c6ecc56 [cxx_status] Mark P0784R7 as partially complete. adds 120a5e9a745 [ARM] Cortex-M4 schedule additions adds 72b544e656b [PowerPC] Fix conditions of assert in PPCAsmPrinter adds 83476b813e2 [clang-format] Reference qualifiers in member templates cau [...] adds 8b1eeafb913 [SLP] Fix for PR31847: Assertion failed: (isLoopInvariant(O [...] adds d30093bb8a3 [DivRemPairs] Don't assert that we won't ever get expanded- [...] adds c5133606627 [MC] Emit unused undefined symbol even if its binding is not set adds eb78dea4ccd [Docs] Moves article links to new pages adds a6d9d31279c [LLVM-C][Ocaml] Add MergeFunctions and DCE pass adds aabf8cbfca8 Add test case peeking through vector concat when combining [...] adds 0e3f6591371 [X86] Add custom isel logic to match VPTERNLOG from 2 logic ops. adds 00966d1791f Don't crash if a variable with a constexpr destructor has a [...] adds 1069c019241 [X86] Remove -x86-experimental-vector-widening-legalization [...] adds 6c320b22cd2 [X86] Fix -Wunused-variable in -DLLVM_ENABLE_ASSERTIONS=off [...] adds 9a5e3d39f69 Undef the macros after their use adds 1b0ea0a12e7 [X86] Split v16i32/v8i64 bitreverse on avx512f targets with [...] adds 4006434ed1d [ELF][test] Change llvm-readobj --arm-attributes to --arch- [...] adds 34f9e98aaec [test] Change llvm-readobj --arm-attributes to --arch-speci [...] new 317d991fa51 AMDGPU/GlobalISel: Fix select for v2s16 and/or/xor new 5951e3f8134 [X86] Remove some redundant isel patterns. NFCI The 2 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: clang/lib/Format/TokenAnnotator.cpp | 25 +- clang/lib/Sema/SemaDeclCXX.cpp | 3 +- clang/test/SemaCXX/constant-expression-cxx2a.cpp | 9 + clang/unittests/Format/FormatTest.cpp | 68 + clang/www/cxx_status.html | 2 +- lld/test/ELF/arm-attributes.s | 6 +- lld/test/ELF/ppc64-abs64-dyn.s | 8 +- lld/test/ELF/ppc64-relocs.s | 4 +- llvm/bindings/ocaml/transforms/ipo/ipo_ocaml.c | 6 + llvm/bindings/ocaml/transforms/ipo/llvm_ipo.ml | 3 + llvm/bindings/ocaml/transforms/ipo/llvm_ipo.mli | 5 + .../transforms/scalar_opts/llvm_scalar_opts.ml | 3 + .../transforms/scalar_opts/llvm_scalar_opts.mli | 5 + .../transforms/scalar_opts/scalar_opts_ocaml.c | 5 + llvm/docs/ProgrammingDocumentation.rst | 5 + llvm/docs/Reference.rst | 24 +- llvm/docs/SubsystemDocumentation.rst | 28 +- llvm/docs/_templates/indexsidebar.html | 2 + llvm/docs/index.rst | 3 - llvm/include/llvm-c/Transforms/IPO.h | 3 + llvm/include/llvm-c/Transforms/Scalar.h | 3 + llvm/include/llvm/MC/MCLinkerOptimizationHint.h | 2 + .../llvm/Transforms/Vectorize/SLPVectorizer.h | 9 +- llvm/lib/MC/ELFObjectWriter.cpp | 3 - llvm/lib/Target/AMDGPU/VOP2Instructions.td | 32 +- llvm/lib/Target/ARM/ARMInstrFormats.td | 1 + llvm/lib/Target/ARM/ARMInstrInfo.td | 18 +- llvm/lib/Target/ARM/ARMInstrThumb2.td | 3 +- llvm/lib/Target/ARM/ARMInstrVFP.td | 11 +- llvm/lib/Target/ARM/ARMScheduleM4.td | 24 +- llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp | 2 +- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp | 80 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 1330 +++----------------- llvm/lib/Target/X86/X86InstrAVX512.td | 78 -- llvm/lib/Target/X86/X86TargetTransformInfo.cpp | 86 +- llvm/lib/Transforms/IPO/IPO.cpp | 4 + llvm/lib/Transforms/Scalar/DivRemPairs.cpp | 2 - llvm/lib/Transforms/Scalar/Scalar.cpp | 4 + llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp | 152 ++- .../CodeGen/AMDGPU/GlobalISel/inst-select-and.mir | 30 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-or.mir | 30 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-xor.mir | 30 +- .../CodeGen/ARM/ParallelDSP/complex_dot_prod.ll | 6 +- .../CodeGen/ARM/ParallelDSP/multi-use-loads.ll | 52 +- .../CodeGen/ARM/ParallelDSP/unroll-n-jam-smlad.ll | 1 - .../ARM/build-attributes-optimization-minsize.ll | 6 +- .../ARM/build-attributes-optimization-mixed.ll | 6 +- .../ARM/build-attributes-optimization-optnone.ll | 6 +- .../ARM/build-attributes-optimization-optsize.ll | 6 +- .../CodeGen/ARM/build-attributes-optimization.ll | 6 +- llvm/test/CodeGen/X86/avx512-cvt.ll | 17 +- llvm/test/CodeGen/X86/avx512-gfni-intrinsics.ll | 144 +-- llvm/test/CodeGen/X86/machine-combiner-int-vec.ll | 117 +- llvm/test/CodeGen/X86/midpoint-int-vec-128.ll | 12 +- llvm/test/CodeGen/X86/midpoint-int-vec-256.ll | 24 +- llvm/test/CodeGen/X86/midpoint-int-vec-512.ll | 84 +- llvm/test/CodeGen/X86/sadd_sat_vec.ll | 57 +- llvm/test/CodeGen/X86/ssub_sat_vec.ll | 57 +- llvm/test/CodeGen/X86/vec_int_to_fp.ll | 16 +- llvm/test/CodeGen/X86/vector-bitreverse.ll | 100 +- llvm/test/CodeGen/X86/vector-fshl-256.ll | 9 +- llvm/test/CodeGen/X86/vector-fshl-512.ll | 56 +- llvm/test/CodeGen/X86/vector-fshl-rot-256.ll | 20 +- llvm/test/CodeGen/X86/vector-fshl-rot-512.ll | 42 +- llvm/test/CodeGen/X86/vector-fshr-256.ll | 29 +- llvm/test/CodeGen/X86/vector-fshr-512.ll | 154 ++- llvm/test/CodeGen/X86/vector-fshr-rot-256.ll | 20 +- llvm/test/CodeGen/X86/vector-fshr-rot-512.ll | 82 +- llvm/test/CodeGen/X86/vector-idiv-sdiv-512.ll | 6 +- llvm/test/CodeGen/X86/vector-rotate-128.ll | 77 +- llvm/test/CodeGen/X86/vector-rotate-256.ll | 69 +- llvm/test/CodeGen/X86/vector-rotate-512.ll | 92 +- llvm/test/CodeGen/X86/vector-shift-ashr-128.ll | 3 +- llvm/test/CodeGen/X86/vector-shift-ashr-256.ll | 18 +- llvm/test/CodeGen/X86/vector-shift-ashr-512.ll | 18 +- llvm/test/CodeGen/X86/vector-shift-ashr-sub128.ll | 9 +- llvm/test/CodeGen/X86/vector-shuffle-combining.ll | 71 ++ llvm/test/MC/ARM/directive-arch-armv2.s | 2 +- llvm/test/MC/ARM/directive-arch-armv2a.s | 2 +- llvm/test/MC/ARM/directive-arch-armv3.s | 2 +- llvm/test/MC/ARM/directive-arch-armv3m.s | 2 +- llvm/test/MC/ARM/directive-arch-armv4.s | 2 +- llvm/test/MC/ARM/directive-arch-armv4t.s | 2 +- llvm/test/MC/ARM/directive-arch-armv5.s | 2 +- llvm/test/MC/ARM/directive-arch-armv5t.s | 2 +- llvm/test/MC/ARM/directive-arch-armv5te.s | 2 +- llvm/test/MC/ARM/directive-arch-armv6-m.s | 2 +- llvm/test/MC/ARM/directive-arch-armv6.s | 2 +- llvm/test/MC/ARM/directive-arch-armv6k.s | 2 +- llvm/test/MC/ARM/directive-arch-armv6t2.s | 2 +- llvm/test/MC/ARM/directive-arch-armv6z.s | 2 +- llvm/test/MC/ARM/directive-arch-armv7-a.s | 2 +- llvm/test/MC/ARM/directive-arch-armv7-m.s | 2 +- llvm/test/MC/ARM/directive-arch-armv7-r.s | 2 +- llvm/test/MC/ARM/directive-arch-armv7.s | 2 +- llvm/test/MC/ARM/directive-arch-armv7a.s | 2 +- llvm/test/MC/ARM/directive-arch-armv7e-m.s | 2 +- llvm/test/MC/ARM/directive-arch-armv7em.s | 2 +- llvm/test/MC/ARM/directive-arch-armv7m.s | 2 +- llvm/test/MC/ARM/directive-arch-armv7r.s | 2 +- llvm/test/MC/ARM/directive-arch-armv8-a.s | 2 +- llvm/test/MC/ARM/directive-arch-armv8.2-a.s | 2 +- llvm/test/MC/ARM/directive-arch-armv8a.s | 2 +- llvm/test/MC/ARM/directive-arch-iwmmxt.s | 2 +- llvm/test/MC/ARM/directive-arch-iwmmxt2.s | 2 +- .../MC/ARM/directive-eabi_attribute-overwrite.s | 2 +- llvm/test/MC/ARM/directive-eabi_attribute.s | 2 +- llvm/test/MC/ARM/directive-fpu-multiple.s | 2 +- llvm/test/MC/ARM/directive-object_arch-2.s | 2 +- llvm/test/MC/ARM/directive-object_arch.s | 2 +- llvm/test/MC/ELF/undef.s | 22 + llvm/test/MC/ELF/weakref.s | 9 + .../DivRemPairs/X86/div-expanded-rem-pair.ll | 36 + .../SLPVectorizer/AArch64/gather-root.ll | 102 +- .../Transforms/SLPVectorizer/AArch64/horizontal.ll | 16 - .../SLPVectorizer/AArch64/spillcost-di.ll | 4 +- llvm/test/Transforms/SLPVectorizer/X86/PR31847.ll | 153 +++ .../test/Transforms/SLPVectorizer/X86/PR35628_1.ll | 13 +- .../test/Transforms/SLPVectorizer/X86/PR35628_2.ll | 5 - llvm/test/Transforms/SLPVectorizer/X86/PR39774.ll | 72 +- llvm/test/Transforms/SLPVectorizer/X86/PR40310.ll | 16 - .../Transforms/SLPVectorizer/X86/bad-reduction.ll | 28 - .../SLPVectorizer/X86/horizontal-list.ll | 354 +----- .../SLPVectorizer/X86/horizontal-minmax.ll | 476 ++----- .../Transforms/SLPVectorizer/X86/horizontal.ll | 148 --- .../Transforms/SLPVectorizer/X86/long_chains.ll | 8 +- .../SLPVectorizer/X86/reassociated-loads.ll | 31 - .../SLPVectorizer/X86/reduction_loads.ll | 24 - .../SLPVectorizer/X86/reduction_unrolled.ll | 35 +- .../Transforms/SLPVectorizer/X86/remark_horcost.ll | 4 - .../SLPVectorizer/X86/reorder_repeated_ops.ll | 22 - .../Transforms/SLPVectorizer/X86/undef_vect.ll | 10 - .../SLPVectorizer/X86/used-reduced-op.ll | 529 ++++++++ .../SLPVectorizer/X86/vectorize-reorder-reuse.ll | 42 - 134 files changed, 2370 insertions(+), 3498 deletions(-) create mode 100644 llvm/test/Transforms/SLPVectorizer/X86/PR31847.ll create mode 100644 llvm/test/Transforms/SLPVectorizer/X86/used-reduced-op.ll -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-mainline-allnoconfig updated (31497432 -> 4f84c0ff)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-mainline-allnoconfig in repository toolchain/ci/base-artifacts. discards 31497432 0: update: llvm-linux: boot new 4f84c0ff 0: update: llvm-linux: boot This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (31497432) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-master-aarch [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 175 +- 02-build_llvm/console.log | 12050 ++++++++++++++++++------------------ 03-build_linux/console.log | 604 +- 06-update_baseline/console.log | 25 + console.log | 12854 ++++++++++++++++++++------------------- jenkins/manifest.sh | 12 +- 6 files changed, 12894 insertions(+), 12826 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[llvm] branch master updated (fe518bfae1d -> 87ba95fdbdb)

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This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository llvm. from fe518bfae1d AMDGPU/GlobalISel: Fix select for v2s16 and/or/xor new 87ba95fdbdb [X86] Remove some redundant isel patterns. NFCI The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: lib/Target/X86/X86InstrAVX512.td | 78 ---------------------------------------- 1 file changed, 78 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[llvm] branch master updated (3383e0bc3c2 -> fe518bfae1d)

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This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository llvm. from 3383e0bc3c2 [test] Change llvm-readobj --arm-attributes to --arch-speci [...] new fe518bfae1d AMDGPU/GlobalISel: Fix select for v2s16 and/or/xor The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: lib/Target/AMDGPU/VOP2Instructions.td | 32 ++++++++++++---------- test/CodeGen/AMDGPU/GlobalISel/inst-select-and.mir | 30 ++++++++++---------- test/CodeGen/AMDGPU/GlobalISel/inst-select-or.mir | 30 ++++++++++---------- test/CodeGen/AMDGPU/GlobalISel/inst-select-xor.mir | 30 ++++++++++---------- 4 files changed, 62 insertions(+), 60 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-lts-defconfig updated (4566f87649c -> 34f9e98aaec)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-lts-defconfig in repository toolchain/ci/llvm-project. from 4566f87649c Fix checking for permitted results of constant expressions. adds 1e8c0850b1f For now, disallow lifetime-extended temporaries with non-tr [...] adds 9bc1c6ecc56 [cxx_status] Mark P0784R7 as partially complete. adds 120a5e9a745 [ARM] Cortex-M4 schedule additions adds 72b544e656b [PowerPC] Fix conditions of assert in PPCAsmPrinter adds 83476b813e2 [clang-format] Reference qualifiers in member templates cau [...] adds 8b1eeafb913 [SLP] Fix for PR31847: Assertion failed: (isLoopInvariant(O [...] adds d30093bb8a3 [DivRemPairs] Don't assert that we won't ever get expanded- [...] adds c5133606627 [MC] Emit unused undefined symbol even if its binding is not set adds eb78dea4ccd [Docs] Moves article links to new pages adds a6d9d31279c [LLVM-C][Ocaml] Add MergeFunctions and DCE pass adds aabf8cbfca8 Add test case peeking through vector concat when combining [...] adds 0e3f6591371 [X86] Add custom isel logic to match VPTERNLOG from 2 logic ops. adds 00966d1791f Don't crash if a variable with a constexpr destructor has a [...] adds 1069c019241 [X86] Remove -x86-experimental-vector-widening-legalization [...] adds 6c320b22cd2 [X86] Fix -Wunused-variable in -DLLVM_ENABLE_ASSERTIONS=off [...] adds 9a5e3d39f69 Undef the macros after their use adds 1b0ea0a12e7 [X86] Split v16i32/v8i64 bitreverse on avx512f targets with [...] adds 4006434ed1d [ELF][test] Change llvm-readobj --arm-attributes to --arch- [...] adds 34f9e98aaec [test] Change llvm-readobj --arm-attributes to --arch-speci [...] No new revisions were added by this update. Summary of changes: clang/include/clang/Basic/DiagnosticASTKinds.td | 3 + clang/lib/AST/ExprConstant.cpp | 10 +- clang/lib/Format/TokenAnnotator.cpp | 25 +- clang/lib/Sema/SemaDeclCXX.cpp | 3 +- clang/test/SemaCXX/constant-expression-cxx2a.cpp | 28 + clang/unittests/Format/FormatTest.cpp | 68 + clang/www/cxx_status.html | 2 +- lld/test/ELF/arm-attributes.s | 6 +- lld/test/ELF/ppc64-abs64-dyn.s | 8 +- lld/test/ELF/ppc64-relocs.s | 4 +- llvm/bindings/ocaml/transforms/ipo/ipo_ocaml.c | 6 + llvm/bindings/ocaml/transforms/ipo/llvm_ipo.ml | 3 + llvm/bindings/ocaml/transforms/ipo/llvm_ipo.mli | 5 + .../transforms/scalar_opts/llvm_scalar_opts.ml | 3 + .../transforms/scalar_opts/llvm_scalar_opts.mli | 5 + .../transforms/scalar_opts/scalar_opts_ocaml.c | 5 + llvm/docs/ProgrammingDocumentation.rst | 5 + llvm/docs/Reference.rst | 24 +- llvm/docs/SubsystemDocumentation.rst | 28 +- llvm/docs/_templates/indexsidebar.html | 2 + llvm/docs/index.rst | 3 - llvm/include/llvm-c/Transforms/IPO.h | 3 + llvm/include/llvm-c/Transforms/Scalar.h | 3 + llvm/include/llvm/MC/MCLinkerOptimizationHint.h | 2 + .../llvm/Transforms/Vectorize/SLPVectorizer.h | 9 +- llvm/lib/MC/ELFObjectWriter.cpp | 3 - llvm/lib/Target/ARM/ARMInstrFormats.td | 1 + llvm/lib/Target/ARM/ARMInstrInfo.td | 18 +- llvm/lib/Target/ARM/ARMInstrThumb2.td | 3 +- llvm/lib/Target/ARM/ARMInstrVFP.td | 11 +- llvm/lib/Target/ARM/ARMScheduleM4.td | 24 +- llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp | 2 +- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp | 80 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 1330 +++----------------- llvm/lib/Target/X86/X86TargetTransformInfo.cpp | 86 +- llvm/lib/Transforms/IPO/IPO.cpp | 4 + llvm/lib/Transforms/Scalar/DivRemPairs.cpp | 2 - llvm/lib/Transforms/Scalar/Scalar.cpp | 4 + llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp | 152 ++- .../CodeGen/ARM/ParallelDSP/complex_dot_prod.ll | 6 +- .../CodeGen/ARM/ParallelDSP/multi-use-loads.ll | 52 +- .../CodeGen/ARM/ParallelDSP/unroll-n-jam-smlad.ll | 1 - .../ARM/build-attributes-optimization-minsize.ll | 6 +- .../ARM/build-attributes-optimization-mixed.ll | 6 +- .../ARM/build-attributes-optimization-optnone.ll | 6 +- .../ARM/build-attributes-optimization-optsize.ll | 6 +- .../CodeGen/ARM/build-attributes-optimization.ll | 6 +- llvm/test/CodeGen/X86/avx512-cvt.ll | 17 +- llvm/test/CodeGen/X86/avx512-gfni-intrinsics.ll | 144 +-- llvm/test/CodeGen/X86/machine-combiner-int-vec.ll | 117 +- llvm/test/CodeGen/X86/midpoint-int-vec-128.ll | 12 +- llvm/test/CodeGen/X86/midpoint-int-vec-256.ll | 24 +- llvm/test/CodeGen/X86/midpoint-int-vec-512.ll | 84 +- llvm/test/CodeGen/X86/sadd_sat_vec.ll | 57 +- llvm/test/CodeGen/X86/ssub_sat_vec.ll | 57 +- llvm/test/CodeGen/X86/vec_int_to_fp.ll | 16 +- llvm/test/CodeGen/X86/vector-bitreverse.ll | 100 +- llvm/test/CodeGen/X86/vector-fshl-256.ll | 9 +- llvm/test/CodeGen/X86/vector-fshl-512.ll | 56 +- llvm/test/CodeGen/X86/vector-fshl-rot-256.ll | 20 +- llvm/test/CodeGen/X86/vector-fshl-rot-512.ll | 42 +- llvm/test/CodeGen/X86/vector-fshr-256.ll | 29 +- llvm/test/CodeGen/X86/vector-fshr-512.ll | 154 ++- llvm/test/CodeGen/X86/vector-fshr-rot-256.ll | 20 +- llvm/test/CodeGen/X86/vector-fshr-rot-512.ll | 82 +- llvm/test/CodeGen/X86/vector-idiv-sdiv-512.ll | 6 +- llvm/test/CodeGen/X86/vector-rotate-128.ll | 77 +- llvm/test/CodeGen/X86/vector-rotate-256.ll | 69 +- llvm/test/CodeGen/X86/vector-rotate-512.ll | 92 +- llvm/test/CodeGen/X86/vector-shift-ashr-128.ll | 3 +- llvm/test/CodeGen/X86/vector-shift-ashr-256.ll | 18 +- llvm/test/CodeGen/X86/vector-shift-ashr-512.ll | 18 +- llvm/test/CodeGen/X86/vector-shift-ashr-sub128.ll | 9 +- llvm/test/CodeGen/X86/vector-shuffle-combining.ll | 71 ++ llvm/test/MC/ARM/directive-arch-armv2.s | 2 +- llvm/test/MC/ARM/directive-arch-armv2a.s | 2 +- llvm/test/MC/ARM/directive-arch-armv3.s | 2 +- llvm/test/MC/ARM/directive-arch-armv3m.s | 2 +- llvm/test/MC/ARM/directive-arch-armv4.s | 2 +- llvm/test/MC/ARM/directive-arch-armv4t.s | 2 +- llvm/test/MC/ARM/directive-arch-armv5.s | 2 +- llvm/test/MC/ARM/directive-arch-armv5t.s | 2 +- llvm/test/MC/ARM/directive-arch-armv5te.s | 2 +- llvm/test/MC/ARM/directive-arch-armv6-m.s | 2 +- llvm/test/MC/ARM/directive-arch-armv6.s | 2 +- llvm/test/MC/ARM/directive-arch-armv6k.s | 2 +- llvm/test/MC/ARM/directive-arch-armv6t2.s | 2 +- llvm/test/MC/ARM/directive-arch-armv6z.s | 2 +- llvm/test/MC/ARM/directive-arch-armv7-a.s | 2 +- llvm/test/MC/ARM/directive-arch-armv7-m.s | 2 +- llvm/test/MC/ARM/directive-arch-armv7-r.s | 2 +- llvm/test/MC/ARM/directive-arch-armv7.s | 2 +- llvm/test/MC/ARM/directive-arch-armv7a.s | 2 +- llvm/test/MC/ARM/directive-arch-armv7e-m.s | 2 +- llvm/test/MC/ARM/directive-arch-armv7em.s | 2 +- llvm/test/MC/ARM/directive-arch-armv7m.s | 2 +- llvm/test/MC/ARM/directive-arch-armv7r.s | 2 +- llvm/test/MC/ARM/directive-arch-armv8-a.s | 2 +- llvm/test/MC/ARM/directive-arch-armv8.2-a.s | 2 +- llvm/test/MC/ARM/directive-arch-armv8a.s | 2 +- llvm/test/MC/ARM/directive-arch-iwmmxt.s | 2 +- llvm/test/MC/ARM/directive-arch-iwmmxt2.s | 2 +- .../MC/ARM/directive-eabi_attribute-overwrite.s | 2 +- llvm/test/MC/ARM/directive-eabi_attribute.s | 2 +- llvm/test/MC/ARM/directive-fpu-multiple.s | 2 +- llvm/test/MC/ARM/directive-object_arch-2.s | 2 +- llvm/test/MC/ARM/directive-object_arch.s | 2 +- llvm/test/MC/ELF/undef.s | 22 + llvm/test/MC/ELF/weakref.s | 9 + .../DivRemPairs/X86/div-expanded-rem-pair.ll | 36 + .../SLPVectorizer/AArch64/gather-root.ll | 102 +- .../Transforms/SLPVectorizer/AArch64/horizontal.ll | 16 - .../SLPVectorizer/AArch64/spillcost-di.ll | 4 +- llvm/test/Transforms/SLPVectorizer/X86/PR31847.ll | 153 +++ .../test/Transforms/SLPVectorizer/X86/PR35628_1.ll | 13 +- .../test/Transforms/SLPVectorizer/X86/PR35628_2.ll | 5 - llvm/test/Transforms/SLPVectorizer/X86/PR39774.ll | 72 +- llvm/test/Transforms/SLPVectorizer/X86/PR40310.ll | 16 - .../Transforms/SLPVectorizer/X86/bad-reduction.ll | 28 - .../SLPVectorizer/X86/horizontal-list.ll | 354 +----- .../SLPVectorizer/X86/horizontal-minmax.ll | 476 ++----- .../Transforms/SLPVectorizer/X86/horizontal.ll | 148 --- .../Transforms/SLPVectorizer/X86/long_chains.ll | 8 +- .../SLPVectorizer/X86/reassociated-loads.ll | 31 - .../SLPVectorizer/X86/reduction_loads.ll | 24 - .../SLPVectorizer/X86/reduction_unrolled.ll | 35 +- .../Transforms/SLPVectorizer/X86/remark_horcost.ll | 4 - .../SLPVectorizer/X86/reorder_repeated_ops.ll | 22 - .../Transforms/SLPVectorizer/X86/undef_vect.ll | 10 - .../SLPVectorizer/X86/used-reduced-op.ll | 529 ++++++++ .../SLPVectorizer/X86/vectorize-reorder-reuse.ll | 42 - 131 files changed, 2339 insertions(+), 3361 deletions(-) create mode 100644 llvm/test/Transforms/SLPVectorizer/X86/PR31847.ll create mode 100644 llvm/test/Transforms/SLPVectorizer/X86/used-reduced-op.ll -- To stop receiving notification emails like this one, please contact the administrator of this repository.

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Tcwg-commits September 2019