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from a5a2cc99fb0 gn build: Merge r372282 new 1d003d31da7 GlobalISel: Don't materialize immarg arguments to intrinsics
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Summary of changes: .../llvm/CodeGen/GlobalISel/InstructionSelector.h | 5 + .../CodeGen/GlobalISel/InstructionSelectorImpl.h | 14 +- include/llvm/Target/TargetSelectionDAG.td | 5 + lib/CodeGen/GlobalISel/IRTranslator.cpp | 27 +- lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 18 +- lib/Target/AArch64/AArch64InstrFormats.td | 4 +- lib/Target/AArch64/AArch64InstrInfo.td | 2 +- lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp | 20 +- lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 7 - lib/Target/AMDGPU/BUFInstructions.td | 110 ++-- lib/Target/AMDGPU/DSInstructions.td | 2 +- lib/Target/AMDGPU/SIISelLowering.cpp | 104 +-- lib/Target/AMDGPU/SIInstructions.td | 12 +- lib/Target/AMDGPU/SOPInstructions.td | 14 +- lib/Target/AMDGPU/VOP1Instructions.td | 18 +- lib/Target/AMDGPU/VOP3Instructions.td | 44 +- lib/Target/ARM/ARMISelLowering.cpp | 24 +- lib/Target/ARM/ARMInstrInfo.td | 52 +- lib/Target/ARM/ARMInstrThumb2.td | 48 +- lib/Target/Hexagon/HexagonDepMapAsm2Intrin.td | 696 ++++++++++----------- lib/Target/Hexagon/HexagonDepOperands.td | 83 +-- lib/Target/Hexagon/HexagonIntrinsics.td | 46 +- lib/Target/Mips/MicroMipsDSPInstrInfo.td | 4 +- lib/Target/Mips/Mips64InstrInfo.td | 1 + lib/Target/Mips/MipsDSPInstrInfo.td | 19 +- lib/Target/Mips/MipsInstrInfo.td | 2 + lib/Target/Mips/MipsMSAInstrInfo.td | 55 +- lib/Target/Mips/MipsSEISelLowering.cpp | 3 +- lib/Target/PowerPC/PPCInstrAltivec.td | 6 +- lib/Target/PowerPC/PPCInstrVSX.td | 4 +- lib/Target/RISCV/RISCVInstrInfoA.td | 8 +- lib/Target/SystemZ/SystemZISelDAGToDAG.cpp | 6 +- lib/Target/SystemZ/SystemZISelLowering.cpp | 49 +- lib/Target/SystemZ/SystemZInstrFormats.td | 166 ++--- lib/Target/SystemZ/SystemZInstrVector.td | 18 +- lib/Target/SystemZ/SystemZOperands.td | 121 ++-- lib/Target/SystemZ/SystemZOperators.td | 6 +- lib/Target/SystemZ/SystemZPatterns.td | 4 +- lib/Target/SystemZ/SystemZSelectionDAGInfo.cpp | 8 +- .../WebAssembly/WebAssemblyInstrBulkMemory.td | 4 +- lib/Target/X86/X86ISelDAGToDAG.cpp | 12 +- lib/Target/X86/X86ISelLowering.cpp | 268 ++++---- lib/Target/X86/X86InstrAVX512.td | 224 +++---- lib/Target/X86/X86InstrMMX.td | 8 +- lib/Target/X86/X86InstrSSE.td | 204 +++--- lib/Target/X86/X86InstrSystem.td | 2 +- lib/Target/X86/X86InstrTSX.td | 2 +- lib/Target/X86/X86InstrXOP.td | 16 +- .../AArch64/GlobalISel/arm64-irtranslator.ll | 3 +- .../AMDGPU/GlobalISel/inst-select-amdgcn.exp.mir | 12 +- .../GlobalISel/inst-select-amdgcn.s.sendmsg.mir | 3 +- .../GlobalISel/irtranslator-amdgcn-sendmsg.ll | 15 + .../AMDGPU/GlobalISel/irtranslator-amdgpu_ps.ll | 12 +- .../AMDGPU/GlobalISel/irtranslator-amdgpu_vs.ll | 9 +- .../irtranslator-struct-return-intrinsics.ll | 5 +- .../AMDGPU/{ => GlobalISel}/llvm.amdgcn.s.sleep.ll | 4 +- .../AMDGPU/GlobalISel/regbankselect-amdgcn-exp.mir | 40 +- test/TableGen/immarg.td | 31 + utils/TableGen/GlobalISelEmitter.cpp | 27 +- 59 files changed, 1425 insertions(+), 1311 deletions(-) create mode 100644 test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgcn-sendmsg.ll copy test/CodeGen/AMDGPU/{ => GlobalISel}/llvm.amdgcn.s.sleep.ll (85%) create mode 100644 test/TableGen/immarg.td