This is an automated email from the git hooks/post-receive script.
unknown user pushed a change to branch master in repository gcc.
from 1fea14def84 c++: missing SFINAE in grok_array_decl [PR111493] new dc607a0d861 RISC-V: Add VLS widen binary combine patterns
The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference.
Summary of changes: gcc/config/riscv/vector-iterators.md | 44 ++++++++++++ .../gcc.target/riscv/rvv/autovec/vls/def.h | 27 ++++++++ .../gcc.target/riscv/rvv/autovec/vls/wadd-1.c | 80 ++++++++++++++++++++++ .../riscv/rvv/autovec/vls/{ext-4.c => wadd-2.c} | 33 +++++---- .../gcc.target/riscv/rvv/autovec/vls/wadd-3.c | 80 ++++++++++++++++++++++ .../riscv/rvv/autovec/vls/{ext-3.c => wadd-4.c} | 34 ++++----- .../gcc.target/riscv/rvv/autovec/vls/wmul-1.c | 80 ++++++++++++++++++++++ .../riscv/rvv/autovec/vls/{ext-4.c => wmul-2.c} | 33 +++++---- .../gcc.target/riscv/rvv/autovec/vls/wmul-3.c | 49 +++++++++++++ .../gcc.target/riscv/rvv/autovec/vls/wsub-1.c | 80 ++++++++++++++++++++++ .../riscv/rvv/autovec/vls/{fnma-2.c => wsub-2.c} | 41 +++++------ .../gcc.target/riscv/rvv/autovec/vls/wsub-3.c | 80 ++++++++++++++++++++++ .../riscv/rvv/autovec/vls/{ext-4.c => wsub-4.c} | 33 +++++---- 13 files changed, 610 insertions(+), 84 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wadd-1.c copy gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/{ext-4.c => wadd-2.c} (56%) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wadd-3.c copy gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/{ext-3.c => wadd-4.c} (56%) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wmul-1.c copy gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/{ext-4.c => wmul-2.c} (56%) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wmul-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wsub-1.c copy gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/{fnma-2.c => wsub-2.c} (56%) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wsub-3.c copy gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/{ext-4.c => wsub-4.c} (56%)