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from bfa1dc6a7ad [WebAssembly] MC: Remove unused code for handling of wasm globals new 111980697bf [MachineOutliner] Freeze registers in new functions new 097b607c720 [SeparateConstOffsetFromGEP] Preserve metadata when splitting GEPs new 45ce427076d AMDGPU: Add intrinsics llvm.amdgcn.cvt.{pknorm.i16, pknorm. [...] new e16a4c10b65 AMDGPU: Fold inline offset for loads properly in moveToVALU [...]
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Summary of changes: include/llvm/IR/IntrinsicsAMDGPU.td | 20 +++ lib/CodeGen/MachineOutliner.cpp | 2 + lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 4 + lib/Target/AMDGPU/AMDGPUISelLowering.h | 4 + lib/Target/AMDGPU/AMDGPUInstrInfo.td | 8 + lib/Target/AMDGPU/SIISelLowering.cpp | 50 ++++++- lib/Target/AMDGPU/SIInstrInfo.cpp | 53 ++++--- lib/Target/AMDGPU/VOP2Instructions.td | 8 +- lib/Transforms/InstCombine/InstCombineCalls.cpp | 12 ++ .../Scalar/SeparateConstOffsetFromGEP.cpp | 2 + test/CodeGen/AArch64/machine-outliner.mir | 2 +- test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.i16.ll | 84 +++++++++++ test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.u16.ll | 84 +++++++++++ test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pknorm.i16.ll | 164 +++++++++++++++++++++ test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pknorm.u16.ll | 164 +++++++++++++++++++++ test/CodeGen/AMDGPU/smrd.ll | 18 +-- .../InstCombine/AMDGPU/amdgcn-intrinsics.ll | 108 ++++++++++++++ ...split-gep-and-gvn-addrspace-addressing-modes.ll | 45 ++++++ 18 files changed, 786 insertions(+), 46 deletions(-) create mode 100644 test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.i16.ll create mode 100644 test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.u16.ll create mode 100644 test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pknorm.i16.ll create mode 100644 test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pknorm.u16.ll