Woodruff, Richard r-woodruff2 at
Fri Dec 10 19:25:30 UTC 2010

The underlying functional spec which TRM started from gives this description:

"In MPU filling mode, the FIFO status can be monitored through the FIFOPointer or through the FIFOThresholdStatus bits in the GPMC_PREFETCH_STATUS register.  FIFOPointer indicates the current number of available free byte places in the FIFO, and FIFOThresholdStatus, when set, indicates that at least FIFOThreshold free byte places are available in the FIFO."

There is an NDA application note about on prefetch engine which also might be useful (SWPA146 - NAND Flash usage with GPMC).

Richard W.

> -----Original Message-----
> From: linaro-dev-bounces at [mailto:linaro-dev-
> bounces at] On Behalf Of Peter Maydell
> Sent: Friday, December 10, 2010 11:06 AM
> To: linaro-dev at
> Subject: OMAP query about GPMC FIFOTHRESHOLDSTATUS bit
> Hi. I have a question about a detail in the OMAP3 TRM, which I
> was hoping some omap-savvy person on this list might be able
> to answer.
> This is about the GPMC prefetch engine register
> bit. I've been using the OMAP35xx TRM (document SPRUF98L, rev L)
> as reference.
> The register summary on page 1176 says "set when FIFOPointer
> exceeds FIFOThreshold value" and is clear that it is 1 if Pointer
> > Threshold. However the description on page 1141 says "The
> FIFOPOINTER indicates the current number of available data to be
> read; FIFOTHRESHOLDSTATUS set to 1 indicates that at least
> FIFOTHRESHOLD bytes are available from the FIFO", ie the bit is
> set if Pointer >= Threshold. The text on p1143 is similar.
> So is the bit set for Pointer > Threshold or Pointer >= Threshold?
> (Greater-than-or-equal makes more conceptual sense to me and
> would match the condition in which GPMC_IRQSTATUS's
> FIFOEVENTSTATUS bit is set.)
> (I'm looking at this because I'm implementing the prefetch engine
> in qemu.)
> thanks in advance
> -- PMM
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