Query: Multiple Mappings to Mem and ARMV6+
viresh.linux at gmail.com
Thu Feb 16 17:37:02 UTC 2012
On Thu, Feb 16, 2012 at 9:15 AM, Catalin Marinas
<catalin.marinas at arm.com> wrote:
> To summarise, if you mix Normal with Device or SO memory, you only get
> the guarantees of the Normal memory (e.g. early write acknowledgement,
> write buffer gathering, speculative accesses), so it's not recommended.
> If you mix Normal Cacheable with Normal Non-cacheable, you need to make
> sure that the cacheable mapping does not have any dirty cache lines that
> could be evicted. Additionally, if you read the buffer through the
> cacheable mapping later, you need to invalidate it first in case cache
> lines have been speculatively fetched. The ARM ARM definition however
> guarantees that accesses through the Non-cacheable mapping does not hit
> any cache lines (brought in via the Cacheable mapping).
I don't know if i understood correctly the earlier mails over the list, but with
speculative writes to Normal Cacheable Memory (Low Mem), we can still
enter an undefined state if we have separate kind of mapping as we have in
dma_alloc_*() and low mem.
Who is responsible here to take care of cleaning and invalidate cached low
mem mappings in case of speculative writes?
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