Acc January 2025

acc@lists.linaro.org

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3 discussions

[PATCH 04/14] uadk: update acc user mode driver

by Longfang Liu

After adapting the new heterogeneous hybrid acceleration function. The initialization of the device driver requires adaptation updates. In addition, the instruction acceleration algorithm driver needs to fully adapt to the synchronous and asynchronous mode of the uadk framework. Signed-off-by: Longfang Liu <liulongfang(a)huawei.com> --- Makefile.am | 2 +- drv/hisi_comp.c | 3 +++ drv/hisi_dae.c | 3 +++ drv/hisi_hpre.c | 3 +++ drv/hisi_sec.c | 3 +++ drv/isa_ce_sm3.c | 18 ++++++++++++- drv/isa_ce_sm4.c | 22 ++++++++++++++-- include/wd_util.h | 4 +++ wd_util.c | 65 +++++++++++++++++++++++++++++++++++++++++++++++ 9 files changed, 119 insertions(+), 4 deletions(-) diff --git a/Makefile.am b/Makefile.am index d671d09..cf50fec 100644 --- a/Makefile.am +++ b/Makefile.am @@ -93,7 +93,7 @@ libhisi_hpre_la_SOURCES=drv/hisi_hpre.c drv/hisi_qm_udrv.c \ hisi_qm_udrv.h libisa_ce_la_SOURCES=arm_arch_ce.h drv/isa_ce_sm3.c drv/isa_ce_sm3_armv8.S isa_ce_sm3.h \ - drv/isa_ce_sm4.c drv/isa_ce_sm4_armv8.S drv/isa_ce_sm4.h + drv/isa_ce_sm4.c drv/isa_ce_sm4_armv8.S drv/isa_ce_sm4.h wd_util.c wd_util.h libisa_sve_la_SOURCES=drv/hash_mb/hash_mb.c wd_digest_drv.h drv/hash_mb/hash_mb.h \ drv/hash_mb/sm3_sve_common.S drv/hash_mb/sm3_mb_asimd_x1.S \ diff --git a/drv/hisi_comp.c b/drv/hisi_comp.c index 547e665..6099efb 100644 --- a/drv/hisi_comp.c +++ b/drv/hisi_comp.c @@ -807,6 +807,9 @@ static int hisi_zip_init(void *conf, void *priv) memcpy(&zip_ctx->config, config, sizeof(struct wd_ctx_config_internal)); /* allocate qp for each context */ for (i = 0; i < config->ctx_num; i++) { + if (config->ctxs[i].ctx_type != UADK_CTX_HW || + !config->ctxs[i].ctx) + continue; h_ctx = config->ctxs[i].ctx; qm_priv.sqe_size = sizeof(struct hisi_zip_sqe); qm_priv.op_type = config->ctxs[i].op_type; diff --git a/drv/hisi_dae.c b/drv/hisi_dae.c index 49d6b55..e8a75a4 100644 --- a/drv/hisi_dae.c +++ b/drv/hisi_dae.c @@ -1573,6 +1573,9 @@ static int dae_init(void *conf, void *priv) qm_priv.sqe_size = sizeof(struct dae_sqe); /* Allocate qp for each context */ for (i = 0; i < config->ctx_num; i++) { + if (config->ctxs[i].ctx_type != UADK_CTX_HW || + !config->ctxs[i].ctx) + continue; h_ctx = config->ctxs[i].ctx; qm_priv.qp_mode = config->ctxs[i].ctx_mode; /* Setting the epoll en to 0 for ASYNC ctx */ diff --git a/drv/hisi_hpre.c b/drv/hisi_hpre.c index f91d7a8..8ade9ed 100644 --- a/drv/hisi_hpre.c +++ b/drv/hisi_hpre.c @@ -501,6 +501,9 @@ static int hpre_init_qm_priv(struct wd_ctx_config_internal *config, qm_priv->sqe_size = sizeof(struct hisi_hpre_sqe); for (i = 0; i < config->ctx_num; i++) { + if (config->ctxs[i].ctx_type != UADK_CTX_HW || + !config->ctxs[i].ctx) + continue; h_ctx = config->ctxs[i].ctx; qm_priv->qp_mode = config->ctxs[i].ctx_mode; /* Setting the epoll en to 0 for ASYNC ctx */ diff --git a/drv/hisi_sec.c b/drv/hisi_sec.c index 7635466..7f46e4b 100644 --- a/drv/hisi_sec.c +++ b/drv/hisi_sec.c @@ -3095,6 +3095,9 @@ static int hisi_sec_init(void *conf, void *priv) qm_priv.sqe_size = sizeof(struct hisi_sec_sqe); /* allocate qp for each context */ for (i = 0; i < config->ctx_num; i++) { + if (config->ctxs[i].ctx_type != UADK_CTX_HW || + !config->ctxs[i].ctx) + continue; h_ctx = config->ctxs[i].ctx; /* setting the type is 0 for sqc_type */ qm_priv.op_type = 0; diff --git a/drv/isa_ce_sm3.c b/drv/isa_ce_sm3.c index c8812df..110eb4d 100644 --- a/drv/isa_ce_sm3.c +++ b/drv/isa_ce_sm3.c @@ -17,7 +17,6 @@ #include "drv/isa_ce_sm3.h" #include "drv/wd_digest_drv.h" #include "wd_digest.h" -#include "wd_util.h" typedef void (sm3_ce_block_fn)(__u32 word_reg[SM3_STATE_WORDS], const unsigned char *src, size_t blocks); @@ -340,6 +339,7 @@ static int do_hmac_sm3_ce(struct wd_digest_msg *msg, __u8 *out_hmac) static int sm3_ce_drv_send(handle_t ctx, void *digest_msg) { + struct wd_soft_ctx *sfctx = (struct wd_soft_ctx *)ctx; struct wd_digest_msg *msg = (struct wd_digest_msg *)digest_msg; __u8 digest[SM3_DIGEST_SIZE] = {0}; int ret; @@ -349,6 +349,10 @@ static int sm3_ce_drv_send(handle_t ctx, void *digest_msg) return -WD_EINVAL; } + ret = wd_queue_is_busy(sfctx); + if (ret) + return ret; + if (msg->data_fmt == WD_SGL_BUF) { WD_ERR("invalid: SM3 CE driver do not support sgl data format!\n"); return -WD_EINVAL; @@ -363,11 +367,23 @@ static int sm3_ce_drv_send(handle_t ctx, void *digest_msg) ret = -WD_EINVAL; } + ret = wd_get_sqe_from_queue(sfctx, msg->tag); + if (ret) + return ret; + return ret; } static int sm3_ce_drv_recv(handle_t ctx, void *digest_msg) { + struct wd_soft_ctx *sfctx = (struct wd_soft_ctx *)ctx; + struct wd_digest_msg *msg = (struct wd_digest_msg *)digest_msg; + int ret; + + ret = wd_put_sqe_to_queue(sfctx, &msg->tag, &msg->result); + if (ret) + return ret; + return WD_SUCCESS; } diff --git a/drv/isa_ce_sm4.c b/drv/isa_ce_sm4.c index 4b2f9cf..d3cd217 100644 --- a/drv/isa_ce_sm4.c +++ b/drv/isa_ce_sm4.c @@ -11,9 +11,10 @@ * Copyright 2024 Huawei Technologies Co.,Ltd. All rights reserved. */ +#include "wd_alg.h" #include "drv/wd_cipher_drv.h" -#include "wd_cipher.h" #include "isa_ce_sm4.h" +#include "wd_cipher.h" #define SM4_ENCRYPT 1 #define SM4_DECRYPT 0 @@ -323,15 +324,20 @@ static int sm4_xts_decrypt(struct wd_cipher_msg *msg, const struct SM4_KEY *rkey static int isa_ce_cipher_send(handle_t ctx, void *wd_msg) { + struct wd_soft_ctx *sfctx = (struct wd_soft_ctx *)ctx; struct wd_cipher_msg *msg = wd_msg; struct SM4_KEY rkey; int ret = 0; - if (!msg) { + if (!msg || !ctx) { WD_ERR("invalid: input sm4 msg is NULL!\n"); return -WD_EINVAL; } + ret = wd_queue_is_busy(sfctx); + if (ret) + return ret; + if (msg->data_fmt == WD_SGL_BUF) { WD_ERR("invalid: SM4 CE driver do not support sgl data format!\n"); return -WD_EINVAL; @@ -384,11 +390,23 @@ static int isa_ce_cipher_send(handle_t ctx, void *wd_msg) return -WD_EINVAL; } + ret = wd_get_sqe_from_queue(sfctx, msg->tag); + if (ret) + return ret; + return ret; } static int isa_ce_cipher_recv(handle_t ctx, void *wd_msg) { + struct wd_soft_ctx *sfctx = (struct wd_soft_ctx *)ctx; + struct wd_cipher_msg *msg = wd_msg; + int ret; + + ret = wd_put_sqe_to_queue(sfctx, &msg->tag, &msg->result); + if (ret) + return ret; + return 0; } diff --git a/include/wd_util.h b/include/wd_util.h index bee7f29..ff9aa02 100644 --- a/include/wd_util.h +++ b/include/wd_util.h @@ -561,6 +561,10 @@ static inline void wd_ctx_spin_unlock(struct wd_ctx_internal *ctx, int type) pthread_spin_unlock(&ctx->lock); } +int wd_queue_is_busy(struct wd_soft_ctx *sctx); +int wd_get_sqe_from_queue(struct wd_soft_ctx *sctx, __u32 tag_id); +int wd_put_sqe_to_queue(struct wd_soft_ctx *sctx, __u32 *tag_id, __u8 *result); + #ifdef __cplusplus } #endif diff --git a/wd_util.c b/wd_util.c index 848ff15..bf6894b 100644 --- a/wd_util.c +++ b/wd_util.c @@ -3077,3 +3077,68 @@ void wd_alg_attrs_uninit(struct wd_init_attrs *attrs) free(ctx_config); wd_sched_rr_release(alg_sched); } + +int wd_queue_is_busy(struct wd_soft_ctx *sctx) +{ + /* The queue is not used */ + if (sctx->run_num >= MAX_SOFT_QUEUE_LENGTH - 1) + return -WD_EBUSY; + + return 0; +} + +int wd_get_sqe_from_queue(struct wd_soft_ctx *sctx, __u32 tag_id) +{ + struct wd_soft_sqe *sqe = NULL; + + pthread_spin_lock(&sctx->slock); + sqe = &sctx->qfifo[sctx->head]; + if (!sqe->used && !sqe->complete) { // find the next not used sqe + sctx->head++; + if (unlikely(sctx->head == MAX_SOFT_QUEUE_LENGTH)) + sctx->head = 0; + + sqe->used = 1; + sqe->complete = 1; + sqe->id = tag_id; + sqe->result = 0; + __atomic_fetch_add(&sctx->run_num, 0x1, __ATOMIC_ACQUIRE); + pthread_spin_unlock(&sctx->slock); + } else { + pthread_spin_unlock(&sctx->slock); + return -WD_EBUSY; + } + + return 0; +} + +int wd_put_sqe_to_queue(struct wd_soft_ctx *sctx, __u32 *tag_id, __u8 *result) +{ + struct wd_soft_sqe *sqe = NULL; + + /* The queue is not used */ + if (sctx->run_num < 1) + return -WD_EAGAIN; + + if (pthread_spin_trylock(&sctx->rlock)) + return -WD_EAGAIN; + sqe = &sctx->qfifo[sctx->tail]; + if (sqe->used && sqe->complete) { // find a used sqe + sctx->tail++; + if (unlikely(sctx->tail == MAX_SOFT_QUEUE_LENGTH)) + sctx->tail = 0; + + *tag_id = sqe->id; + *result = sqe->result; + sqe->used = 0x0; + sqe->complete = 0x0; + __atomic_fetch_sub(&sctx->run_num, 0x1, __ATOMIC_ACQUIRE); + pthread_spin_unlock(&sctx->rlock); + } else { + pthread_spin_unlock(&sctx->rlock); + return -WD_EAGAIN; + } + + return 0; +} + -- 2.24.0

6 months

[PATCH 00/14] uadk supports heterogeneous computing

by Longfang Liu

Function updates on the uadk framework. Support heterogeneous hybrid computing acceleration functions for all uadk algorithms Longfang Liu (14): Revert "drivers alloc and free resources by themself" uadk: add heterogeneous scheduling solutions uadk: update uadk scheduler uadk: update acc user mode driver uadk: aead adapts to heterogeneous scheduling mode uadk: update hash agg's code uadk: update cipher's function code uadk: comp adapt to heterogeneous scheduling mode uadk: DH adapt to heterogeneous scheduling mode uadk: digest adapt to heterogeneous scheduling mode uadk: ECC adapt to heterogeneous scheduling mode uadk: rsa adapt to heterogeneous scheduling mode uadk: update uadk's internal functions uadk_tool: update uadk test tool Makefile.am | 2 +- drv/hash_mb/hash_mb.c | 48 +- drv/hisi_comp.c | 32 +- drv/hisi_dae.c | 39 +- drv/hisi_hpre.c | 63 +- drv/hisi_sec.c | 120 ++- drv/isa_ce_sm3.c | 55 +- drv/isa_ce_sm4.c | 59 +- include/wd_alg.h | 58 +- include/wd_alg_common.h | 58 +- include/wd_sched.h | 7 + include/wd_util.h | 35 +- uadk_tool/benchmark/sec_uadk_benchmark.c | 71 +- wd_aead.c | 126 ++- wd_agg.c | 81 +- wd_alg.c | 63 +- wd_cipher.c | 103 ++- wd_comp.c | 92 ++- wd_dh.c | 95 ++- wd_digest.c | 125 ++- wd_ecc.c | 97 ++- wd_rsa.c | 95 ++- wd_sched.c | 974 +++++++++++++++++++++-- wd_util.c | 798 ++++++++++++------- 24 files changed, 2205 insertions(+), 1091 deletions(-) -- 2.24.0

6 months

[PATCH 00/14] uadk supports heterogeneous computing

by Longfang Liu

6 months

2025

2024

2023

2022

Acc January 2025