Re: Failure to boot with 13.10

-- Tixy > > > Thanks > > Eric H > > > > > ______________________________________________________________________ > From: Eric Huang > Sent: Wednesday, November 20, 2013 1:05 PM > To: 'Jon Medhurst (Tixy)'; linaro-android@lists.linaro.org > Subject: Failure to boot with 13.10 > > > > > Jon, > > I tried to update my Vexpress TC2 to 13.10, but bootup seems to > stuck at “Running boot script from flash BOOTSCRIPT”. This is the > first time I tried to switch to use UEFI with zImage. I updated the > firmware of my VExpress following the steps listed in the release > note. Any idea what I did wrong? > > > > Cmd> > > Powering up system... > > Daughterboard fitted to site 1. > > > > Switching on ATXPSU... > > ATX3V3: ON > > VIOset: 1.8V > > MBtemp: 37 degC > > > > Configuring motherboard (rev D, var A)... > > IOFPGA config: PASSED > > MUXFPGA config: PASSED > > OSC CLK config: PASSED > > Programming image \SOFTWARE\TC2\zimage.bin > > Erasing Flash > > . > > Writing Flash > > > > Updating eeprom with image zimage > > Image: zimage UPDATED from \SOFTWARE\TC2\zimage.bin > > Programming image \SOFTWARE\TC2\dtb.bin > > Erasing Flash > > . > > Writing Flash > > > > Updating eeprom with image dtb > > Image: dtb UPDATED from \SOFTWARE\TC2\dtb.bin > > Programming image \SOFTWARE\TC2\initrd.bin > > Erasing Flash > > . > > Writing Flash > > > > Updating eeprom with image initrd > > Image: initrd UPDATED from \SOFTWARE\TC2\initrd.bin > > > > Testing SMC devices (FPGA build 16)... > > SRAM 32MB test: PASSED > > VRAM 8MB test: PASSED > > LAN9118 test: PASSED > > USB & OTG test: PASSED > > KMI1/KMI2 test: PASSED > > MMC & SD test: PASSED > > DVI image test: PASSED > > AACI AC97 test: PASSED > > CF card test: PASSED > > UART port test: PASSED > > MAC addrs test: PASSED > > > > Reading Site 1 Board File \SITE1\HBI0249A\board.txt > > DB1 JTAG configuration complete. > > Setting DB1 OSCCLKS... > > DB1.0 DCC 0 SPI configuration complete. > > > > Writing SCC 0x40610007 with 0xFF00FF00 > > Writing SCC 0x40610046 with 0x01CD1011 > > Writing SCC 0x406101C0 with 0x1032F003 > > Writing SCC 0x40610100 with 0x33330C00 > > Writing SCC 0x40610048 with 0x022F1010 > > Writing SCC 0x40610049 with 0x0011710D > > Writing SCC 0x4061004A with 0x022F1010 > > Writing SCC 0x4061004B with 0x0011710D > > Writing SCC 0x4061004C with 0x022F1010 > > Writing SCC 0x4061004D with 0x0011710D > > Writing SCC 0x4061004E with 0x022F1010 > > Writing SCC 0x4061004F with 0x0011710D > > Writing SCC 0x40610300 with 0x00000005 > > Writing SCC 0x40610301 with 0x060E0356 > > Writing SCC 0x40610302 with 0x00000000 > > Writing SCC 0x40610303 with 0x00000000 > > Writing SCC 0x40610304 with 0x384061A8 > > Writing SCC 0x40610305 with 0x38407530 > > Writing SCC 0x40610306 with 0x384088B8 > > Writing SCC 0x40610307 with 0x38409C40 > > Writing SCC 0x40610308 with 0x3840AFC8 > > Writing SCC 0x40610309 with 0x3840C350 > > Writing SCC 0x4061030A with 0x3CF0D6D8 > > Writing SCC 0x4061030B with 0x41A0EA60 > > Writing SCC 0x4061030C with 0x3840445C > > Writing SCC 0x4061030D with 0x38404E20 > > Writing SCC 0x4061030E with 0x384061A8 > > Writing SCC 0x4061030F with 0x38407530 > > Writing SCC 0x40610310 with 0x384088B8 > > Writing SCC 0x40610311 with 0x38409C40 > > Writing SCC 0x40610312 with 0x3CF0AFC8 > > Writing SCC 0x40610313 with 0x41A0C350 > > DB1.0 DCC 0 SCC configuration complete. > > > > DB SMB clock enabled. > > Waiting for SITE1 CB_READY... > > Testing SMB clock... > > Configuring MUXFPGA for MB. > > Setting DVI mode for VGA. > > Releasing Daughterboard resets. > > Switching MCC log to UART1. > > %BootMonitor-Warning, Unable to open SYSTEM.DAT > > > > > > ARM Versatile Express Boot Monitor > > Version: V5.1.9 > > Build Date: Dec 3 2012 > > Daughterboard Site 1: V2P-CA15_A7 Cortex A7 > > Daughterboard Site 2: Not Used > > Running boot script from flash - BOOTSCRIPT > > > > > >