All,
During Connect the suggestion was made that each working group should have
its own IRC Channel for discussions and topics relating to the group in
particular (as opposed to #linaro which is 'generic' Linaro conversations).
Therefore I have just set up #linaro-tcwg on Freenode for the Toolchain
Working Group.
This channel is public and open to anyone who wants to talk with the TCWG
group about anything toolchain related.
Thanks,
Matt
--
Matthew Gretton-Dann
Toolchain Working Group, Linaro
Good afternoon,
I would like to announce the breakthrough in extending gdb with non
intrusive instructions and functions tracing on ARM processors using
Coresight ETM traces, as described in previous mails.
the source code is made public in the git repository
https://github.com/gzied/binutils-gdb/ in the branch gdb_arm_coresight.
this implementation was compiled and tested on an STM32MP1 (ARMv7
Architecture) board running "Linux arm 5.3.10-armv7-lpae-x15" distribution
where the device tree was modified to declare CoreSight components.
to build the software
>checkout the software from the branch gdb_arm_coresight
> cd ..
>mkdir build
>cd build
> ../binutils-gdb/configure --with-arm-cs
>make
after a successful build gdb will be available in the folder build/gdb
to run the software
build the software you would like to debug with debugging info (-g flag)
>gcc -g software.c -o software
start debugging your software
>gdb software
set a breakpoint at main
(gdb) b main
(gdb) run
set a breakpoint in a location after the code you would like to trace
(gdb) b my_function
set your etm sink, sinks can be found by listing the folder
/sys/bus/event_source/devices/cs_etm/sinks/. use a sink that is capable of
storing the traces on chip (etf, etb ...)
(gdb) set record btrace etm sink tmc_etf0
start recording etm traces
(gdb) record btrace etm
continue the execution of the program
(gdb) c
wait until the breakpoint is hit,
analyse and display the traces
- on assembly level
(gdb) record instruction-history
- on c level
(gdb) record function-call-history /ilc
you can increase the number of instructions displayed by using
(gdb) set record instruction-history-size size
(gdb) set record function-call-history-size size
the work is still in an early stage and needs to be improved, extended and
stabilized. your feedback and contributions are welcome
Kind Regards
Zied Guermazi
VirtIO Related Work ([VIRT-366])
================================
- had a couple of HOs and internal threads to flesh out understanding
for VirtIO work
- queried VIRTIO adoption in other hypervisors Message-Id:
<87mu93vwy2.fsf(a)linaro.org> to help understanding
- need a meeting with QC/NXP to discuss their requirements and why
they need certain devices in VirtIO
- a lot of the Android focus seems to be on isolating various secure
workloads
- avoiding needing secure but un-trusted code at elevated privileges
with access to main OS
- suspect the breakdown in the card needs re-arranging
[VIRT-366] <https://projects.linaro.org/browse/VIRT-366>
Upstream Work ([VIRT-109])
==========================
- posted [PATCH v2 00/12] testing/next (with build fixes!) Message-Id:
<20200130113223.31046-10-alex.bennee(a)linaro.org>
- posted [PULL 00/19] testing and plugin updates Message-Id:
<20200226073929.28237-1-alex.bennee(a)linaro.org>
- did some debugging/diagnosis for recent slowdown of ARM emulation in
master Message-Id:
<CAPan3Wq-MVwcJQELP8n+g33CR7tsiGXQ698gA177nd2my9hWCw(a)mail.gmail.com>
- posted [PATCH v1 0/4] Fix codegen translation cache size
Message-Id: <20200226181020.19592-1-alex.bennee(a)linaro.org>
[VIRT-109] <https://projects.linaro.org/browse/VIRT-109>
Completed Reviews [3/3]
=======================
[PATCH v16 00/10] VIRTIO-IOMMU device
Message-Id: <20200214132745.23392-1-eric.auger(a)redhat.com>
- CLOSING NOTE [2020-02-26 Wed 15:37]
It's in an in-flight PR now, will play with it once it lands.
Added: <2020-02-14 Fri>
[PATCH RISU] aarch64.risu: Add patterns for v8.3-RCPC and v8.4-RCPC insns
Message-Id: <20200225143923.22297-1-peter.maydell(a)linaro.org>
[PATCH v3 0/3] Fix number of priority bits for arm boards
Message-Id: <1582537164-764-1-git-send-email-sai.pavan.boddu(a)xilinx.com>
- CLOSING NOTE [2020-02-28 Fri 17:22]
Have been pulled into target-arm next but didn't fix the
kvm-unit-test failures with priority masking as I had hopped they
would.
Added: <2020-02-25 Tue>
Absences
========
- None
Current Review Queue
====================
* [RFC][PATCH 0/3] IVSHMEM version 2 device for QEMU
Message-Id: <cover.1573477032.git.jan.kiszka(a)siemens.com>
Added: <2020-02-14 Fri>
* {PATCH v2 0/2} tests/tcg/multiarch: Add tests for implemented real
Message-Id: <1581603905-21565-1-git-send-email-Filip.Bozuta(a)rt-rk.com>
Added: <2020-02-13 Thu>
* [RFC 0/9] Add an interVM memory sharing device
Message-Id: <1580815851-28887-1-git-send-email-i.kotrasinsk(a)partner.samsung.com>
Added: <2020-02-05 Wed>
* [PATCH v2 0/7] configure: Improve PIE and other linkage
Message-Id: <20191218223441.23852-1-richard.henderson(a)linaro.org>
Added: <2020-01-06 Mon>
--
Alex Bennée
Progress:
* VIRT-65 [QEMU upstream maintainership]
- Got confused by QEMU aborting in the PMU code on a GICv3-only host,
which turns out to be because our error handling for "no GICv2
support" was broken. Sent a patch.
- Another push towards getting texi-to-rST conversion done:
+ Converted a few more simple texi doc files to rST
+ Took up a patchset Paolo did for more automated conversion, and
sorted out the parts it didn't deal with, to get it to a point
where it could delete almost all of the texinfo sources. Sent
a big patchset to the list for review.
- patch review:
+ Gumstix cleanup patchset
+ rth's series to honour more HCR_EL2 traps
+ add a few missing devices to integratorcp
+ get the number of implemented priority bits in GICv2 right
* VIRT-241 [QEMU ISA Support for A-profile]
- Implemented the v8.3-RCPC, v8.4-RCPC and v8.3-CCIDX extensions,
and sent patches to the list
thanks
-- PMM
== Progress ==
* BFD Linker:
- GNU-629: non-contiguous memory support: posted updated v5
* GCC:
* GCC-9: continued work for validation of -mpure-code on v6m. Fix
committed to trunk and backported to gcc-9
* GCC upstream validation:
- reported a couple of failures/regressions
- working on reproducing a non-functional code problem with spec2006
on arm with LTO and -Os
* misc:
- infra fixes / troubleshooting / reviews
== Next ==
* Binutils: GNU-629: support non-contiguous memory regions in linker
* spec2006 / LTO / Os / aarch32
* FDPIC GDB
Four day week.
[VIRT-344 # ARMv8.5-MemTag, Memory Tagging Extension ]
Lots of work here.
Noticed that our TBI handling is wrong for system mode, such that the FAR_ELx
register gets the wrong contents. Noticed that SVE isn't handling TBI at all,
much less being prepared for MTE. Noticed that even AdvSIMD would not quite
produce the correct results for LD*/ST* (multiple structures).
Rearranging the actual MTE check from the ground up. Found an odd case with
DC_ZVA that threw a wrench into that planning.
[VIRT-327 # Richard's upstream QEMU work ]
Honor more HCR_EL2 trap bits.
HPPA patch queue flushed.
Patch review for ppc "hardfloat" patch.
Patch review for memory_region_allocate_system_memory.
r~
Progress:
* VIRT-65 [QEMU upstream maintainership]
- Sent out a patchset creating a 'tools' manual and moving some
docs into it that were previously in the 'interop' manual
- more code review this week than last week
- pushed out another arm pullreq
* VIRT-241 [QEMU ISA Support for A-profile]
- several patches implementing features landed in master,
so I was able to close out some of the subtasks here
thanks
-- PMM
== Progress ==
* BFD Linker:
- GNU-629: non-contiguous memory support: handling feedback received
* GCC:
* GCC-9: continued work for validation of -mpure-code on v6m. All new
failures reported with cortex-m0 + -mpure-code are to be expected
(mainly testcases forcing options incompatible with -mpure-code)
* GCC upstream validation:
- reported a couple of failures/regressions
- looked at a problem with LTO profiled bootstrap failing on aarch32
with gcc-8. Could not reproduce with current trunk
- working on reproducing a non-functional code problem with spec2006
on arm with LTO and -Os
* misc:
- infra fixes / troubleshooting / reviews
- looked at a problem reported about addr2line and kernel symbols.
Needs more analysis
== Next ==
* Binutils: GNU-629: support non-contiguous memory regions in linker
* GCC-9: continue work for validation of -mpure-code on v6m
* spec2006 / LTO / Os / aarch32
* FDPIC GDB
== Progress ==
* More Morello (updating for new capability encoding)
* Tiny amount of GlobalISel arm32 maintenance (not committed yet)
== Plan ==
* More Morello
