All,
During Connect the suggestion was made that each working group should have
its own IRC Channel for discussions and topics relating to the group in
particular (as opposed to #linaro which is 'generic' Linaro conversations).
Therefore I have just set up #linaro-tcwg on Freenode for the Toolchain
Working Group.
This channel is public and open to anyone who wants to talk with the TCWG
group about anything toolchain related.
Thanks,
Matt
--
Matthew Gretton-Dann
Toolchain Working Group, Linaro
== Progress ==
* GCC upstream validation:
- scripts updates and cleanup
- new scheme for arm-eabi now in production (cortex-a7 in arm and
thumb modes, cortex-m[0347,33]
- upgraded to qemu-5.0
- reported a few regressions
* GCC:
- PR94743 (IRQ handler and Neon registers): No feedback yet.
* misc:
- infra fixes / troubleshooting / reviews
- looking at cortex-m benchmarking harnesses, at last able to run a
sample code on my small stm32 board
- internal meetings / paperwork
== Next ==
* GCC validation
- switch to qemu-system-mode for cortex-m33, in order to run the cmse tests
* PR94743
* GCC/cortex-M testing
* cortex-m benchmarking
* FDPIC GDB
[VIRT-339 # ARMv8.5-BTI, Branch Target Identification ]
Updated to match the latest kernel for-next/bti-user branch; I hope this is
going to be merged for 5.7.
Posted v9 for review.
[VIRT-349 # QEMU SVE2 Supprt ]
More RISU work to improve support for SVE. Stephen Long has posted some sve2
risu patterns that need reviewing, and I plan to test all of that next week vs
ArmIE.
I had a start on rebasing my current sve2 patch set on master, with lots of
prereqs merged. But stopped in the middle because I realized that I wanted to
get all of the RISU work done first, so that I can test each patch as it is
updated.
r~
PS: Out all next week on holiday.
Progress:
* VIRT-65 [QEMU upstream maintainership]
- Various bits of code review; put together and sent another
arm pullreq.
* VIRT-364 [QEMU support for ARMv8.1-M extensions]
- Fixed up the 2-reg-shift/1-reg-imm patchset as per code review
comments and sent a v2
thanks
-- PMM
[VIRT-344 # ARMv8.5-MemTag, Memory Tagging Extension ]
Some prerequisites merged upstream.
[VIRT-349 # QEMU SVE2 Support ]
Some prerequisites merged upstream.
Work on risu to compress sve output files.
Split out the crypto conversion to gvec.
[VIRT-327 # Richard's upstream QEMU work ]
Posted some softfloat cleanups.
Some patch review.
Support non-overlapping regions for decodetree.
r~
VirtIO Related Work ([VIRT-366])
================================
VirtiIO blogpost ([LBO-2])
- finished final version of draft with future work and call to action
[LBO-2] <https://projects.linaro.org/browse/LBO-2>
Upstream Work ([VIRT-109])
==========================
- posted [PATCH v1 0/8] plugins/next (cleanup, cpu_index and lockstep)
Message-Id: <20200513173200.11830-1-alex.bennee(a)linaro.org>
- posted [PATCH v1 00/10] testing and tcg tweaks Message-Id:
<20200513175134.19619-1-alex.bennee(a)linaro.org>
- posted [PULL v2 00/13] testing, tcg and plugin updates Message-Id:
<20200515144405.20580-1-alex.bennee(a)linaro.org>
[VIRT-109] <https://projects.linaro.org/browse/VIRT-109>
Completed Reviews [9/9]
=======================
[PATCH 0/4] softfloat: fix floatx80 emulation bugs
Message-Id: <alpine.DEB.2.21.2005010034560.30535(a)digraph.polyomino.org.uk>
[PATCH v2 0/4] softfloat: fix floatx80 emulation bugs
Message-Id: <alpine.DEB.2.21.2005042332380.22972(a)digraph.polyomino.org.uk>
- CLOSING NOTE [2020-05-11 Mon 08:16]
rth already pulled into his tree
Added: <2020-05-05 Tue>
[PATCH v4 00/10] tests/vm: Add support for aarch64 VMs
Message-Id: <20200312142728.12285-1-robert.foley(a)linaro.org>
- CLOSING NOTE [2020-05-11 Mon 10:22]
Generally looks ok but awaiting v11 to deal with re-base conflicts
to fully test.
Added: <2020-03-27 Fri>
[PATCH v8 00/74] per-CPU locks
Message-Id: <20200326193156.4322-1-robert.foley(a)linaro.org>
- CLOSING NOTE [2020-05-12 Tue 19:39]
A few minor comments but looking good. Ran stress testing.
Added: <2020-03-27 Fri>
[PATCH 0/3] plugins: Move declarations around and rename 'hwaddr' argument
Message-Id: <20200510171119.20827-1-f4bug(a)amsat.org>
- CLOSING NOTE [2020-05-12 Tue 19:45]
Queued to my tree
Added: <2020-05-10 Sun>
[PATCH 3/3] plugins: avoid failing plugin when CPU is inited several times
Message-Id: <CAEme+7FPF+inSJSXQPmuv8Up3Eam0N7fT03zqM-RvcvKsxjfVQ(a)mail.gmail.com>
- didn't apply but found bug in cpu_index code
[PATCH 0/5] docs/system: Document some arm board models
Message-Id: <20200507151819.28444-1-peter.maydell(a)linaro.org>
[PATCH v6 0/9] tests/vm: Add support for aarch64 VMs
Message-Id: <20200512193340.265-1-robert.foley(a)linaro.org>
- CLOSING NOTE [2020-05-15 Fri 18:31]
Ran into problems testing on my Gentoo box, sent some patches to
rf-fw
Added: <2020-05-12 Tue>
[PATCH 0/5] target/i386: fxtract, fscale fixes
Message-Id: <alpine.DEB.2.21.2005070038550.18350(a)digraph.polyomino.org.uk>
- CLOSING NOTE [2020-05-15 Fri 18:32]
Testing bit looks ok, leaving the x86 side to people that understand
it.
Added: <2020-05-15 Fri>
--
Alex Bennée
== Progress ==
* GCC upstream validation:
- reported a couple of regressions
- sent an email to discussed the preferred combinations when running
the testsuite
* GCC:
- PR94743 (IRQ handler and Neon registers): iterating. Sent updated
patch to emit a warning. Cleanup patches merged. Sent WIP patch that
saves FP regs for discussion.
* misc:
- infra fixes / troubleshooting / reviews
- looking at cortex-m benchmarking harnesses, issues with openocd
== Next ==
* GCC validation matrix updates
* PR94743
* GCC/cortex-M testing
* cortex-m benchmarking
* FDPIC GDB
