------------------&nbsp;Original&nbsp;------------------ From: "Lorenzo Pieralisi" <lorenzo.pieralisi@linaro.org&gt;; Date:&nbsp;Sat, Dec 17, 2022 00:14 AM To:&nbsp;"Zhangfei Gao"<zhangfei.gao@linaro.org&gt;; Cc:&nbsp;"Joyce Qi"<joyce.qi@linaro.org&gt;;"jean-philippe"<jean-philippe@linaro.org&gt;;"linaro-open-discussions"<linaro-open-discussions@op-lists.linaro.org&gt;;"linux"<linux@armlinux.org.uk&gt;; Subject:&nbsp;Re: [Linaro-open-discussions] Re: Linaro-open-discussions Digest, Vol 25, Issue 3

On Thu, Oct 27, 2022 at 12:06:59PM +0800, Zhangfei Gao wrote: &gt; Hi, Lorenzo &gt; &gt; When we debug vsva, sva on guest with 2-stage translation, &gt; we found tlb miss impact performance a lot, with Jean's help. &gt; &gt; Currently we are using huge page feature in glibc to overcome this issue. &gt; With huge page, vsva in guest can achieve comparable performance as sva in &gt; host. &gt; &gt; More details: https://docs.qq.com/doc/DRXlpQmpTSlBZTGZZ &gt; Will do some &gt; &gt; Basically we are using two optimization methods/ &gt; host sva: using memset fist to overcome io page fault, since cpu alloc &gt; physical memory is much faster than smmu. &gt; guest vsva: using huge page to overcome tlbmiss. &gt; &gt; The customer are asking whether (next version) silicon (smmu) can do some &gt; help to concur tlb miss issue or io page fault issue.

I can bring this up with the SMMU architect - thank you for taking time to describe the use cases and SW you are deploying.

&gt; If so, software can be simpler. &gt; Any suggestions?

Talking to SMMU architects - there is not much SW can do other than what you are doing already.

Thanks, Lorenzo

&gt; Thanks &gt; &gt; &gt; On 2022/10/20 下午8:47, Joyce Qi via Linaro-open-discussions wrote: &gt; &gt; Hi Jonathan,Lorenzo,all, &gt; &gt; &gt; &gt; Do we have any topic to sync on our LOD meeting next week? &gt; &gt; &gt; &gt; Thanks:) &gt; &gt; Joyce &gt; &gt; &gt; &gt; &gt; &gt; &gt;&nbsp;