linaro-android March 2012

linaro-android@lists.linaro.org

52 participants
56 discussions

Port Android Ice Cream Sandwich to Pandaboard(TI OMAP4460)

by mammar

Hi, I am a newbie to porting and currently learning embedded systems with interest in Android. So i thought it would be good learning if port Android Ice Cream Sandwich to Pandaboard(TI OMAP4460). Note: I know that Android Ice Cream Sandwich is already ported to Pandaboard but as i am a newbie so i want to learn the things from scratch to strengthen my skills. https://wiki.linaro.org/Platform/Android I started from the above link to see how can i start porting android to a board. The link below gives the steps to get android source code from https://android-build.linaro.org/. But there are lots of builds on https://android-build.linaro.org/ and i don't know which should i get for my pandaboard. https://wiki.linaro.org/Platform/Android/GetSource I also followed the link below https://wiki.linaro.org/Platform/Android/PortingToNewBoard but the git clone git://android.git.linaro.org/platform/manifests.git gives the following error Initialized empty Git repository in /home/ma/android/manifests/.git/ fatal: The remote end hung up unexpectedly Can someone kindly guide me in the right direction so that i can download and build the right code for my pandaboard and make further changes in the Android ICS code for pandaboard. Any sort of help will be greatly appreciated. Thanks.

12 years, 1 month

Switching to 12.03 release toolchain for Android builds

by Abhishek Paliwal

12 years, 1 month

Upcoming Dates for Android 12.03 Release

by Zach Pfeffer

Its that time of the month again. From, https://wiki.linaro.org/Cycles. Here's the plan: March 15th, Toolchain WG Release 2012.03 (Done) March 22nd, Kernel WG Freeze, WGs/LTs Release March 26th, Cut Android releases (Abhishek will select the last tip that boots to a UI) March 27th, QA Android releases March 29th, Release Linaro Android 12.03 If there is something you need to get in, please get it in now. If tips aren't booting please take a look now so we can stabilize things. We've had 2 RC this month. Take a look at the QA test sheets for the bootloader testing we've done. Origen: QA sheets: https://docs.google.com/a/linaro.org/spreadsheet/ccc?key=0AkxwyUNxNaAadDRDV… Snowball: QA Sheet: https://docs.google.com/a/linaro.org/spreadsheet/ccc?key=0AkxwyUNxNaAadEF1N… iMX53/iMX6: QA Sheet: https://docs.google.com/a/linaro.org/spreadsheet/ccc?key=0AkxwyUNxNaAadDE1M… Panda: (4430/4460) QA Sheet : https://docs.google.com/a/linaro.org/spreadsheet/ccc?key=0AkxwyUNxNaAadGVWd… Vexpress: QA Sheet: https://docs.google.com/a/linaro.org/spreadsheet/ccc?key=0AkxwyUNxNaAadExQd… -- Zach Pfeffer Android Platform Team Lead, Linaro Platform Teams Linaro.org | Open source software for ARM SoCs Follow Linaro: http://www.facebook.com/pages/Linaro http://twitter.com/#!/linaroorg - http://www.linaro.org/linaro-blog

12 years, 1 month

RE: HELP - Cannot boot Origen Board

by Andrew Fraser

In response to your questions: The .img file came from Origen/Insignal website. I also tried with the image you mention but got exactly the same results. The LCD never comes up - no backlight, no display. The SD power LED (LED4) comes on while I see the boot text in terminal then the boot text stops and LED4 goes out. I tried the Ubuntu image as well - similar results, I see output on terminal which stops and LED4 goes off. Again, absolutely no display on the LCD and no ability to log in on the terminal. Thanks for your interest. Andy ________________________________ From: Amit Pundir [mailto:amit.pundir@linaro.org] Sent: Mon 19/03/2012 06:16 To: Andrew Fraser Cc: linaro-android(a)lists.linaro.org Subject: Re: HELP - Cannot boot Origen Board Hi Andrew, On 17 March 2012 01:23, Andrew Fraser <afraser(a)andyfraser.co.uk> wrote: I have just purchased an Origen Board - Full Package. I flashed the SD card with igen-ics-gcc46-samsunglt-stable-blob.img We do not ship images in .img format. Did you try the images from https://android-build.linaro.org/builds/~linaro-android/origen-ics-gcc46-sa… ? and placed it into the SD card slot. I flicked the power switch and pressed SWITCH then POWER and saw the board booting in terminal. However, after a short period of time LED4 turns off and I do not see the LCD light or show the Android screen. Do you mean LCD and Android UI doesn't come up at all or they turned off after some time? The output in terminal is given below. Is my board faulty or have I not flashed the correct image to the SD card ? If this output is all you have got then there is definitely something wrong somewhere. Did you try booting Linaro's Ubuntu images on Origen? Regards, Amit Pundir U-Boot 2011.06-01275-gd6186aa (Feb 17 2012 - 08:54:12) for ORIGEN CPU: S5PC210@1000MHz Board: ORIGEN DRAM: 1 GiB WARNING: Caches not enabled MMC: SAMSUNG SD/MMC: 0 *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial Hit any key to stop autoboot: 0 reading boot.scr 397 bytes read Running bootscript from mmc0:2 ... ## Executing script at 42000000 reading uImage 4049424 bytes read reading uInitrd 166156 bytes read ## Booting kernel from Legacy Image at 40007000 ... Image Name: Linux-3.0.4+ Image Type: ARM Linux Kernel Image (uncompressed) Data Size: 4049360 Bytes = 3.9 MiB Load Address: 40008000 Entry Point: 40008000 Verifying Checksum ... OK ## Loading init Ramdisk from Legacy Image at 42000000 ... Image Name: Android Ramdisk Image Image Type: ARM Linux RAMDisk Image (gzip compressed) Data Size: 166092 Bytes = 162.2 KiB Load Address: 00000000 Entry Point: 00000000 Verifying Checksum ... OK Loading Kernel Image ... OK OK Starting kernel ... Uncompressing Linux... done, booting the kernel. <5>Linux version 3.0.4+ (jenkins-build@ip-10-140-6-146) (gcc version 4.6.3 20120201 (prerelease) (Linaro GCC 4.6-2012.02) ) #1 SMP PREEMPT Fri Feb 17 09:34:26 UTC 2012 CPU: ARMv7 Processor [412fc091] revision 1 (ARMv7), cr=10c5387f CPU: VIPT nonaliasing data cache, VIPT aliasing instruction cache Machine: ORIGEN <4>Ignoring unrecognised tag 0x00000000 <4>Ignoring unrecognised tag 0x00000000 <4>Ignoring unrecognised tag 0x00000000 <4>Ignoring unrecognised tag 0x00000000 <5>Truncating RAM at 60000000-7fffffff to -6dffffff (vmalloc region overlap). <3>CMA reserve : jpeg, addr is 0x5e800000, size is 0x1800000 <3>CMA reserve : fimc0, addr is 0x5e300000, size is 0x500000 <3>CMA reserve : fimc1, addr is 0x5de00000, size is 0x500000 <3>CMA reserve : fimc2, addr is 0x5d900000, size is 0x500000 <3>CMA reserve : fimc3, addr is 0x5d400000, size is 0x500000 <3>CMA reserve : fimd, addr is 0x5bc00000, size is 0x1800000 <3>CMA reserve : common, addr is 0x57c00000, size is 0x4000000 <3>CMA reserve : (null), addr is 0x57c00000, size is 0x0 Memory policy: ECC disabled, Data cache writealloc CPU EXYNOS4210 (id 0x43210011) <7>exynos4_init_clocks: initializing clocks <6>S3C24XX Clocks, Copyright 2004 Simtec Electronics <3>s3c_register_clksrc: clock armclk has no registers set <3>mout_audss: bad source 0 <7>exynos4_setup_clocks: registering clocks <7>exynos4_setup_clocks: xtal is 24000000 <6>EXYNOS4: PLL settings, A=1000000000, M=800000000, E=96000000 V=108000000<6>EXYNOS4: ARMCLK=1000000000, DMC=400000000, ACLK200=200000000 ACLK100=100000000, ACLK160=160000000, ACLK133=133333333 <6>uclk1: source is mout_mpll (6), rate is 100000000 <6>uclk1: source is mout_mpll (6), rate is 100000000 <6>uclk1: source is mout_mpll (6), rate is 100000000 <6>uclk1: source is mout_mpll (6), rate is 100000000 <6>sclk_pwm: source is ext_xtal (0), rate is 24000000 <6>sclk_csis: source is xusbxti (1), rate is 0 <6>sclk_csis: source is xusbxti (1), rate is 0 <6>sclk_cam0: source is xusbxti (1), rate is 0 <6>sclk_cam1: source is xusbxti (1), rate is 0 <6>sclk_fimc: source is xusbxti (1), rate is 0 <6>sclk_fimc: source is xusbxti (1), rate is 0 <6>sclk_fimc: source is xusbxti (1), rate is 0 <6>sclk_fimc: source is xusbxti (1), rate is 0 <6>sclk_mixer: source is sclk_dac (0), rate is 24000000 <6>sclk_fimd0: source is xusbxti (1), rate is 0 <6>sclk_fimd1: source is xusbxti (1), rate is 0 <6>sclk_sata: source is mout_mpll (0), rate is 133333333 <6>sclk_spi: source is xusbxti (1), rate is 0 <6>sclk_spi: source is mout_mpll (6), rate is 80000000 <6>sclk_spi: source is xusbxti (1), rate is 0 <6>sclk_fimg2d: source is mout_g2d0 (0), rate is 100000000 <7>On node 0 totalpages: 188416 <7> Normal zone: 1472 pages used for memmap <7> Normal zone: 0 pages reserved <7> Normal zone: 186944 pages, LIFO batch:31 <6>PERCPU: Embedded 7 pages/cpu @c0f96000 s6528 r8192 d13952 u32768 <7>pcpu-alloc: s6528 r8192 d13952 u32768 alloc=8*4096 <7>pcpu-alloc: [0] 0 [0] 1 Built 1 zonelists in Zone order, mobility grouping on. Total pages: 186944 <5>Kernel command line: console=tty0 console=ttySAC2,115200n8 rootwait ro init=/init androidboot.console=ttySAC2 console=ttySAC2 root=/dev/mmcblk0p2 <6>PID hash table entries: 4096 (order: 2, 16384 bytes) <6>Dentry cache hash table entries: 131072 (order: 7, 524288 bytes) <6>Inode-cache hash table entries: 65536 (order: 6, 262144 bytes) <6>Memory: 736MB = 736MB total <5>Memory: 601736k/601736k available, 151928k reserved, 0K highmem <5>Virtual kernel memory layout: vector : 0xffff0000 - 0xffff1000 ( 4 kB) fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB) DMA : 0xfe800000 - 0xffe00000 ( 22 MB) vmalloc : 0xee800000 - 0xf6000000 ( 120 MB) lowmem : 0xc0000000 - 0xee000000 ( 736 MB) modules : 0xbf000000 - 0xc0000000 ( 16 MB) .text : 0xc0008000 - 0xc078fd14 (7712 kB) .init : 0xc0790000 - 0xc07d5980 ( 279 kB) .data : 0xc07d6000 - 0xc0835930 ( 383 kB) .bss : 0xc0835954 - 0xc098bca8 (1369 kB) <6>Preemptible hierarchical RCU implementation. <6>NR_IRQS:624 <6>sched_clock: 32 bits at 50MHz, resolution 20ns, wraps every 85899ms <6>Console: colour dummy device 80x30 <6>console [tty0] enabled Linux version 3.0.4+ (jenkins-build@ip-10-140-6-146) (gcc version 4.6.3 20120201 (prerelease) (Linaro GCC 4.6-2012.02) ) #1 SMP PREEMPT Fri Feb 17 09:34:26 UTC 2012 CPU: ARMv7 Processor [412fc091] revision 1 (ARMv7), cr=10c5387f CPU: VIPT nonaliasing data cache, VIPT aliasing instruction cache Machine: ORIGEN Ignoring unrecognised tag 0x00000000 Ignoring unrecognised tag 0x00000000 Ignoring unrecognised tag 0x00000000 Ignoring unrecognised tag 0x00000000 Truncating RAM at 60000000-7fffffff to -6dffffff (vmalloc region overlap). CMA reserve : jpeg, addr is 0x5e800000, size is 0x1800000 CMA reserve : fimc0, addr is 0x5e300000, size is 0x500000 CMA reserve : fimc1, addr is 0x5de00000, size is 0x500000 CMA reserve : fimc2, addr is 0x5d900000, size is 0x500000 CMA reserve : fimc3, addr is 0x5d400000, size is 0x500000 CMA reserve : fimd, addr is 0x5bc00000, size is 0x1800000 CMA reserve : common, addr is 0x57c00000, size is 0x4000000 CMA reserve : (null), addr is 0x57c00000, size is 0x0 Memory policy: ECC disabled, Data cache writealloc CPU EXYNOS4210 (id 0x43210011) S3C24XX Clocks, Copyright 2004 Simtec Electronics s3c_register_clksrc: clock armclk has no registers set mout_audss: bad source 0 EXYNOS4: PLL settings, A=1000000000, M=800000000, E=96000000 V=108000000 EXYNOS4: ARMCLK=1000000000, DMC=400000000, ACLK200=200000000 ACLK100=100000000, ACLK160=160000000, ACLK133=133333333 uclk1: source is mout_mpll (6), rate is 100000000 uclk1: source is mout_mpll (6), rate is 100000000 uclk1: source is mout_mpll (6), rate is 100000000 uclk1: source is mout_mpll (6), rate is 100000000 sclk_pwm: source is ext_xtal (0), rate is 24000000 sclk_csis: source is xusbxti (1), rate is 0 sclk_csis: source is xusbxti (1), rate is 0 sclk_cam0: source is xusbxti (1), rate is 0 sclk_cam1: source is xusbxti (1), rate is 0 sclk_fimc: source is xusbxti (1), rate is 0 sclk_fimc: source is xusbxti (1), rate is 0 sclk_fimc: source is xusbxti (1), rate is 0 sclk_fimc: source is xusbxti (1), rate is 0 sclk_mixer: source is sclk_dac (0), rate is 24000000 sclk_fimd0: source is xusbxti (1), rate is 0 sclk_fimd1: source is xusbxti (1), rate is 0 sclk_sata: source is mout_mpll (0), rate is 133333333 sclk_spi: source is xusbxti (1), rate is 0 sclk_spi: source is mout_mpll (6), rate is 80000000 sclk_spi: source is xusbxti (1), rate is 0 sclk_fimg2d: source is mout_g2d0 (0), rate is 100000000 PERCPU: Embedded 7 pages/cpu @c0f96000 s6528 r8192 d13952 u32768 Built 1 zonelists in Zone order, mobility grouping on. Total pages: 186944 Kernel command line: console=tty0 console=ttySAC2,115200n8 rootwait ro init=/init androidboot.console=ttySAC2 console=ttySAC2 root=/dev/mmcblk0p2 PID hash table entries: 4096 (order: 2, 16384 bytes) Dentry cache hash table entries: 131072 (order: 7, 524288 bytes) Inode-cache hash table entries: 65536 (order: 6, 262144 bytes) Memory: 736MB = 736MB total Memory: 601736k/601736k available, 151928k reserved, 0K highmem Virtual kernel memory layout: vector : 0xffff0000 - 0xffff1000 ( 4 kB) fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB) DMA : 0xfe800000 - 0xffe00000 ( 22 MB) vmalloc : 0xee800000 - 0xf6000000 ( 120 MB) lowmem : 0xc0000000 - 0xee000000 ( 736 MB) modules : 0xbf000000 - 0xc0000000 ( 16 MB) .text : 0xc0008000 - 0xc078fd14 (7712 kB) .init : 0xc0790000 - 0xc07d5980 ( 279 kB) .data : 0xc07d6000 - 0xc0835930 ( 383 kB) .bss : 0xc0835954 - 0xc098bca8 (1369 kB) Preemptible hierarchical RCU implementation. NR_IRQS:624 sched_clock: 32 bits at 50MHz, resolution 20ns, wraps every 85899ms Console: colour dummy device 80x30 console <tty0] enabled 6>console [ttySAC2] enabled console [tt<SAC2] enabled 6>Calibrating delay loop... Calibrating delay loop... <c>1992.29 BogoMIPS (lpj=4980736) 1992.29 BogoMIPS<(lpj=4980736) 6>pid_max: default: 32768 minimum: 301 pid_max: default: 32768 minimum: 301 <6>Mount-cache hash table entries: 512 Mount-cache hash table entries: 512 <6>CPU: Testing write buffer coherency: CPU: Testing write buffer coherency: ok ok <6>ftrace: allocating 19856 entries in 59 pages ftrace: allocating 19856 entries in 59 pages <6>CPU0: thread -1, cpu 0, socket 9, mpidr 80000900 CPU0: thread -1, cpu 0, socket 9, <pidr 80000900 6>Calibrating local timer... Calibrating local timer... 249.93MHz. 249.93MHz. <6>hw perfevents: enabled with ARMv7 Cortex-A9 PMU driver, 7 counters available hw perfevents: enabled with ARMv7 Cortex-A9 PMU driver, 7 counters available <6>L310 cache controller enabled L310 cache cont<oller enabled 6>l2x0: 16 ways, CACHE_ID 0x4100c4c5, AUX_CTRL 0x7e470001, Cache size: 1048576 B l2x0: 16 ways, CACHE_ID 0x4100c4c5, AUX_CTRL 0x7e470001, Cache size: 1048576 B CPU1: Booted secondary processor <2>CPU1: Unknown IPI message 0x1 _______________________________________________ linaro-android mailing list linaro-android(a)lists.linaro.org http://lists.linaro.org/mailman/listinfo/linaro-android

12 years, 1 month

HELP - Cannot boot Origen Board

by Andrew Fraser

I have just purchased an Origen Board - Full Package. I flashed the SD card with igen-ics-gcc46-samsunglt-stable-blob.img and placed it into the SD card slot. I flicked the power switch and pressed SWITCH then POWER and saw the board booting in terminal. However, after a short period of time LED4 turns off and I do not see the LCD light or show the Android screen. The output in terminal is given below. Is my board faulty or have I not flashed the correct image to the SD card ? U-Boot 2011.06-01275-gd6186aa (Feb 17 2012 - 08:54:12) for ORIGEN CPU: S5PC210@1000MHz Board: ORIGEN DRAM: 1 GiB WARNING: Caches not enabled MMC: SAMSUNG SD/MMC: 0 *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial Hit any key to stop autoboot: 0 reading boot.scr 397 bytes read Running bootscript from mmc0:2 ... ## Executing script at 42000000 reading uImage 4049424 bytes read reading uInitrd 166156 bytes read ## Booting kernel from Legacy Image at 40007000 ... Image Name: Linux-3.0.4+ Image Type: ARM Linux Kernel Image (uncompressed) Data Size: 4049360 Bytes = 3.9 MiB Load Address: 40008000 Entry Point: 40008000 Verifying Checksum ... OK ## Loading init Ramdisk from Legacy Image at 42000000 ... Image Name: Android Ramdisk Image Image Type: ARM Linux RAMDisk Image (gzip compressed) Data Size: 166092 Bytes = 162.2 KiB Load Address: 00000000 Entry Point: 00000000 Verifying Checksum ... OK Loading Kernel Image ... OK OK Starting kernel ... Uncompressing Linux... done, booting the kernel. <5>Linux version 3.0.4+ (jenkins-build@ip-10-140-6-146) (gcc version 4.6.3 20120201 (prerelease) (Linaro GCC 4.6-2012.02) ) #1 SMP PREEMPT Fri Feb 17 09:34:26 UTC 2012 CPU: ARMv7 Processor [412fc091] revision 1 (ARMv7), cr=10c5387f CPU: VIPT nonaliasing data cache, VIPT aliasing instruction cache Machine: ORIGEN <4>Ignoring unrecognised tag 0x00000000 <4>Ignoring unrecognised tag 0x00000000 <4>Ignoring unrecognised tag 0x00000000 <4>Ignoring unrecognised tag 0x00000000 <5>Truncating RAM at 60000000-7fffffff to -6dffffff (vmalloc region overlap). <3>CMA reserve : jpeg, addr is 0x5e800000, size is 0x1800000 <3>CMA reserve : fimc0, addr is 0x5e300000, size is 0x500000 <3>CMA reserve : fimc1, addr is 0x5de00000, size is 0x500000 <3>CMA reserve : fimc2, addr is 0x5d900000, size is 0x500000 <3>CMA reserve : fimc3, addr is 0x5d400000, size is 0x500000 <3>CMA reserve : fimd, addr is 0x5bc00000, size is 0x1800000 <3>CMA reserve : common, addr is 0x57c00000, size is 0x4000000 <3>CMA reserve : (null), addr is 0x57c00000, size is 0x0 Memory policy: ECC disabled, Data cache writealloc CPU EXYNOS4210 (id 0x43210011) <7>exynos4_init_clocks: initializing clocks <6>S3C24XX Clocks, Copyright 2004 Simtec Electronics <3>s3c_register_clksrc: clock armclk has no registers set <3>mout_audss: bad source 0 <7>exynos4_setup_clocks: registering clocks <7>exynos4_setup_clocks: xtal is 24000000 <6>EXYNOS4: PLL settings, A=1000000000, M=800000000, E=96000000 V=108000000<6>EXYNOS4: ARMCLK=1000000000, DMC=400000000, ACLK200=200000000 ACLK100=100000000, ACLK160=160000000, ACLK133=133333333 <6>uclk1: source is mout_mpll (6), rate is 100000000 <6>uclk1: source is mout_mpll (6), rate is 100000000 <6>uclk1: source is mout_mpll (6), rate is 100000000 <6>uclk1: source is mout_mpll (6), rate is 100000000 <6>sclk_pwm: source is ext_xtal (0), rate is 24000000 <6>sclk_csis: source is xusbxti (1), rate is 0 <6>sclk_csis: source is xusbxti (1), rate is 0 <6>sclk_cam0: source is xusbxti (1), rate is 0 <6>sclk_cam1: source is xusbxti (1), rate is 0 <6>sclk_fimc: source is xusbxti (1), rate is 0 <6>sclk_fimc: source is xusbxti (1), rate is 0 <6>sclk_fimc: source is xusbxti (1), rate is 0 <6>sclk_fimc: source is xusbxti (1), rate is 0 <6>sclk_mixer: source is sclk_dac (0), rate is 24000000 <6>sclk_fimd0: source is xusbxti (1), rate is 0 <6>sclk_fimd1: source is xusbxti (1), rate is 0 <6>sclk_sata: source is mout_mpll (0), rate is 133333333 <6>sclk_spi: source is xusbxti (1), rate is 0 <6>sclk_spi: source is mout_mpll (6), rate is 80000000 <6>sclk_spi: source is xusbxti (1), rate is 0 <6>sclk_fimg2d: source is mout_g2d0 (0), rate is 100000000 <7>On node 0 totalpages: 188416 <7> Normal zone: 1472 pages used for memmap <7> Normal zone: 0 pages reserved <7> Normal zone: 186944 pages, LIFO batch:31 <6>PERCPU: Embedded 7 pages/cpu @c0f96000 s6528 r8192 d13952 u32768 <7>pcpu-alloc: s6528 r8192 d13952 u32768 alloc=8*4096 <7>pcpu-alloc: [0] 0 [0] 1 Built 1 zonelists in Zone order, mobility grouping on. Total pages: 186944 <5>Kernel command line: console=tty0 console=ttySAC2,115200n8 rootwait ro init=/init androidboot.console=ttySAC2 console=ttySAC2 root=/dev/mmcblk0p2 <6>PID hash table entries: 4096 (order: 2, 16384 bytes) <6>Dentry cache hash table entries: 131072 (order: 7, 524288 bytes) <6>Inode-cache hash table entries: 65536 (order: 6, 262144 bytes) <6>Memory: 736MB = 736MB total <5>Memory: 601736k/601736k available, 151928k reserved, 0K highmem <5>Virtual kernel memory layout: vector : 0xffff0000 - 0xffff1000 ( 4 kB) fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB) DMA : 0xfe800000 - 0xffe00000 ( 22 MB) vmalloc : 0xee800000 - 0xf6000000 ( 120 MB) lowmem : 0xc0000000 - 0xee000000 ( 736 MB) modules : 0xbf000000 - 0xc0000000 ( 16 MB) .text : 0xc0008000 - 0xc078fd14 (7712 kB) .init : 0xc0790000 - 0xc07d5980 ( 279 kB) .data : 0xc07d6000 - 0xc0835930 ( 383 kB) .bss : 0xc0835954 - 0xc098bca8 (1369 kB) <6>Preemptible hierarchical RCU implementation. <6>NR_IRQS:624 <6>sched_clock: 32 bits at 50MHz, resolution 20ns, wraps every 85899ms <6>Console: colour dummy device 80x30 <6>console [tty0] enabled Linux version 3.0.4+ (jenkins-build@ip-10-140-6-146) (gcc version 4.6.3 20120201 (prerelease) (Linaro GCC 4.6-2012.02) ) #1 SMP PREEMPT Fri Feb 17 09:34:26 UTC 2012 CPU: ARMv7 Processor [412fc091] revision 1 (ARMv7), cr=10c5387f CPU: VIPT nonaliasing data cache, VIPT aliasing instruction cache Machine: ORIGEN Ignoring unrecognised tag 0x00000000 Ignoring unrecognised tag 0x00000000 Ignoring unrecognised tag 0x00000000 Ignoring unrecognised tag 0x00000000 Truncating RAM at 60000000-7fffffff to -6dffffff (vmalloc region overlap). CMA reserve : jpeg, addr is 0x5e800000, size is 0x1800000 CMA reserve : fimc0, addr is 0x5e300000, size is 0x500000 CMA reserve : fimc1, addr is 0x5de00000, size is 0x500000 CMA reserve : fimc2, addr is 0x5d900000, size is 0x500000 CMA reserve : fimc3, addr is 0x5d400000, size is 0x500000 CMA reserve : fimd, addr is 0x5bc00000, size is 0x1800000 CMA reserve : common, addr is 0x57c00000, size is 0x4000000 CMA reserve : (null), addr is 0x57c00000, size is 0x0 Memory policy: ECC disabled, Data cache writealloc CPU EXYNOS4210 (id 0x43210011) S3C24XX Clocks, Copyright 2004 Simtec Electronics s3c_register_clksrc: clock armclk has no registers set mout_audss: bad source 0 EXYNOS4: PLL settings, A=1000000000, M=800000000, E=96000000 V=108000000 EXYNOS4: ARMCLK=1000000000, DMC=400000000, ACLK200=200000000 ACLK100=100000000, ACLK160=160000000, ACLK133=133333333 uclk1: source is mout_mpll (6), rate is 100000000 uclk1: source is mout_mpll (6), rate is 100000000 uclk1: source is mout_mpll (6), rate is 100000000 uclk1: source is mout_mpll (6), rate is 100000000 sclk_pwm: source is ext_xtal (0), rate is 24000000 sclk_csis: source is xusbxti (1), rate is 0 sclk_csis: source is xusbxti (1), rate is 0 sclk_cam0: source is xusbxti (1), rate is 0 sclk_cam1: source is xusbxti (1), rate is 0 sclk_fimc: source is xusbxti (1), rate is 0 sclk_fimc: source is xusbxti (1), rate is 0 sclk_fimc: source is xusbxti (1), rate is 0 sclk_fimc: source is xusbxti (1), rate is 0 sclk_mixer: source is sclk_dac (0), rate is 24000000 sclk_fimd0: source is xusbxti (1), rate is 0 sclk_fimd1: source is xusbxti (1), rate is 0 sclk_sata: source is mout_mpll (0), rate is 133333333 sclk_spi: source is xusbxti (1), rate is 0 sclk_spi: source is mout_mpll (6), rate is 80000000 sclk_spi: source is xusbxti (1), rate is 0 sclk_fimg2d: source is mout_g2d0 (0), rate is 100000000 PERCPU: Embedded 7 pages/cpu @c0f96000 s6528 r8192 d13952 u32768 Built 1 zonelists in Zone order, mobility grouping on. Total pages: 186944 Kernel command line: console=tty0 console=ttySAC2,115200n8 rootwait ro init=/init androidboot.console=ttySAC2 console=ttySAC2 root=/dev/mmcblk0p2 PID hash table entries: 4096 (order: 2, 16384 bytes) Dentry cache hash table entries: 131072 (order: 7, 524288 bytes) Inode-cache hash table entries: 65536 (order: 6, 262144 bytes) Memory: 736MB = 736MB total Memory: 601736k/601736k available, 151928k reserved, 0K highmem Virtual kernel memory layout: vector : 0xffff0000 - 0xffff1000 ( 4 kB) fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB) DMA : 0xfe800000 - 0xffe00000 ( 22 MB) vmalloc : 0xee800000 - 0xf6000000 ( 120 MB) lowmem : 0xc0000000 - 0xee000000 ( 736 MB) modules : 0xbf000000 - 0xc0000000 ( 16 MB) .text : 0xc0008000 - 0xc078fd14 (7712 kB) .init : 0xc0790000 - 0xc07d5980 ( 279 kB) .data : 0xc07d6000 - 0xc0835930 ( 383 kB) .bss : 0xc0835954 - 0xc098bca8 (1369 kB) Preemptible hierarchical RCU implementation. NR_IRQS:624 sched_clock: 32 bits at 50MHz, resolution 20ns, wraps every 85899ms Console: colour dummy device 80x30 console <tty0] enabled 6>console [ttySAC2] enabled console [tt<SAC2] enabled 6>Calibrating delay loop... Calibrating delay loop... <c>1992.29 BogoMIPS (lpj=4980736) 1992.29 BogoMIPS<(lpj=4980736) 6>pid_max: default: 32768 minimum: 301 pid_max: default: 32768 minimum: 301 <6>Mount-cache hash table entries: 512 Mount-cache hash table entries: 512 <6>CPU: Testing write buffer coherency: CPU: Testing write buffer coherency: ok ok <6>ftrace: allocating 19856 entries in 59 pages ftrace: allocating 19856 entries in 59 pages <6>CPU0: thread -1, cpu 0, socket 9, mpidr 80000900 CPU0: thread -1, cpu 0, socket 9, <pidr 80000900 6>Calibrating local timer... Calibrating local timer... 249.93MHz. 249.93MHz. <6>hw perfevents: enabled with ARMv7 Cortex-A9 PMU driver, 7 counters available hw perfevents: enabled with ARMv7 Cortex-A9 PMU driver, 7 counters available <6>L310 cache controller enabled L310 cache cont<oller enabled 6>l2x0: 16 ways, CACHE_ID 0x4100c4c5, AUX_CTRL 0x7e470001, Cache size: 1048576 B l2x0: 16 ways, CACHE_ID 0x4100c4c5, AUX_CTRL 0x7e470001, Cache size: 1048576 B CPU1: Booted secondary processor <2>CPU1: Unknown IPI message 0x1

12 years, 1 month

Re: Touch screen problem

by Francesco Sarasini

My touchscreen is now working by using an usb controller. the system see it as eGalax I have a problem with the lcd aoutput. The image on the screen is not centered. How can I do? are there any settings? http://i44.tinypic.com/2gv3k38.jpg Thanks Sarasini 2012/2/24 Bharathi Subramanian <bharathi.list(a)gmail.com> > No Idea. Please check about the driver support on touchscreen folder > with controller number. > > Bye :) > -- > Bharathi Subramanian >

12 years, 1 month

[ATT] Gerrit mirroring switches to use push --force by default

by Paul Sokolovsky

Hello, It seems that upstreams we mirror to our Gerrit just love to do history rewriting, so we regularly get stuff like: INFO:./git-gerrit-mirror:=== Processing: git://git.omapzoom.org (2 repositories) === INFO:./git-gerrit-mirror:Pushing in platform/hardware/ti/omap4xxx.git Everything up-to-date INFO:./git-gerrit-mirror:Pushing in kernel/omap.git remote: Resolving deltas: 0% (0/231) ^Mremote: Resolving deltas: 1% (3/231) ^Mremote: Resolving deltas: 1% (3/231) To ssh://linaro-aosp-sync-bot@gerrit-git:29418/kernel/omap-omapzoom.git cf718d5..d3c5467 p-android-omap-3.0 -> p-android-omap-3.0 ! [rejected] p-android-omap-3.1 -> p-android-omap-3.1 (non-fast-forward) error: failed to push some refs to 'ssh://linaro-aosp-sync-bot@gerrit-git:29418/kernel/omap-omapzoom.git' To prevent you from losing history, non-fast-forward updates were rejected That means that we're regularly behind in our mirror. This is not new issue, it was spotted soon after the mirror was launched (i.e. half-year ago), and I proposed to do push --force right then, but so far just run a forced push from time to time manually. Well, I guess it's time to make it automatic. What that would mean? That if you push something to an upstream branch, it will be lost soon, irrecoverably. Note that it's explicitly prohibited per our branch policy to commit anything into upstream branches, all Linaro changes should go into separate branches, named per "linaro*" pattern. And as all changes go thru Gerrit review, I guess there's almost no chance to push something in wrong branch by mistake. Still, I figure I better send a heads-up to remind of all this. (And we're waiting on Gerrit upgrade to enforce branch policy on Gerrit level). https://bugs.launchpad.net/linaro-android-infrastructure/+bug/956950 Thanks, Paul Linaro.org | Open source software for ARM SoCs Follow Linaro: http://www.facebook.com/pages/Linaro http://twitter.com/#!/linaroorg - http://www.linaro.org/linaro-blog

12 years, 1 month

2012.03 toolchain releases

by Bernhard Rosenkränzer

Builds are done -- please test: https://android-build.linaro.org/builds/~linaro-android/toolchain-4.6-2012.… https://android-build.linaro.org/builds/~linaro-android/toolchain-4.7-2012.… ttyl bero

12 years, 1 month

EEMBC AndEBench

by Michael Hope

EEMBC have announced AndEBench, a mixed native/Java benchmark for Android. It's available on the Market. I don't know much more. It seems to be CPU bound and the test names sound a bit like CoreMark. The source is available for license and might be worth the Android guys looking into. The awesome thing is they used the 2012.01 Linaro Binary toolchain release to build the native parts - see the compiler version string in the log :) -- Michael

12 years, 1 month

Gerrit SSH interface status and "SSH API" replacement?

by Paul Sokolovsky

Hello, Now that Google itself doesn't use SSH interface to Gerrit (https://android-review.googlesource.com/ssh_info), does it mean that SSH interface is deprecated, i.e. should other parties consider moving away from it? That apparently would make maintenance schedule less flexible: previously, there were separate "Gerrit admin" role which didn't require "sysadmin" (filesystem-level) access for things like DB maintenance. Another question, is there a replacement for "SSH API" like "gerrit review", "gerrit stream-events", etc.? Well, what we'd need right now is analog of "gerrit ls-projects", i.e. a stable, machine-readable way to get a list of projects in AOSP Gerrit. Any hints? Thanks, Paul Linaro.org | Open source software for ARM SoCs Follow Linaro: http://www.facebook.com/pages/Linaro http://twitter.com/#!/linaroorg - http://www.linaro.org/linaro-blog

12 years, 1 month

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linaro-android March 2012