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423 discussions

[RFC][PATCH 0/3] Strange hackbench speed-up

by Lukasz Luba

Hi, I have noticed an odd behavior in hackbench test, when developing some enhancements for thermal subsystem. It is present on ARM64 big.LITTLE (4b+4l) SoC. When hackbench runs normally after system reboot, it takes ~11sec to finish. When the module (which has locking present) is loaded and unloaded, time-to-finish is around ~6sec. The module tries to mimic the thermal framework, so everyone can experiment on local system without the need of thermal configuration. The test scenario and results are described in patch 1/3. Patch 3/3 is to narrow down the issue - mutex_unlock() call. Please apply only patch 1 and 2 and give it a try. You should see the speed-up 11s -> 6s. Then apply patch 3, rebuild the module, reboot the system, load the module, and run the test again (there should not be any improvements 11s -> 11s). I have noticed that the sequence: load the module, unload, run the test, also gives the speed-up. So there is no need to constantly touch the mutexes in the background. Any comments are welcome, esspecially for Will or Mark who where implementing low-level atomic stuff for mutexes. Tested on a few kernels (tag 4.18-rc6, EAS-next-integration_20180817_0000, some stable 4.14.x) and all are affected. Ypu can experiment with this kernel: EAS kernel branch: eas/next/integration_20180817_0000 also check tag: v4.18-rc6 url: http://linux-arm.org/git?p=linux-power.git;a=shortlog;h=refs/heads/eas/next… Regards, Lukasz Luba Lukasz Luba (3): drivers: base: add test module hackbench speedup drivers: base: add hackbench_speedup as a module drivers: hackbench_speedup: remove locking drivers/base/Makefile | 1 + drivers/base/hackbench_speedup.c | 148 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 149 insertions(+) create mode 100644 drivers/base/hackbench_speedup.c -- 2.7.4

5 years, 9 months

Arm TechCon 2018 Attendees contact list

by Maria Garcia

Hello, Hope you are doing well! I'm trying to figure out if you are interested in procuring an Attendees contact list of " Arm TechCon 2018" and there will be a cost associated with the list. Attendees: . ASIC/FPGA Engineers . Chief Hacker/Wizard . Chip Architects & Designers . CIO/CTO/CSO/CISO . IT Directors and Managers . Manager of E-Business/E-Commerce . Design & Development Engineers . Embedded Software Engineers . Hardware Engineers . OEM System Designer . Operator/Carrier . Software Architects Developers & Engineers . App and Game Developers . System Design and Processor Design Engineers . System Architect, Systems Analyst . VP/Director of Hardware Engineering . VP/Director of Software Engineering This list comes with full contact details like: Contact Name, Title, Company Name, Size, Physical Address, Opt-In Email address, Phone & Fax numbers and etc. Please let me know your interest to send you the number of attendees and cost for your review. Looking forward for your response. Thanks & Regards, Maria.garcia If you wish to not to receive further emails, change the subject line to Unsubscribe

5 years, 9 months

[Integration Branch] Update 14-September-2018

by Douglas Raillard

Hi, A new EAS integration branch created for September 14th is available on branch eas/next/integration here: http://linux-arm.org/git?p=linux-power.git For further information about main features, test coverage and work items for next integration please have a look at: https://developer.arm.com/open-source/energy-aware-scheduling/eas-mainline-… Best Regards, Douglas

5 years, 9 months

EAS behavior and lack of idle states in SoC

by Lukasz Luba

Hi ARM folks! I have some work to do with EAS + IPA. I have a platform with arm64 4 big + 4 LITTLE that will hopefully get EAS and IPA (when I solve some thermal issues). Unfortunately, in this SoC and code we don't have idle states (new SoCs will just get normal psci support). I run different kernel versions, also your latest integration-next (after dropping whole /drivers/usb because the changes in that branch broke it). Have you ever tried to evaluate EAS on a platform which has only WFI idle? Do you know what could be the impact on the EAS? I have some other thought and issues to discuss regarding EAS (migrations, load balancing, etc) but this question regarding idle is probably fundamental. Cheers, Lukasz Luba

5 years, 9 months

[Integration Branch] Update 31-August-2018

by Douglas Raillard

Hi, A new EAS integration branch created for August 31st is available on branch eas/next/integration here: http://linux-arm.org/git?p=linux-power.git For further information about main features, test coverage and work items for next integration please have a look at: https://developer.arm.com/open-source/energy-aware-scheduling/eas-mainline-… Best Regards, Douglas

5 years, 10 months

[Integration Branch] Update 17-August-2018

by Douglas Raillard

Hi, A new EAS integration branch created for August 17th is available on branch eas/next/integration here: http://linux-arm.org/git?p=linux-power.git For further information about main features, test coverage and work items for next integration please have a look at: https://developer.arm.com/open-source/energy-aware-scheduling/eas-mainline-… Best Regards, Douglas

5 years, 10 months

4.18 update to experimental/eas-dev for Android development

by Quentin Perret

Hi all, The 'experimental/eas-dev' branch (which holds the candidate EAS patches for the next Android Kernel version) has been updated to Linux 4.18: https://android.googlesource.com/kernel/common exprimental/eas-dev All the EAS patches are also available as part of the Android stack maintained by Amit Pundir in the 'android-mainline-tracking' branch available on AOSP. If you wish to contribute patches to EAS that you think are Android-specific, please do so by posting them to AOSP Gerrit against the 'experimental/eas-dev' branch. The branch will be rebased and force-pushed at each kernel release (e.g. 4.18, 4.19), hence maintaining a clean stack of patches that will be used during the creation of the next Android Common Kernel. For more details about the contribution process to EAS, please refer to the Arm developer website [1]. Cheers, Quentin [1] https://developer.arm.com/open-source/energy-aware-scheduling/contributing-…

5 years, 10 months

[Integration Branch] Update 03-August-2018

by Douglas Raillard

Hi, A new EAS integration branch created for August 3rd is available on branch eas/next/integration here: http://linux-arm.org/git?p=linux-power.git For further information about main features, test coverage and work items for next integration please have a look at: https://developer.arm.com/open-source/energy-aware-scheduling/eas-mainline-… Best Regards, Douglas

5 years, 11 months

Computing the dynamic-power-coefficient on Exynos5422

by Oliver Effland

Hi, First of all: thanks for all the valuable input! @(Russell, Dietmar & Steven) On 07/23/2018 08:51 AM, Steven Miao wrote: > Hi Oliver, > > Generally these dynamic co-efficiency and static leakage power comes > from hardware design team by running power estimation tool, however > you can tun these co-efficiency and parameters for better performance. > > How did you get A7 or A15 power? Get Soc power or there's separate > sensor for A7/A15? Yes indeed, there are 2 seperate sensors for the A7 and A15. > If you want to create cpu busy power model manually, you can: > 1 leave 1 A7 + 1 A15 core online, keep other cores offline, disable > thermal zone, disable idle state for all cores > 2 set A7 frequency to 200Mhz, move all the task to A15, run cpu > intensive task on A7(dhrystone, sysbench cpu test), read sensor to get > 1 A7 power P1(read from A7 cluster sensor) > 3 online 2 A7 core, run dhrystone on each core, and get power P2 > > we can get 1 A7 core power@200Mhz ~= P2 - P1 (A7 power X 2 + static > power - A7 power X 1 - static power I followed your manual steps (using a busy loop for 10s, instead of a benchmark) and corrected my calculations (with the static power in mind): A7: freq(MHz) voltage(mV) Power(mW) A7_Power(mW) Stat_Power(mW) DPC 200 918.750 34.768 12.203 10.362 72.283955 400 920.000 60.805 21.25 18.305 62.765831 600 968.750 98.046 35.084 27.878 62.306652 800 1042.500 148.095 52.285 43.525 60.136063 1000 1116.250 212.214 76.112 59.99 61.084382 1200 1190.000 288.958 99.993 88.972 58.842948 1400 1288.750 411.936 144.807 122.322 62.276495 mean: 62 A15: freq(MHz) voltage(mV) Power(mW) A15_Power(mW) Stat_Power(mW) DPC 200 916250 122.584 31.139 60.306 185.458477 500 916250 225.101 68.774 87.553 163.842401 800 942500 349.158 112.432 124.294 158.211202 1100 1016250 540.78 169.556 201.668 149.251725 1400 1078750 779.19 258.214 262.762 158.493016 1700 1180000 1179.344 392.107 395.13 165.650083 2000 1320000 1969.764 648.768 672.228 186.170798 mean: 164 The ratio between A15 and A7 is now 164/62 = 2.645 I hope the dynamic-power-coefficient's are more accurate now? > dynamic-power-coefficient ~= 400 - 500 is reasonable for big core > dynamic-power-coefficient ~= 100 is reasonable for LITTLE core. > For IPA it can work effectively with a poor power model(not so > accurate), for EAS it just need power model of LITTLE core and big > core is proportional. I'm guessing my values differ from your suggested values, because it's 32bit ARM? Best regards, Oliver

5 years, 11 months

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5 years, 11 months

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