Linaro-acpi July 2013

linaro-acpi@lists.linaro.org

12 participants
30 discussions

[RFC][PATCH 1/2] ARM64: add cpu topology definition

by Hanjun Guo

Power aware scheduling needs the cpu topology information to improve the cpu scheduler decision making. For ARM64, we can get the topology from the MPIDR register which defines the the affinity of processors. This patch is mainly based on arch/arm/kernel/topology.c written by Vincent Guittot, and replaced the topology array with per cpu variable. Signed-off-by: Hanjun Guo <hanjun.guo(a)linaro.org> --- arch/arm64/Kconfig | 9 +++ arch/arm64/include/asm/cputype.h | 11 ++++ arch/arm64/include/asm/topology.h | 41 ++++++++++++ arch/arm64/kernel/Makefile | 1 + arch/arm64/kernel/smp.c | 6 ++ arch/arm64/kernel/topology.c | 128 +++++++++++++++++++++++++++++++++++++ 6 files changed, 196 insertions(+) create mode 100644 arch/arm64/include/asm/topology.h create mode 100644 arch/arm64/kernel/topology.c diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 9737e97..f0ce91b 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -150,6 +150,15 @@ config SMP If you don't know what to do here, say N. +config ARM64_CPU_TOPOLOGY + bool "Support cpu topology definition" + depends on SMP && ARM64 + default y + help + Support ARM64 cpu topology definition. The MPIDR register defines + affinity between processors which is then used to describe the cpu + topology of an ARM64 System. + config NR_CPUS int "Maximum number of CPUs (2-32)" range 2 32 diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index 5fe138e..68b55af 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -30,6 +30,17 @@ #define MPIDR_HWID_BITMASK 0xff00ffffff +#define MPIDR_SMP_BITMASK (0x1 << 30) +#define MPIDR_MT_BITMASK (0x1 << 24) + +#define MPIDR_LEVEL_BITS 8 +#define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1) + +#define MPIDR_AFFINITY_LEVEL_0(mpidr) ((mpidr) & MPIDR_LEVEL_MASK) +#define MPIDR_AFFINITY_LEVEL_1(mpidr) ((mpidr >> 8) & MPIDR_LEVEL_MASK) +#define MPIDR_AFFINITY_LEVEL_2(mpidr) ((mpidr >> 16) & MPIDR_LEVEL_MASK) +#define MPIDR_AFFINITY_LEVEL_3(mpidr) ((mpidr >> 32) & MPIDR_LEVEL_MASK) + #define read_cpuid(reg) ({ \ u64 __val; \ asm("mrs %0, " reg : "=r" (__val)); \ diff --git a/arch/arm64/include/asm/topology.h b/arch/arm64/include/asm/topology.h new file mode 100644 index 0000000..8631808 --- /dev/null +++ b/arch/arm64/include/asm/topology.h @@ -0,0 +1,41 @@ +#ifndef _ASM_ARM64_TOPOLOGY_H +#define _ASM_ARM64_TOPOLOGY_H + +#ifdef CONFIG_ARM64_CPU_TOPOLOGY + +#include <linux/cpumask.h> + +struct cputopo_arm64 { + int thread_id; + int core_id; + int socket_id; + cpumask_t thread_sibling; + cpumask_t core_sibling; +}; + +DECLARE_PER_CPU(struct cputopo_arm64, cpu_topology); + +#define cpu_topo(cpu) per_cpu(cpu_topology, cpu) + +#define topology_physical_package_id(cpu) (cpu_topo(cpu).socket_id) +#define topology_core_id(cpu) (cpu_topo(cpu).core_id) +#define topology_core_cpumask(cpu) (&cpu_topo(cpu).core_sibling) +#define topology_thread_cpumask(cpu) (&cpu_topo(cpu).thread_sibling) + +#define mc_capable() (cpu_topo(0).socket_id != -1) +#define smt_capable() (cpu_topo(0).thread_id != -1) + +void init_cpu_topology(void); +void store_cpu_topology(unsigned int cpuid); +const struct cpumask *cpu_coregroup_mask(int cpu); + +#else + +static inline void init_cpu_topology(void) { } +static inline void store_cpu_topology(unsigned int cpuid) { } + +#endif + +#include <asm-generic/topology.h> + +#endif /* _ASM_ARM64_TOPOLOGY_H */ diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile index 7b4b564..a47c359 100644 --- a/arch/arm64/kernel/Makefile +++ b/arch/arm64/kernel/Makefile @@ -18,6 +18,7 @@ arm64-obj-$(CONFIG_SMP) += smp.o smp_spin_table.o smp_psci.o arm64-obj-$(CONFIG_HW_PERF_EVENTS) += perf_event.o arm64-obj-$(CONFIG_HAVE_HW_BREAKPOINT)+= hw_breakpoint.o arm64-obj-$(CONFIG_EARLY_PRINTK) += early_printk.o +arm64-obj-$(CONFIG_ARM64_CPU_TOPOLOGY) += topology.o obj-y += $(arm64-obj-y) vdso/ obj-m += $(arm64-obj-m) diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c index fee5cce..197b1da 100644 --- a/arch/arm64/kernel/smp.c +++ b/arch/arm64/kernel/smp.c @@ -39,6 +39,7 @@ #include <asm/atomic.h> #include <asm/cacheflush.h> #include <asm/cputype.h> +#include <asm/topology.h> #include <asm/mmu_context.h> #include <asm/pgtable.h> #include <asm/pgalloc.h> @@ -215,6 +216,8 @@ asmlinkage void secondary_start_kernel(void) local_irq_enable(); local_fiq_enable(); + store_cpu_topology(cpu); + /* * OK, it's off to the idle thread for us */ @@ -387,6 +390,9 @@ void __init smp_prepare_cpus(unsigned int max_cpus) int cpu, err; unsigned int ncores = num_possible_cpus(); + init_cpu_topology(); + store_cpu_topology(smp_processor_id()); + /* * are we trying to boot more cores than exist? */ diff --git a/arch/arm64/kernel/topology.c b/arch/arm64/kernel/topology.c new file mode 100644 index 0000000..1eb0435 --- /dev/null +++ b/arch/arm64/kernel/topology.c @@ -0,0 +1,128 @@ +/* + * arch/arm64/kernel/topology.c + * + * Copyright (C) 2013 Linaro Limited. + * Written by: Hanjun Guo + * + * based on arch/arm/kernel/topology.c + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ + +#include <linux/cpu.h> +#include <linux/cpumask.h> +#include <linux/init.h> +#include <linux/percpu.h> +#include <linux/sched.h> + +#include <asm/cputype.h> +#include <asm/topology.h> + +DEFINE_PER_CPU(struct cputopo_arm64, cpu_topology); + +const struct cpumask *cpu_coregroup_mask(int cpu) +{ + return &cpu_topo(cpu).core_sibling; +} + +void update_siblings_masks(unsigned int cpuid) +{ + struct cputopo_arm64 *topo, *cpuid_topo = &cpu_topo(cpuid); + int cpu; + + /* update core and thread sibling masks */ + for_each_possible_cpu(cpu) { + topo = &cpu_topo(cpu); + + if (cpuid_topo->socket_id != topo->socket_id) + continue; + + cpumask_set_cpu(cpuid, &topo->core_sibling); + if (cpu != cpuid) + cpumask_set_cpu(cpu, &cpuid_topo->core_sibling); + + if (cpuid_topo->core_id != topo->core_id) + continue; + + cpumask_set_cpu(cpuid, &topo->thread_sibling); + if (cpu != cpuid) + cpumask_set_cpu(cpu, &cpuid_topo->thread_sibling); + } + smp_wmb(); +} + +/* + * store_cpu_topology is called at boot when only one cpu is running + * and with the mutex cpu_hotplug.lock locked, when several cpus have booted, + * which prevents simultaneous write access to cpu_topology array + */ +void store_cpu_topology(unsigned int cpuid) +{ + struct cputopo_arm64 *cpuid_topo = &cpu_topo(cpuid); + u64 mpidr; + + /* If the cpu topology has been already set, just return */ + if (cpuid_topo->core_id != -1) + return; + + mpidr = read_cpuid_mpidr(); + + /* create cpu topology mapping */ + if (!(mpidr & MPIDR_SMP_BITMASK)) { + /* + * This is a multiprocessor system + * multiprocessor format & multiprocessor mode field are set + */ + + if (mpidr & MPIDR_MT_BITMASK) { + /* core performance interdependency */ + cpuid_topo->thread_id = MPIDR_AFFINITY_LEVEL_0(mpidr); + cpuid_topo->core_id = MPIDR_AFFINITY_LEVEL_1(mpidr); + cpuid_topo->socket_id = MPIDR_AFFINITY_LEVEL_2(mpidr); + } else { + /* largely independent cores */ + cpuid_topo->thread_id = -1; + cpuid_topo->core_id = MPIDR_AFFINITY_LEVEL_0(mpidr); + cpuid_topo->socket_id = MPIDR_AFFINITY_LEVEL_1(mpidr); + } + } else { + /* + * This is an uniprocessor system + * we are in multiprocessor format but uniprocessor system + * or in the old uniprocessor format + */ + cpuid_topo->thread_id = -1; + cpuid_topo->core_id = 0; + cpuid_topo->socket_id = -1; + } + + update_siblings_masks(cpuid); + + printk(KERN_INFO "CPU%u: thread %d, cpu %d, socket %d, mpidr 0x%llx\n", + cpuid, cpu_topo(cpuid).thread_id, + cpu_topo(cpuid).core_id, + cpu_topo(cpuid).socket_id, mpidr); +} + +/* + * init_cpu_topology is called at boot when only one cpu is running + * which prevent simultaneous write access to cpu_topology array + */ +void __init init_cpu_topology(void) +{ + unsigned int cpu; + + /* init core mask */ + for_each_possible_cpu(cpu) { + struct cputopo_arm64 *topo = &cpu_topo(cpu); + + topo->thread_id = -1; + topo->core_id = -1; + topo->socket_id = -1; + cpumask_clear(&topo->core_sibling); + cpumask_clear(&topo->thread_sibling); + } + smp_wmb(); +} -- 1.7.9.5

11 years, 10 months

[PATCH -v2] ARM64: Add cpu topology definition

by Hanjun Guo

Power aware scheduling needs the cpu topology information to improve the cpu scheduler decision making. sched_mc and sched_smt will use the topology information. For ARM64, we can get the topology from the MPIDR register which defines the the affinity of processors. This patch is mainly based on arch/arm/kernel/topology.c written by Vincent Guittot, and replaced the topology array with per cpu variable. v2: Make the changelog easier to understand. Use 'u64' for MPIDR value on arm64. Some typo fix. Signed-off-by: Hanjun Guo <hanjun.guo(a)linaro.org> --- arch/arm64/Kconfig | 25 ++++++++ arch/arm64/include/asm/cputype.h | 11 ++++ arch/arm64/include/asm/topology.h | 35 +++++++++++ arch/arm64/kernel/Makefile | 5 +- arch/arm64/kernel/smp.c | 6 ++ arch/arm64/kernel/topology.c | 120 +++++++++++++++++++++++++++++++++++++ 6 files changed, 198 insertions(+), 4 deletions(-) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index c967b11..67c1c53 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -144,6 +144,31 @@ config SMP If you don't know what to do here, say N. +config ARM64_CPU_TOPOLOGY + bool "Support cpu topology definition" + depends on SMP && ARM64 + default y + help + Support ARM64 cpu topology definition. The MPIDR register defines + affinity between processors which is then used to describe the cpu + topology of an ARM64 System. + +config SCHED_MC + bool "Multi-core scheduler support" + depends on ARM64_CPU_TOPOLOGY + help + Multi-core scheduler support improves the CPU scheduler's decision + making when dealing with multi-core CPU chips at a cost of slightly + increased overhead in some places. If unsure say N here. + +config SCHED_SMT + bool "SMT scheduler support" + depends on ARM64_CPU_TOPOLOGY + help + Improves the CPU scheduler's decision making when dealing with + MultiThreading at a cost of slightly increased overhead in some + places. If unsure say N here. + config NR_CPUS int "Maximum number of CPUs (2-32)" range 2 32 diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index cf27494..ef7e682 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -30,6 +30,17 @@ #define MPIDR_HWID_BITMASK 0xff00ffffff +#define MPIDR_SMP_BITMASK (0x1 << 30) +#define MPIDR_MT_BITMASK (0x1 << 24) + +#define MPIDR_LEVEL_BITS 8 +#define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1) + +#define MPIDR_AFFINITY_LEVEL_0(mpidr) ((mpidr) & MPIDR_LEVEL_MASK) +#define MPIDR_AFFINITY_LEVEL_1(mpidr) ((mpidr >> 8) & MPIDR_LEVEL_MASK) +#define MPIDR_AFFINITY_LEVEL_2(mpidr) ((mpidr >> 16) & MPIDR_LEVEL_MASK) +#define MPIDR_AFFINITY_LEVEL_3(mpidr) ((mpidr >> 32) & MPIDR_LEVEL_MASK) + #define read_cpuid(reg) ({ \ u64 __val; \ asm("mrs %0, " reg : "=r" (__val)); \ diff --git a/arch/arm64/include/asm/topology.h b/arch/arm64/include/asm/topology.h index 22c9421..06440d4 100644 --- a/arch/arm64/include/asm/topology.h +++ b/arch/arm64/include/asm/topology.h @@ -1,8 +1,43 @@ #ifndef _ASM_ARM64_TOPOLOGY_H #define _ASM_ARM64_TOPOLOGY_H +#ifdef CONFIG_ARM64_CPU_TOPOLOGY + +#include <linux/cpumask.h> + +struct cputopo_arm64 { + int thread_id; + int core_id; + int socket_id; + cpumask_t thread_sibling; + cpumask_t core_sibling; +}; + +DECLARE_PER_CPU(struct cputopo_arm64, cpu_topology); + +#define cpu_topo(cpu) per_cpu(cpu_topology, cpu) + +#define topology_physical_package_id(cpu) (cpu_topo(cpu).socket_id) +#define topology_core_id(cpu) (cpu_topo(cpu).core_id) +#define topology_core_cpumask(cpu) (&cpu_topo(cpu).core_sibling) +#define topology_thread_cpumask(cpu) (&cpu_topo(cpu).thread_sibling) + +#define mc_capable() (cpu_topo(0).socket_id != -1) +#define smt_capable() (cpu_topo(0).thread_id != -1) + +void init_cpu_topology(void); +void store_cpu_topology(unsigned int cpuid); +const struct cpumask *cpu_coregroup_mask(int cpu); void arch_fix_phys_package_id(int num, u32 slot); +#else + +static inline void arch_fix_phys_package_id(int num, u32 slot) {} +static inline void init_cpu_topology(void) { } +static inline void store_cpu_topology(unsigned int cpuid) { } + +#endif + #include <asm-generic/topology.h> #endif /* _ASM_ARM64_TOPOLOGY_H */ diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile index c5e29d5..a47c359 100644 --- a/arch/arm64/kernel/Makefile +++ b/arch/arm64/kernel/Makefile @@ -18,6 +18,7 @@ arm64-obj-$(CONFIG_SMP) += smp.o smp_spin_table.o smp_psci.o arm64-obj-$(CONFIG_HW_PERF_EVENTS) += perf_event.o arm64-obj-$(CONFIG_HAVE_HW_BREAKPOINT)+= hw_breakpoint.o arm64-obj-$(CONFIG_EARLY_PRINTK) += early_printk.o +arm64-obj-$(CONFIG_ARM64_CPU_TOPOLOGY) += topology.o obj-y += $(arm64-obj-y) vdso/ obj-m += $(arm64-obj-m) @@ -27,7 +28,3 @@ extra-y := $(head-y) vmlinux.lds # vDSO - this must be built first to generate the symbol offsets $(call objectify,$(arm64-obj-y)): $(obj)/vdso/vdso-offsets.h $(obj)/vdso/vdso-offsets.h: $(obj)/vdso - -# Hack for now -obj-y += topology.o - diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c index 5ec1723..36d09fe 100644 --- a/arch/arm64/kernel/smp.c +++ b/arch/arm64/kernel/smp.c @@ -39,6 +39,7 @@ #include <asm/atomic.h> #include <asm/cacheflush.h> #include <asm/cputype.h> +#include <asm/topology.h> #include <asm/mmu_context.h> #include <asm/pgtable.h> #include <asm/pgalloc.h> @@ -206,6 +207,8 @@ asmlinkage void __cpuinit secondary_start_kernel(void) local_irq_enable(); local_fiq_enable(); + store_cpu_topology(cpu); + /* * OK, now it's safe to let the boot CPU continue. Wait for * the CPU migration code to notice that the CPU is online @@ -407,6 +410,9 @@ void __init smp_prepare_cpus(unsigned int max_cpus) int cpu, err; unsigned int ncores = num_possible_cpus(); + init_cpu_topology(); + store_cpu_topology(smp_processor_id()); + /* * are we trying to boot more cores than exist? */ diff --git a/arch/arm64/kernel/topology.c b/arch/arm64/kernel/topology.c index 5c8e69c..947fcc2 100644 --- a/arch/arm64/kernel/topology.c +++ b/arch/arm64/kernel/topology.c @@ -1,3 +1,16 @@ +/* + * arch/arm64/kernel/topology.c + * + * Copyright (C) 2013 Linaro Limited. + * Written by: Hanjun Guo + * + * based on arch/arm/kernel/topology.c + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ + #include <linux/cpu.h> #include <linux/cpumask.h> #include <linux/export.h> @@ -13,6 +26,113 @@ #include <asm/topology.h> #include <asm/cpu.h> +DEFINE_PER_CPU(struct cputopo_arm64, cpu_topology); + +const struct cpumask *cpu_coregroup_mask(int cpu) +{ + return &cpu_topo(cpu).core_sibling; +} + +void update_siblings_masks(unsigned int cpuid) +{ + struct cputopo_arm64 *topo, *cpuid_topo = &cpu_topo(cpuid); + int cpu; + + /* update core and thread sibling masks */ + for_each_possible_cpu(cpu) { + topo = &cpu_topo(cpu); + + if (cpuid_topo->socket_id != topo->socket_id) + continue; + + cpumask_set_cpu(cpuid, &topo->core_sibling); + if (cpu != cpuid) + cpumask_set_cpu(cpu, &cpuid_topo->core_sibling); + + if (cpuid_topo->core_id != topo->core_id) + continue; + + cpumask_set_cpu(cpuid, &topo->thread_sibling); + if (cpu != cpuid) + cpumask_set_cpu(cpu, &cpuid_topo->thread_sibling); + } + smp_wmb(); +} + +/* + * store_cpu_topology is called at boot when only one cpu is running + * and with the mutex cpu_hotplug.lock locked, when several cpus have booted, + * which prevents simultaneous write access to cpu_topology array + */ +void store_cpu_topology(unsigned int cpuid) +{ + struct cputopo_arm64 *cpuid_topo = &cpu_topo(cpuid); + u64 mpidr; + + /* If the cpu topology has been already set, just return */ + if (cpuid_topo->core_id != -1) + return; + + mpidr = read_cpuid_mpidr(); + + /* create cpu topology mapping */ + if (!(mpidr & MPIDR_SMP_BITMASK)) { + /* + * This is a multiprocessor system + * multiprocessor format & multiprocessor mode field are set + */ + + if (mpidr & MPIDR_MT_BITMASK) { + /* core performance interdependency */ + cpuid_topo->thread_id = MPIDR_AFFINITY_LEVEL_0(mpidr); + cpuid_topo->core_id = MPIDR_AFFINITY_LEVEL_1(mpidr); + cpuid_topo->socket_id = MPIDR_AFFINITY_LEVEL_2(mpidr); + } else { + /* largely independent cores */ + cpuid_topo->thread_id = -1; + cpuid_topo->core_id = MPIDR_AFFINITY_LEVEL_0(mpidr); + cpuid_topo->socket_id = MPIDR_AFFINITY_LEVEL_1(mpidr); + } + } else { + /* + * This is an uniprocessor system + * we are in multiprocessor format but uniprocessor system + * or in the old uniprocessor format + */ + cpuid_topo->thread_id = -1; + cpuid_topo->core_id = 0; + cpuid_topo->socket_id = -1; + } + + update_siblings_masks(cpuid); + + pr_info("CPU%u: thread %d, cpu %d, socket %d, mpidr 0x%llx\n", + cpuid, cpu_topo(cpuid).thread_id, + cpu_topo(cpuid).core_id, + cpu_topo(cpuid).socket_id, mpidr); +} + +/* + * init_cpu_topology is called at boot when only one cpu is running + * which prevent simultaneous write access to cpu_topology array + */ +void __init init_cpu_topology(void) +{ + unsigned int cpu; + + /* init core mask */ + for_each_possible_cpu(cpu) { + struct cputopo_arm64 *topo = &cpu_topo(cpu); + + topo->thread_id = -1; + topo->core_id = -1; + topo->socket_id = -1; + cpumask_clear(&topo->core_sibling); + cpumask_clear(&topo->thread_sibling); + } + smp_wmb(); +} + void arch_fix_phys_package_id(int num, u32 slot) { } -- 1.7.9.5

11 years, 10 months

[PATCH] Add in a dummy platform in ASL

by al.stone＠linaro.org

From: Al Stone <al.stone(a)linaro.org> Add in a dummy platform intended as essentially null tables to be used in testing only. The intent is to put into the tables only what is needed to know we can load and initialize ACPI, but configure nothing. Signed-off-by: Al Stone <al.stone(a)linaro.org> --- platforms/dummy.acpi/.gitignore | 3 + platforms/dummy.acpi/apic.asl | 133 +++++++++++++++++ platforms/dummy.acpi/asf!.asl | 80 +++++++++++ platforms/dummy.acpi/bert.asl | 21 +++ platforms/dummy.acpi/bgrt.asl | 25 ++++ platforms/dummy.acpi/boot.asl | 21 +++ platforms/dummy.acpi/cpep.asl | 26 ++++ platforms/dummy.acpi/csrt.asl | 143 +++++++++++++++++++ platforms/dummy.acpi/dbgp.asl | 29 ++++ platforms/dummy.acpi/dmar.asl | 68 +++++++++ platforms/dummy.acpi/dsdt.asl | 17 +++ platforms/dummy.acpi/dummy.manifest | 34 +++++ platforms/dummy.acpi/ecdt.asl | 37 +++++ platforms/dummy.acpi/einj.asl | 151 ++++++++++++++++++++ platforms/dummy.acpi/erst.asl | 278 ++++++++++++++++++++++++++++++++++++ platforms/dummy.acpi/facp.asl | 167 ++++++++++++++++++++++ platforms/dummy.acpi/facs.asl | 21 +++ platforms/dummy.acpi/fpdt.asl | 35 +++++ platforms/dummy.acpi/gtdt.asl | 42 ++++++ platforms/dummy.acpi/hest.asl | 193 +++++++++++++++++++++++++ platforms/dummy.acpi/hpet.asl | 33 +++++ platforms/dummy.acpi/ivrs.asl | 86 +++++++++++ platforms/dummy.acpi/mcfg.asl | 26 ++++ platforms/dummy.acpi/mchi.asl | 38 +++++ platforms/dummy.acpi/mpst.asl | 87 +++++++++++ platforms/dummy.acpi/msct.asl | 51 +++++++ platforms/dummy.acpi/oem0.asl | 18 +++ platforms/dummy.acpi/pmtt.asl | 105 ++++++++++++++ platforms/dummy.acpi/rsdp.asl | 17 +++ platforms/dummy.acpi/rsdt.asl | 20 +++ platforms/dummy.acpi/s3pt.asl | 26 ++++ platforms/dummy.acpi/sbst.asl | 22 +++ platforms/dummy.acpi/slic.asl | 56 ++++++++ platforms/dummy.acpi/slit.asl | 60 ++++++++ platforms/dummy.acpi/spcr.asl | 46 ++++++ platforms/dummy.acpi/spmi.asl | 40 ++++++ platforms/dummy.acpi/srat.asl | 57 ++++++++ platforms/dummy.acpi/ssdt0.asl | 17 +++ platforms/dummy.acpi/tcpa.asl | 22 +++ platforms/dummy.acpi/tpm2.asl | 22 +++ platforms/dummy.acpi/uefi.asl | 21 +++ platforms/dummy.acpi/waet.asl | 22 +++ platforms/dummy.acpi/wdat.asl | 47 ++++++ platforms/dummy.acpi/wddt.asl | 44 ++++++ platforms/dummy.acpi/wdrt.asl | 42 ++++++ platforms/dummy.acpi/xsdt.asl | 39 +++++ 46 files changed, 2588 insertions(+) create mode 100644 platforms/dummy.acpi/.gitignore create mode 100644 platforms/dummy.acpi/apic.asl create mode 100644 platforms/dummy.acpi/asf!.asl create mode 100644 platforms/dummy.acpi/bert.asl create mode 100644 platforms/dummy.acpi/bgrt.asl create mode 100644 platforms/dummy.acpi/boot.asl create mode 100644 platforms/dummy.acpi/cpep.asl create mode 100644 platforms/dummy.acpi/csrt.asl create mode 100644 platforms/dummy.acpi/dbgp.asl create mode 100644 platforms/dummy.acpi/dmar.asl create mode 100644 platforms/dummy.acpi/dsdt.asl create mode 100644 platforms/dummy.acpi/dummy.manifest create mode 100644 platforms/dummy.acpi/ecdt.asl create mode 100644 platforms/dummy.acpi/einj.asl create mode 100644 platforms/dummy.acpi/erst.asl create mode 100644 platforms/dummy.acpi/facp.asl create mode 100644 platforms/dummy.acpi/facs.asl create mode 100644 platforms/dummy.acpi/fpdt.asl create mode 100644 platforms/dummy.acpi/gtdt.asl create mode 100644 platforms/dummy.acpi/hest.asl create mode 100644 platforms/dummy.acpi/hpet.asl create mode 100644 platforms/dummy.acpi/ivrs.asl create mode 100644 platforms/dummy.acpi/mcfg.asl create mode 100644 platforms/dummy.acpi/mchi.asl create mode 100644 platforms/dummy.acpi/mpst.asl create mode 100644 platforms/dummy.acpi/msct.asl create mode 100644 platforms/dummy.acpi/oem0.asl create mode 100644 platforms/dummy.acpi/pmtt.asl create mode 100644 platforms/dummy.acpi/rsdp.asl create mode 100644 platforms/dummy.acpi/rsdt.asl create mode 100644 platforms/dummy.acpi/s3pt.asl create mode 100644 platforms/dummy.acpi/sbst.asl create mode 100644 platforms/dummy.acpi/slic.asl create mode 100644 platforms/dummy.acpi/slit.asl create mode 100644 platforms/dummy.acpi/spcr.asl create mode 100644 platforms/dummy.acpi/spmi.asl create mode 100644 platforms/dummy.acpi/srat.asl create mode 100644 platforms/dummy.acpi/ssdt0.asl create mode 100644 platforms/dummy.acpi/tcpa.asl create mode 100644 platforms/dummy.acpi/tpm2.asl create mode 100644 platforms/dummy.acpi/uefi.asl create mode 100644 platforms/dummy.acpi/waet.asl create mode 100644 platforms/dummy.acpi/wdat.asl create mode 100644 platforms/dummy.acpi/wddt.asl create mode 100644 platforms/dummy.acpi/wdrt.asl create mode 100644 platforms/dummy.acpi/xsdt.asl diff --git a/platforms/dummy.acpi/.gitignore b/platforms/dummy.acpi/.gitignore new file mode 100644 index 0000000..9585b50 --- /dev/null +++ b/platforms/dummy.acpi/.gitignore @@ -0,0 +1,3 @@ +*.aml +*.lst +*.acpi diff --git a/platforms/dummy.acpi/apic.asl b/platforms/dummy.acpi/apic.asl new file mode 100644 index 0000000..5784017 --- /dev/null +++ b/platforms/dummy.acpi/apic.asl @@ -0,0 +1,133 @@ +/* + * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org> + * + * [APIC] Multiple APIC Description Table (MADT) + * Format: [ByteLength] FieldName : HexFieldValue + * + * This source is released under the terms of the GPLv2. + */ + +[0004] Signature : "APIC" +[0004] Table Length : 000000F6 +[0001] Revision : 01 +[0001] Checksum : B0 +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "DUMMY " +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20110623 + +[0004] Local Apic Address : 00000000 +[0004] Flags (decoded below) : 00000001 + PC-AT Compatibility : 1 + +[0001] Subtable Type : 00 [Processor Local APIC] +[0001] Length : 08 +[0001] Processor ID : 00 +[0001] Local Apic ID : 00 +[0004] Flags (decoded below) : 00000001 + Processor Enabled : 1 + +[0001] Subtable Type : 01 [I/O APIC] +[0001] Length : 0C +[0001] I/O Apic ID : 01 +[0001] Reserved : 00 +[0004] Address : 00000000 +[0004] Interrupt : 00000000 + +[0001] Subtable Type : 02 [Interrupt Source Override] +[0001] Length : 0A +[0001] Bus : 00 +[0001] Source : 00 +[0004] Interrupt : 00000000 +[0002] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 + +[0001] Subtable Type : 03 [NMI Source] +[0001] Length : 08 +[0002] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 +[0004] Interrupt : 00000001 + +[0001] Subtable Type : 04 [Local APIC NMI] +[0001] Length : 06 +[0001] Processor ID : 00 +[0002] Flags (decoded below) : 0005 + Polarity : 1 + Trigger Mode : 1 +[0001] Interrupt Input LINT : 01 + +[0001] Subtable Type : 05 [Local APIC Address Override] +[0001] Length : 0C +[0002] Reserved : 0000 +[0008] APIC Address : 0000000000000000 + +[0001] Subtable Type : 06 [I/O SAPIC] +[0001] Length : 10 +[0001] I/O Sapic ID : 00 +[0001] Reserved : 00 +[0004] Interrupt Base : 00000000 +[0008] Address : 0000000000000000 + +[0001] Subtable Type : 07 [Local SAPIC] +[0001] Length : 16 +[0001] Processor ID : 00 +[0001] Local Sapic ID : 00 +[0001] Local Sapic EID : 00 +[0003] Reserved : 000000 +[0004] Flags (decoded below) : 00000001 + Processor Enabled : 1 +[0004] Processor UID : 00000000 +[0006] Processor UID String : "\CPU0" + +[0001] Subtable Type : 08 [Platform Interrupt Sources] +[0001] Length : 10 +[0002] Flags (decoded below) : 0005 + Polarity : 1 + Trigger Mode : 1 +[0001] InterruptType : 00 +[0001] Processor ID : 00 +[0001] Processor EID : 00 +[0001] I/O Sapic Vector : 00 +[0004] Interrupt : 00000001 +[0004] Flags (decoded below) : 00000001 + CPEI Override : 1 + +[0001] Subtable Type : 09 [Processor Local x2APIC] +[0001] Length : 10 +[0002] Reserved : 0000 +[0004] Processor x2Apic ID : 00000000 +[0004] Flags (decoded below) : 00000001 + Processor Enabled : 1 +[0004] Processor UID : 00000000 + +[0001] Subtable Type : 0A [Local x2APIC NMI] +[0001] Length : 0C +[0002] Flags (decoded below) : 0005 + Polarity : 1 + Trigger Mode : 1 +[0004] Processor UID : 00000000 +[0001] Interrupt Input LINT : 00 +[0003] Reserved : 000000 + +[0001] Subtable Type : 0B [Generic Interrupt Controller] +[0001] Length : 28 +[0002] Reserved : 0000 +[0004] Local GIC Hardware ID : 00000000 +[0004] Processor UID : 00000000 +[0004] Flags (decoded below) : 00000001 + Processor Enabled : 1 +[0004] Parking Protocol Version : 00000000 +[0004] Performance Interrupt : 00000000 +[0008] Parked Address : 0000000000000000 +[0008] Base Address : 0000000000000000 + +[0001] Subtable Type : 0C [Generic Interrupt Distributor] +[0001] Length : 18 +[0002] Reserved : 0000 +[0004] Local GIC Hardware ID : 00000000 +[0008] Base Address : 0000000000000000 +[0004] Interrupt Base : 00000000 +[0004] Reserved : 00000000 diff --git a/platforms/dummy.acpi/asf!.asl b/platforms/dummy.acpi/asf!.asl new file mode 100644 index 0000000..a05f924 --- /dev/null +++ b/platforms/dummy.acpi/asf!.asl @@ -0,0 +1,80 @@ +/* + * Intel ACPI Component Architecture + * iASL Compiler/Disassembler version 20130117-64 [Jan 31 2013] + * Copyright (c) 2000 - 2013 Intel Corporation + * + * Template for [ASF!] ACPI Table + * Format: [ByteLength] FieldName : HexFieldValue + */ + +[0004] Signature : "ASF!" [Alert Standard Format table] +[0004] Table Length : 00000072 +[0001] Revision : 10 +[0001] Checksum : 0B +[0006] Oem ID : "INTEL " +[0008] Oem Table ID : "TEMPLATE" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20100528 + +[0001] Subtable Type : 00 [ASF Information] +[0001] Reserved : 00 +[0002] Length : 0010 +[0001] Minimum Reset Value : 00 +[0001] Minimum Polling Interval : 00 +[0002] System ID : 0000 +[0004] Manufacturer ID : 00000000 +[0001] Flags : 00 +[0003] Reserved : 000000 + +[0001] Subtable Type : 01 [ASF Alerts] +[0001] Reserved : 00 +[0002] Length : 0014 +[0001] AssertMask : 00 +[0001] DeassertMask : 00 +[0001] Alert Count : 01 +[0001] Alert Data Length : 0C + +[0001] Address : 00 +[0001] Command : 00 +[0001] Mask : 00 +[0001] Value : 00 +[0001] SensorType : 00 +[0001] Type : 00 +[0001] Offset : 00 +[0001] SourceType : 00 +[0001] Severity : 00 +[0001] SensorNumber : 00 +[0001] Entity : 00 +[0001] Instance : 00 + +[0001] Subtable Type : 02 [ASF Remote Control] +[0001] Reserved : 00 +[0002] Length : 000C +[0001] Control Count : 01 +[0001] Control Data Length : 04 +[0002] Reserved : 0000 + +[0001] Function : 00 +[0001] Address : 00 +[0001] Command : 00 +[0001] Value : 00 + +[0001] Subtable Type : 03 [ASF RMCP Boot Options] +[0001] Reserved : 00 +[0002] Length : 0017 +[0007] Capabilities : 00 00 00 00 00 00 00 +[0001] Completion Code : 00 +[0004] Enterprise ID : 00000000 +[0001] Command : 00 +[0002] Parameter : 0000 +[0002] Boot Options : 0000 +[0002] Oem Parameters : 0000 + +[0001] Subtable Type : 84 [ASF Address] +[0001] Reserved : 00 +[0002] Length : 0007 +[0001] Eprom Address : 00 +[0001] Device Count : 01 +[0001] Addresses : 00 + diff --git a/platforms/dummy.acpi/bert.asl b/platforms/dummy.acpi/bert.asl new file mode 100644 index 0000000..55b1622 --- /dev/null +++ b/platforms/dummy.acpi/bert.asl @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org> + * + * [BERT] Boot Error Record Table + * Format: [ByteLength] FieldName : HexFieldValue + * + * This source is released under the terms of the GPLv2. + */ + +[0004] Signature : "BERT" +[0004] Table Length : 00000030 +[0001] Revision : 01 +[0001] Checksum : 15 +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "DUMMY " +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20100528 + +[0004] Boot Error Region Length : 00000000 +[0008] Boot Error Region Address : 0000000000000000 diff --git a/platforms/dummy.acpi/bgrt.asl b/platforms/dummy.acpi/bgrt.asl new file mode 100644 index 0000000..c8af10e --- /dev/null +++ b/platforms/dummy.acpi/bgrt.asl @@ -0,0 +1,25 @@ +/* + * Intel ACPI Component Architecture + * iASL Compiler/Disassembler version 20130117-64 [Jan 31 2013] + * Copyright (c) 2000 - 2013 Intel Corporation + * + * Template for [BGRT] ACPI Table + * Format: [ByteLength] FieldName : HexFieldValue + */ + +[0004] Signature : "BGRT" [Boot Graphics Resource Table] +[0004] Table Length : 00000038 +[0001] Revision : 01 +[0001] Checksum : 0D +[0006] Oem ID : "INTEL " +[0008] Oem Table ID : "TEMPLATE" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20110623 + +[0002] Version : 0001 +[0001] Status : 00 +[0001] Image Type : 00 +[0008] Image Address : 0000000000000000 +[0004] Image OffsetX : 00000000 +[0004] Image OffsetY : 00000000 diff --git a/platforms/dummy.acpi/boot.asl b/platforms/dummy.acpi/boot.asl new file mode 100644 index 0000000..5a567fb --- /dev/null +++ b/platforms/dummy.acpi/boot.asl @@ -0,0 +1,21 @@ +/* + * Intel ACPI Component Architecture + * iASL Compiler/Disassembler version 20130117-64 [Jan 31 2013] + * Copyright (c) 2000 - 2013 Intel Corporation + * + * Template for [BOOT] ACPI Table + * Format: [ByteLength] FieldName : HexFieldValue + */ + +[0004] Signature : "BOOT" [Simple Boot Flag Table] +[0004] Table Length : 00000028 +[0001] Revision : 01 +[0001] Checksum : 0D +[0006] Oem ID : "INTEL " +[0008] Oem Table ID : "TEMPLATE" +[0004] Oem Revision : 06040000 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20100528 + +[0001] Boot Register Index : 00 +[0003] Reserved : 000000 diff --git a/platforms/dummy.acpi/cpep.asl b/platforms/dummy.acpi/cpep.asl new file mode 100644 index 0000000..4383816 --- /dev/null +++ b/platforms/dummy.acpi/cpep.asl @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org> + * + * [CPEP] Corrected Platform Error Polling Table + * Format: [ByteLength] FieldName : HexFieldValue + * + * This source is released under the terms of the GPLv2. + */ + +[0004] Signature : "CPEP" +[0004] Table Length : 00000034 +[0001] Revision : 01 +[0001] Checksum : 0F +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "DUMMY " +[0004] Oem Revision : 00000000 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20100528 + +[0008] Reserved : 0000000000000000 + +[0001] Subtable Type : 00 +[0001] Length : 08 +[0001] Processor ID : 00 +[0001] Processor EID : 00 +[0004] Polling Interval : 00000000 diff --git a/platforms/dummy.acpi/csrt.asl b/platforms/dummy.acpi/csrt.asl new file mode 100644 index 0000000..ab43ea5 --- /dev/null +++ b/platforms/dummy.acpi/csrt.asl @@ -0,0 +1,143 @@ +/* + * Intel ACPI Component Architecture + * iASL Compiler/Disassembler version 20130117-64 [Jan 31 2013] + * Copyright (c) 2000 - 2013 Intel Corporation + * + * Template for [CSRT] ACPI Table + * Format: [ByteLength] FieldName : HexFieldValue + */ + +[0004] Signature : "CSRT" [Core System Resource Table] +[0004] Table Length : 0000014C +[0001] Revision : 01 +[0001] Checksum : 0D +[0006] Oem ID : "INTEL " +[0008] Oem Table ID : "TEMPLATE" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20121114 + + +[0004] Length : 00000088 +[0004] Vendor ID : 4C544E49 +[0004] Subvendor ID : 00000000 +[0002] Device ID : 9C60 +[0002] Subdevice ID : 0000 +[0002] Revision : 0002 +[0002] Reserved : 0000 +[0004] Shared Info Length : 0000001C + +[0002] Major Version : 0001 +[0002] Minor Version : 0000 +[0004] MMIO Base Address Low : B3A00000 +[0004] MMIO Base Address High : 00000000 +[0004] GSI Interrupt : 0000002A +[0001] Interrupt Polarity : 02 +[0001] Interrupt Mode : 00 +[0001] Num Channels : 06 +[0001] DMA Address Width : 20 +[0002] Base Request Line : 0000 +[0002] Num Handshake Signals : 0010 +[0004] Max Block Size : 00000FFF + +[0004] Length : 0000000C +[0002] Type : 0003 +[0002] Subtype : 0001 +[0004] UID : 20495053 + +[0004] Length : 0000000C +[0002] Type : 0003 +[0002] Subtype : 0000 +[0004] UID : 30414843 + +[0004] Length : 0000000C +[0002] Type : 0003 +[0002] Subtype : 0000 +[0004] UID : 31414843 + +[0004] Length : 0000000C +[0002] Type : 0003 +[0002] Subtype : 0000 +[0004] UID : 32414843 + +[0004] Length : 0000000C +[0002] Type : 0003 +[0002] Subtype : 0000 +[0004] UID : 33414843 + +[0004] Length : 0000000C +[0002] Type : 0003 +[0002] Subtype : 0000 +[0004] UID : 34414843 + +[0004] Length : 0000000C +[0002] Type : 0003 +[0002] Subtype : 0000 +[0004] UID : 35414843 + +[0004] Length : 000000A0 +[0004] Vendor ID : 4C544E49 +[0004] Subvendor ID : 00000000 +[0002] Device ID : 9C60 +[0002] Subdevice ID : 0000 +[0002] Revision : 0003 +[0002] Reserved : 0000 +[0004] Shared Info Length : 0000001C + +[0002] Major Version : 0001 +[0002] Minor Version : 0000 +[0004] MMIO Base Address Low : 00000000 +[0004] MMIO Base Address High : 00000000 +[0004] GSI Interrupt : 0000002B +[0001] Interrupt Polarity : 02 +[0001] Interrupt Mode : 00 +[0001] Num Channels : 08 +[0001] DMA Address Width : 20 +[0002] Base Request Line : 0010 +[0002] Num Handshake Signals : 0010 +[0004] Max Block Size : 00000FFF + +[0004] Length : 0000000C +[0002] Type : 0003 +[0002] Subtype : 0001 +[0004] UID : 20433249 + +[0004] Length : 0000000C +[0002] Type : 0003 +[0002] Subtype : 0000 +[0004] UID : 30414843 + +[0004] Length : 0000000C +[0002] Type : 0003 +[0002] Subtype : 0000 +[0004] UID : 31414843 + +[0004] Length : 0000000C +[0002] Type : 0003 +[0002] Subtype : 0000 +[0004] UID : 32414843 + +[0004] Length : 0000000C +[0002] Type : 0003 +[0002] Subtype : 0000 +[0004] UID : 33414843 + +[0004] Length : 0000000C +[0002] Type : 0003 +[0002] Subtype : 0000 +[0004] UID : 34414843 + +[0004] Length : 0000000C +[0002] Type : 0003 +[0002] Subtype : 0000 +[0004] UID : 35414843 + +[0004] Length : 0000000C +[0002] Type : 0003 +[0002] Subtype : 0000 +[0004] UID : 36414843 + +[0004] Length : 0000000C +[0002] Type : 0003 +[0002] Subtype : 0000 +[0004] UID : 37414843 diff --git a/platforms/dummy.acpi/dbgp.asl b/platforms/dummy.acpi/dbgp.asl new file mode 100644 index 0000000..d1a826f --- /dev/null +++ b/platforms/dummy.acpi/dbgp.asl @@ -0,0 +1,29 @@ +/* + * Intel ACPI Component Architecture + * iASL Compiler/Disassembler version 20130117-64 [Jan 31 2013] + * Copyright (c) 2000 - 2013 Intel Corporation + * + * Template for [DBGP] ACPI Table + * Format: [ByteLength] FieldName : HexFieldValue + */ + +[0004] Signature : "DBGP" [Debug Port table] +[0004] Table Length : 00000034 +[0001] Revision : 01 +[0001] Checksum : 1A +[0006] Oem ID : "INTEL " +[0008] Oem Table ID : "TEMPLATE" +[0004] Oem Revision : 00000000 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20100528 + +[0001] Interface Type : 00 +[0003] Reserved : 000000 + +[0012] Debug Port Register : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 08 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 00 [Undefined/Legacy] +[0008] Address : 0000000000000000 + diff --git a/platforms/dummy.acpi/dmar.asl b/platforms/dummy.acpi/dmar.asl new file mode 100644 index 0000000..e10c8c3 --- /dev/null +++ b/platforms/dummy.acpi/dmar.asl @@ -0,0 +1,68 @@ +/* + * Intel ACPI Component Architecture + * iASL Compiler/Disassembler version 20130117-64 [Jan 31 2013] + * Copyright (c) 2000 - 2013 Intel Corporation + * + * Template for [DMAR] ACPI Table + * Format: [ByteLength] FieldName : HexFieldValue + */ + +[0004] Signature : "DMAR" [DMA Remapping table] +[0004] Table Length : 0000008C +[0001] Revision : 01 +[0001] Checksum : 15 +[0006] Oem ID : "INTEL " +[0008] Oem Table ID : "TEMPLATE" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20100528 + +[0001] Host Address Width : 2F +[0001] Flags : 01 + +[0002] Subtable Type : 0000 [Hardware Unit Definition] +[0002] Length : 0018 +[0001] Flags : 01 +[0001] Reserved : 00 +[0002] PCI Segment Number : 0000 +[0008] Register Base Address : 00000000FD020000 + +[0001] Device Scope Entry Type : 03 +[0001] Entry Length : 08 +[0002] Reserved : 0000 +[0001] Enumeration ID : 08 +[0001] PCI Bus Number : F0 +[0002] PCI Path : 1F,07 + +[0002] Subtable Type : 0001 [Reserved Memory Region] +[0002] Length : 0020 +[0002] Reserved : 0000 +[0002] PCI Segment Number : 0000 +[0008] Base Address : 0000000078C21000 +[0008] End Address (limit) : 0000000078C23FFF + +[0001] Device Scope Entry Type : 01 +[0001] Entry Length : 08 +[0002] Reserved : 0000 +[0001] Enumeration ID : 00 +[0001] PCI Bus Number : 00 +[0002] PCI Path : 1D,00 + +[0002] Subtable Type : 0002 [Root Port ATS Capability] +[0002] Length : 0010 +[0001] Flags : 00 +[0001] Reserved : 00 +[0002] PCI Segment Number : 0000 + +[0001] Device Scope Entry Type : 02 +[0001] Entry Length : 08 +[0002] Reserved : 0000 +[0001] Enumeration ID : 00 +[0001] PCI Bus Number : 00 +[0002] PCI Path : 01,00 + +[0002] Subtable Type : 0003 [Remapping Hardware Static Affinity] +[0002] Length : 0014 +[0004] Reserved : 00000000 +[0008] Base Address : 00000000FD020000 +[0004] Proximity Domain : 00000000 diff --git a/platforms/dummy.acpi/dsdt.asl b/platforms/dummy.acpi/dsdt.asl new file mode 100644 index 0000000..541525b --- /dev/null +++ b/platforms/dummy.acpi/dsdt.asl @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org> + * + * [DSDT] Null Description + * + * This source is released under the terms of the GPLv2. + */ + +DefinitionBlock ( + "dsdt.aml", // output filename + "DSDT", // table signature + 1, // DSDT compliance revision + "LINARO", // OEM ID + "DUMMY ", // table ID + 0x00000002) // OEM revision +{ +} diff --git a/platforms/dummy.acpi/dummy.manifest b/platforms/dummy.acpi/dummy.manifest new file mode 100644 index 0000000..6b3a743 --- /dev/null +++ b/platforms/dummy.acpi/dummy.manifest @@ -0,0 +1,34 @@ +# +# Each line is either a comment, white space, or two fields: +# +# <signature> : <ASL file name> +# +# NB: for each file x.asl, an AML file called x.aml will be created +# + +rsdp: rsdp.asl +xsdt: xsdt.asl +facp: facp.asl +dsdt: dsdt.asl +ssdt: ssdt0.asl +bert: bert.asl +ecdt: ecdt.asl +facs: facs.asl +gtdt: gtdt.asl +hest: hest.asl +apic: apic.asl +mcfg: mcfg.asl +mpst: mpst.asl +oem: oem0.asl +pmmt: pmmt.asl +slit: slit.asl +spmi: spmi.asl +srat: srat.asl +uefi: uefi.asl +cpep: cpep.asl +einj: einj.asl +erst: erst.asl +fpdt: fpdt.asl +mchi: mchi.asl +msct: msct.asl + diff --git a/platforms/dummy.acpi/ecdt.asl b/platforms/dummy.acpi/ecdt.asl new file mode 100644 index 0000000..2e38590 --- /dev/null +++ b/platforms/dummy.acpi/ecdt.asl @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org> + * + * [ECDT] Embedded Controller Boot Resources Table + * Format: [ByteLength] FieldName : HexFieldValue + * + * This source is released under the terms of the GPLv2. + */ + +[0004] Signature : "ECDT" +[0004] Table Length : 00000042 +[0001] Revision : 01 +[0001] Checksum : 2D +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "DUMMY " +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20100528 + + +[0012] Command/Status Register : [Generic Address Structure] +[0001] Space ID : 01 [SystemIO] +[0001] Bit Width : 08 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 00 [Undefined/Legacy] +[0008] Address : 0000000000000066 + +[0012] Data Register : [Generic Address Structure] +[0001] Space ID : 01 [SystemIO] +[0001] Bit Width : 08 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 00 [Undefined/Legacy] +[0008] Address : 0000000000000062 + +[0004] UID : 00000000 +[0001] GPE Number : 09 +[0001] Namepath : "" diff --git a/platforms/dummy.acpi/einj.asl b/platforms/dummy.acpi/einj.asl new file mode 100644 index 0000000..65915c3 --- /dev/null +++ b/platforms/dummy.acpi/einj.asl @@ -0,0 +1,151 @@ +/* + * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org> + * + * [EINJ] Error Injection Table + * Format: [ByteLength] FieldName : HexFieldValue + * + * This source released under the terms of the GPLv2. + */ + +[0004] Signature : "EINJ" +[0004] Table Length : 00000130 +[0001] Revision : 01 +[0001] Checksum : 09 +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "DUMMY " +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20100528 + +[0004] Injection Header Length : 00000030 +[0001] Flags : 00 +[0003] Reserved : 000000 +[0004] Injection Entry Count : 0000000A + +[0001] Action : 00 [Begin Operation] +[0001] Instruction : 00 [Read Register] +[0001] Flags (decoded below) : 00 + Preserve Register Bits : 0 +[0001] Reserved : 00 + +[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0000000000000000 + +[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF + +[0001] Action : 01 [Get Trigger Table] +[0001] Instruction : 00 [Read Register] +[0001] Flags (decoded below) : 00 + Preserve Register Bits : 0 +[0001] Reserved : 00 + +[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0000000000000000 + +[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF + +[0001] Action : 02 [Set Error Type] +[0001] Instruction : 02 [Write Register] +[0001] Flags (decoded below) : 01 + Preserve Register Bits : 1 +[0001] Reserved : 00 + +[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0000000000000000 + +[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF + +[0001] Action : 03 [Get Error Type] +[0001] Instruction : 00 [Read Register] +[0001] Flags (decoded below) : 00 + Preserve Register Bits : 0 +[0001] Reserved : 00 + +[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0000000000000000 + +[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF + +[0001] Action : 04 [End Operation] +[0001] Instruction : 03 [Write Register Value] +[0001] Flags (decoded below) : 01 + Preserve Register Bits : 1 +[0001] Reserved : 00 + +[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0000000000000000 + +[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF + +[0001] Action : 05 [Execute Operation] +[0001] Instruction : 03 [Write Register Value] +[0001] Flags (decoded below) : 01 + Preserve Register Bits : 1 +[0001] Reserved : 00 + +[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 01 [SystemIO] +[0001] Bit Width : 10 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 02 [Word Access:16] +[0008] Address : 0000000000000000 + +[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF + +[0001] Action : 06 [Check Busy Status] +[0001] Instruction : 01 [Read Register Value] +[0001] Flags (decoded below) : 00 + Preserve Register Bits : 0 +[0001] Reserved : 00 + +[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0000000000000000 + +[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF + +[0001] Action : 07 [Get Command Status] +[0001] Instruction : 00 [Read Register] +[0001] Flags (decoded below) : 01 + Preserve Register Bits : 1 +[0001] Reserved : 00 + +[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0000000000000000 + +[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF diff --git a/platforms/dummy.acpi/erst.asl b/platforms/dummy.acpi/erst.asl new file mode 100644 index 0000000..33100bd --- /dev/null +++ b/platforms/dummy.acpi/erst.asl @@ -0,0 +1,278 @@ +/* + * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org> + * + * [ERST] Error Record Serialization Table + * Format: [ByteLength] FieldName : HexFieldValue + * + * This source released under the terms of the GPLv2. + */ + +[0004] Signature : "ERST" +[0004] Table Length : 00000230 +[0001] Revision : 01 +[0001] Checksum : AB +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "DUMMY " +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20100528 + +[0004] Serialization Header Length : 00000030 +[0004] Reserved : 00000000 +[0004] Instruction Entry Count : 00000010 + +[0001] Action : 00 [Begin Write Operation] +[0001] Instruction : 03 [Write Register Value] +[0001] Flags (decoded below) : 00 + Preserve Register Bits : 0 +[0001] Reserved : 00 + +[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0000000000000000 + +[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF + +[0001] Action : 01 [Begin Read Operation] +[0001] Instruction : 03 [Write Register Value] +[0001] Flags (decoded below) : 00 + Preserve Register Bits : 0 +[0001] Reserved : 00 + +[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0000000000000000 + +[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF + +[0001] Action : 02 [Begin Clear Operation] +[0001] Instruction : 03 [Write Register Value] +[0001] Flags (decoded below) : 00 + Preserve Register Bits : 0 +[0001] Reserved : 00 + +[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0000000000000000 + +[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF + +[0001] Action : 03 [End Operation] +[0001] Instruction : 04 [Noop] +[0001] Flags (decoded below) : 01 + Preserve Register Bits : 1 +[0001] Reserved : 00 + +[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0000000000000000 + +[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF + +[0001] Action : 04 [Set Record Offset] +[0001] Instruction : 02 [Write Register] +[0001] Flags (decoded below) : 00 + Preserve Register Bits : 0 +[0001] Reserved : 00 + +[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0000000000000000 + +[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF + +[0001] Action : 05 [Execute Operation] +[0001] Instruction : 03 [Write Register Value] +[0001] Flags (decoded below) : 00 + Preserve Register Bits : 0 +[0001] Reserved : 00 + +[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 01 [SystemIO] +[0001] Bit Width : 08 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 01 [Byte Access:8] +[0008] Address : 0000000000000000 + +[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF + +[0001] Action : 06 [Check Busy Status] +[0001] Instruction : 01 [Read Register Value] +[0001] Flags (decoded below) : 00 + Preserve Register Bits : 0 +[0001] Reserved : 00 + +[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0000000000000000 + +[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF + +[0001] Action : 07 [Get Command Status] +[0001] Instruction : 00 [Read Register] +[0001] Flags (decoded below) : 00 + Preserve Register Bits : 0 +[0001] Reserved : 00 + +[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0000000000000000 + +[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF + +[0001] Action : 08 [Get Record Identifier] +[0001] Instruction : 00 [Read Register] +[0001] Flags (decoded below) : 00 + Preserve Register Bits : 0 +[0001] Reserved : 00 + +[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0000000000000000 + +[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF + +[0001] Action : 09 [Set Record Identifier] +[0001] Instruction : 02 [Write Register] +[0001] Flags (decoded below) : 00 + Preserve Register Bits : 0 +[0001] Reserved : 00 + +[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0000000000000000 + +[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF + +[0001] Action : 0A [Get Record Count] +[0001] Instruction : 00 [Read Register] +[0001] Flags (decoded below) : 00 + Preserve Register Bits : 0 +[0001] Reserved : 00 + +[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0000000000000000 + +[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF + +[0001] Action : 0B [Begin Dummy Write] +[0001] Instruction : 03 [Write Register Value] +[0001] Flags (decoded below) : 00 + Preserve Register Bits : 0 +[0001] Reserved : 00 + +[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0000000000000000 + +[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF + +[0001] Action : 0C [Unused/Unknown Action] +[0001] Instruction : 00 [Read Register] +[0001] Flags (decoded below) : 00 + Preserve Register Bits : 0 +[0001] Reserved : 00 + +[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0000000000000000 + +[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF + +[0001] Action : 0D [Get Error Address Range] +[0001] Instruction : 00 [Read Register] +[0001] Flags (decoded below) : 00 + Preserve Register Bits : 0 +[0001] Reserved : 00 + +[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0000000000000000 + +[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF + +[0001] Action : 0E [Get Error Address Length] +[0001] Instruction : 00 [Read Register] +[0001] Flags (decoded below) : 00 + Preserve Register Bits : 0 +[0001] Reserved : 00 + +[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0000000000000000 + +[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF + +[0001] Action : 0F [Get Error Attributes] +[0001] Instruction : 00 [Read Register] +[0001] Flags (decoded below) : 00 + Preserve Register Bits : 0 +[0001] Reserved : 00 + +[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0000000000000000 + +[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF diff --git a/platforms/dummy.acpi/facp.asl b/platforms/dummy.acpi/facp.asl new file mode 100644 index 0000000..45d4d92 --- /dev/null +++ b/platforms/dummy.acpi/facp.asl @@ -0,0 +1,167 @@ +/* + * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org> + * + * [FACP] ACPI Table + * + * This source is released under the terms of the GPLv2. + */ + +[0004] Signature : "FACP" +[0004] Table Length : 0000010C +[0001] Revision : 05 +[0001] Checksum : 18 +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "DUMMY " +[0004] Oem Revision : 00000000 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20111123 + +[0004] FACS Address : 00000000 +[0004] DSDT Address : 00000010 +[0001] Model : 00 +[0001] PM Profile : 04 /* Enterprise Server */ +[0002] SCI Interrupt : 0000 +[0004] SMI Command Port : 00000000 +[0001] ACPI Enable Value : 00 +[0001] ACPI Disable Value : 00 +[0001] S4BIOS Command : 00 +[0001] P-State Control : 00 +[0004] PM1A Event Block Address : 00000001 +[0004] PM1B Event Block Address : 00000000 +[0004] PM1A Control Block Address : 00000001 +[0004] PM1B Control Block Address : 00000000 +[0004] PM2 Control Block Address : 00000001 +[0004] PM Timer Block Address : 00000001 +[0004] GPE0 Block Address : 00000001 +[0004] GPE1 Block Address : 00000000 +[0001] PM1 Event Block Length : 04 +[0001] PM1 Control Block Length : 02 +[0001] PM2 Control Block Length : 01 +[0001] PM Timer Block Length : 04 +[0001] GPE0 Block Length : 08 +[0001] GPE1 Block Length : 00 +[0001] GPE1 Base Offset : 00 +[0001] _CST Support : 00 +[0002] C2 Latency : 0000 +[0002] C3 Latency : 0000 +[0002] CPU Cache Size : 0000 +[0002] Cache Flush Stride : 0000 +[0001] Duty Cycle Offset : 00 +[0001] Duty Cycle Width : 00 +[0001] RTC Day Alarm Index : 00 +[0001] RTC Month Alarm Index : 00 +[0001] RTC Century Index : 00 +[0002] Boot Flags (decoded below) : 0000 + Legacy Devices Supported (V2) : 0 + 8042 Present on ports 60/64 (V2) : 0 + VGA Not Present (V4) : 0 + MSI Not Supported (V4) : 0 + PCIe ASPM Not Supported (V4) : 0 + CMOS RTC Not Present (V5) : 0 +[0001] Reserved : 00 +[0004] Flags (decoded below) : 00000000 + WBINVD instruction is operational (V1) : 1 + WBINVD flushes all caches (V1) : 1 + All CPUs support C1 (V1) : 0 + C2 works on MP system (V1) : 0 + Control Method Power Button (V1) : 1 + Control Method Sleep Button (V1) : 1 + RTC wake not in fixed reg space (V1) : 0 + RTC can wake system from S4 (V1) : 0 + 32-bit PM Timer (V1) : 0 + Docking Supported (V1) : 0 + Reset Register Supported (V2) : 0 + Sealed Case (V3) : 0 + Headless - No Video (V3) : 1 + Use native instr after SLP_TYPx (V3) : 0 + PCIEXP_WAK Bits Supported (V4) : 0 + Use Platform Timer (V4) : 0 + RTC_STS valid on S4 wake (V4) : 0 + Remote Power-on capable (V4) : 1 + Use APIC Cluster Model (V4) : 0 + Use APIC Physical Destination Mode (V4) : 0 + Hardware Reduced (V5) : 1 + Low Power S0 Idle (V5) : 1 + +[0012] Reset Register : [Generic Address Structure] +[0001] Space ID : 01 [SystemIO] +[0001] Bit Width : 08 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 01 [Byte Access:8] +[0008] Address : 0000000000000001 + +[0001] Value to cause reset : 00 +[0003] Reserved : 000000 +[0008] FACS Address : 0000000000000000 +[0008] DSDT Address : 0000000000000010 +[0012] PM1A Event Block : [Generic Address Structure] +[0001] Space ID : 01 [SystemIO] +[0001] Bit Width : 20 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 02 [Word Access:16] +[0008] Address : 0000000000000001 + +[0012] PM1B Event Block : [Generic Address Structure] +[0001] Space ID : 01 [SystemIO] +[0001] Bit Width : 00 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 00 [Undefined/Legacy] +[0008] Address : 0000000000000000 + +[0012] PM1A Control Block : [Generic Address Structure] +[0001] Space ID : 01 [SystemIO] +[0001] Bit Width : 10 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 02 [Word Access:16] +[0008] Address : 0000000000000001 + +[0012] PM1B Control Block : [Generic Address Structure] +[0001] Space ID : 01 [SystemIO] +[0001] Bit Width : 00 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 00 [Undefined/Legacy] +[0008] Address : 0000000000000000 + +[0012] PM2 Control Block : [Generic Address Structure] +[0001] Space ID : 01 [SystemIO] +[0001] Bit Width : 08 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 00 [Undefined/Legacy] +[0008] Address : 0000000000000001 + +[0012] PM Timer Block : [Generic Address Structure] +[0001] Space ID : 01 [SystemIO] +[0001] Bit Width : 20 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 03 [DWord Access:32] +[0008] Address : 0000000000000001 + +[0012] GPE0 Block : [Generic Address Structure] +[0001] Space ID : 01 [SystemIO] +[0001] Bit Width : 80 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 01 [Byte Access:8] +[0008] Address : 0000000000000001 + +[0012] GPE1 Block : [Generic Address Structure] +[0001] Space ID : 01 [SystemIO] +[0001] Bit Width : 00 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 00 [Undefined/Legacy] +[0008] Address : 0000000000000000 + + +[0012] Sleep Control Register : [Generic Address Structure] +[0001] Space ID : 01 [SystemIO] +[0001] Bit Width : 08 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 01 [Byte Access:8] +[0008] Address : 0000000000000000 + +[0012] Sleep Status Register : [Generic Address Structure] +[0001] Space ID : 01 [SystemIO] +[0001] Bit Width : 08 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 01 [Byte Access:8] +[0008] Address : 0000000000000000 + diff --git a/platforms/dummy.acpi/facs.asl b/platforms/dummy.acpi/facs.asl new file mode 100644 index 0000000..8d12b41 --- /dev/null +++ b/platforms/dummy.acpi/facs.asl @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org> + * + * [FACS] ACPI Table + * + * This source is released under the terms of the GPLv2. + */ + +[0004] Signature : "FACS" +[0004] Length : 00000040 +[0004] Hardware Signature : 00000000 +[0004] 32 Firmware Waking Vector : 00000000 +[0004] Global Lock : 00000000 +[0004] Flags (decoded below) : 00000000 + S4BIOS Support Present : 0 + 64-bit Wake Supported (V2) : 0 +[0008] 64 Firmware Waking Vector : 0000000000000000 +[0001] Version : 02 +[0003] Reserved : 000000 +[0004] OspmFlags (decoded below) : 00000000 + 64-bit Wake Env Required (V2) : 0 diff --git a/platforms/dummy.acpi/fpdt.asl b/platforms/dummy.acpi/fpdt.asl new file mode 100644 index 0000000..047255f --- /dev/null +++ b/platforms/dummy.acpi/fpdt.asl @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org> + * + * [FPDT] Firmware Performance Data Table + * Format: [ByteLength] FieldName : HexFieldValue + * + * This source released under the terms of the GPLv2. + */ + +[0004] Signature : "FPDT" +[0004] Table Length : 00000064 +[0001] Revision : 01 +[0001] Checksum : BD +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "DUMMY " +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20110804 + + +[0002] Subtable Type : 0000 +[0001] Length : 30 +[0001] Revision : 01 +[0004] Reserved : 00000000 +[0008] Reset End : 0000000000000000 +[0008] Load Image Start : 0000000000000000 +[0008] Start Image Start : 0000000000000000 +[0008] Exit Services Entry : 0000000000000000 +[0008] Exit Services Exit : 0000000000000000 + +[0002] Subtable Type : 0001 +[0001] Length : 10 +[0001] Revision : 01 +[0004] Reserved : 00000000 +[0008] S3PT Address : 0000000000000000 diff --git a/platforms/dummy.acpi/gtdt.asl b/platforms/dummy.acpi/gtdt.asl new file mode 100644 index 0000000..e08cd06 --- /dev/null +++ b/platforms/dummy.acpi/gtdt.asl @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org> + * + * [GTDT] Generic Timer Description Table + * Format: [ByteLength] FieldName : HexFieldValue + * + * This source is released under the terms of the GPLv2. + */ + +[0004] Signature : "GTDT" +[0004] Table Length : 00000050 +[0001] Revision : 01 +[0001] Checksum : F1 +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "DUMMY " +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20110623 + +[0008] Timer Address : 0000000000000000 +[0004] Flags (decoded below) : 00000001 + Memory Present : 1 + +[0004] Secure PL1 Interrupt : 00000000 +[0004] SPL1 Flags (decoded below) : 00000000 + Trigger Mode : 0 + Polarity : 0 + +[0004] Non-Secure PL1 Interrupt : 00000000 +[0004] NSPL1 Flags (decoded below) : 00000000 + Trigger Mode : 0 + Polarity : 0 + +[0004] Virtual Timer Interrupt : 00000000 +[0004] VT Flags (decoded below) : 00000000 + Trigger Mode : 0 + Polarity : 0 + +[0004] Non-Secure PL2 Interrupt : 00000000 +[0004] NSPL2 Flags (decoded below) : 00000000 + Trigger Mode : 0 + Polarity : 0 diff --git a/platforms/dummy.acpi/hest.asl b/platforms/dummy.acpi/hest.asl new file mode 100644 index 0000000..e34d856 --- /dev/null +++ b/platforms/dummy.acpi/hest.asl @@ -0,0 +1,193 @@ +/* + * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org + * + * [HEST] Hardware Error Source Table + * Format: [ByteLength] FieldName : HexFieldValue + * + * This source is released under the terms of the GPLv2. + */ + +[0004] Signature : "HEST" +[0004] Table Length : 000001D4 +[0001] Revision : 01 +[0001] Checksum : 20 +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "DUMMY " +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20100528 + +[0004] Error Source Count : 00000004 + +[0002] Subtable Type : 0000 [IA-32 Machine Check Exception] +[0002] Source Id : 0000 +[0002] Reserved1 : 0000 +[0001] Flags (decoded below) : 00 + Firmware First : 0 +[0001] Enabled : 01 +[0004] Records To Preallocate : 00000001 +[0004] Max Sections Per Record : 00000001 +[0008] Global Capability Data : 0000000000000000 +[0008] Global Control Data : 0000000000000000 +[0001] Num Hardware Banks : 02 +[0007] Reserved2 : 00000000000000 + +[0001] Bank Number : 00 +[0001] Clear Status On Init : 00 +[0001] Status Format : 00 +[0001] Reserved : 00 +[0004] Control Register : 00000000 +[0008] Control Data : 0000000000000000 +[0004] Status Register : 00000000 +[0004] Address Register : 00000000 +[0004] Misc Register : 00000000 + +[0001] Bank Number : 01 +[0001] Clear Status On Init : 00 +[0001] Status Format : 00 +[0001] Reserved : 00 +[0004] Control Register : 00000000 +[0008] Control Data : 0000000000000000 +[0004] Status Register : 00000000 +[0004] Address Register : 00000000 +[0004] Misc Register : 00000000 + +[0002] Subtable Type : 0001 [IA-32 Corrected Machine Check] +[0002] Source Id : 0001 +[0002] Reserved1 : 0000 +[0001] Flags (decoded below) : 00 + Firmware First : 0 +[0001] Enabled : 01 +[0004] Records To Preallocate : 00000001 +[0004] Max Sections Per Record : 00000001 + +[0028] Notify : [Hardware Error Notification Structure] +[0001] Notify Type : 00 [Polled] +[0001] Notify Length : 00 +[0002] Configuration Write Enable : 0000 +[0004] PollInterval : 00000000 +[0004] Vector : 00000000 +[0004] Polling Threshold Value : 00000000 +[0004] Polling Threshold Window : 00000000 +[0004] Error Threshold Value : 00000000 +[0004] Error Threshold Window : 00000000 + +[0001] Num Hardware Banks : 02 +[0003] Reserved2 : 000000 + +[0001] Bank Number : 00 +[0001] Clear Status On Init : 00 +[0001] Status Format : 00 +[0001] Reserved : 00 +[0004] Control Register : 00000000 +[0008] Control Data : 0000000000000000 +[0004] Status Register : 00000000 +[0004] Address Register : 00000000 +[0004] Misc Register : 00000000 + +[0001] Bank Number : 01 +[0001] Clear Status On Init : 00 +[0001] Status Format : 00 +[0001] Reserved : 00 +[0004] Control Register : 00000000 +[0008] Control Data : 0000000000000000 +[0004] Status Register : 00000000 +[0004] Address Register : 00000000 +[0004] Misc Register : 00000000 + +[0002] Subtable Type : 0007 [PCI Express AER (AER Endpoint)] +[0002] Source Id : 0000 +[0002] Reserved : 0000 +[0001] Flags (decoded below) : 00 + Firmware First : 0 +[0001] Enabled : 01 +[0004] Records To Preallocate : 00000001 +[0004] Max Sections Per Record : 00000001 +[0004] Bus : 00000000 +[0002] Device : 0000 +[0002] Function : 0000 +[0002] DeviceControl : 0000 +[0002] Reserved : 0000 +[0004] Uncorrectable Mask : 00000000 +[0004] Uncorrectable Severity : 00000000 +[0004] Correctable Mask : 00000000 +[0004] Advanced Capabilities : 00000000 + +[0002] Subtable Type : 0008 [PCI Express/PCI-X Bridge AER] +[0002] Source Id : 0000 +[0002] Reserved : 0000 +[0001] Flags (decoded below) : 00 + Firmware First : 0 +[0001] Enabled : 01 +[0004] Records To Preallocate : 00000001 +[0004] Max Sections Per Record : 00000001 +[0004] Bus : 00000000 +[0002] Device : 0000 +[0002] Function : 0000 +[0002] DeviceControl : 0000 +[0002] Reserved : 0000 +[0004] Uncorrectable Mask : 00000000 +[0004] Uncorrectable Severity : 00000000 +[0004] Correctable Mask : 00000000 +[0004] Advanced Capabilities : 00000000 +[0004] 2nd Uncorrectable Mask : 00000000 +[0004] 2nd Uncorrectable Severity : 00000000 +[0004] 2nd Advanced Capabilities : 00000000 + +[0002] Subtable Type : 0009 [Generic Hardware Error Source] +[0002] Source Id : 0002 +[0002] Related Source Id : FFFF +[0001] Reserved : 00 +[0001] Enabled : 01 +[0004] Records To Preallocate : 00000001 +[0004] Max Sections Per Record : 00000001 +[0004] Max Raw Data Length : 00001000 + +[0012] Error Status Address : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0000000000000000 + +[0028] Notify : [Hardware Error Notification Structure] +[0001] Notify Type : 03 [SCI] +[0001] Notify Length : 1C +[0002] Configuration Write Enable : 0000 +[0004] PollInterval : 00000000 +[0004] Vector : 00000000 +[0004] Polling Threshold Value : 00000000 +[0004] Polling Threshold Window : 00000000 +[0004] Error Threshold Value : 00000000 +[0004] Error Threshold Window : 00000000 + +[0004] Error Status Block Length : 00001000 + +[0002] Subtable Type : 0009 [Generic Hardware Error Source] +[0002] Source Id : 0003 +[0002] Related Source Id : 0000 +[0001] Reserved : 00 +[0001] Enabled : 01 +[0004] Records To Preallocate : 00000001 +[0004] Max Sections Per Record : 00000001 +[0004] Max Raw Data Length : 00001000 + +[0012] Error Status Address : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0000000000000000 + +[0028] Notify : [Hardware Error Notification Structure] +[0001] Notify Type : 04 [NMI] +[0001] Notify Length : 1C +[0002] Configuration Write Enable : 0000 +[0004] PollInterval : 00000000 +[0004] Vector : 00000000 +[0004] Polling Threshold Value : 00000000 +[0004] Polling Threshold Window : 00000000 +[0004] Error Threshold Value : 00000000 +[0004] Error Threshold Window : 00000000 + +[0004] Error Status Block Length : 00001000 diff --git a/platforms/dummy.acpi/hpet.asl b/platforms/dummy.acpi/hpet.asl new file mode 100644 index 0000000..c150282 --- /dev/null +++ b/platforms/dummy.acpi/hpet.asl @@ -0,0 +1,33 @@ +/* + * Intel ACPI Component Architecture + * iASL Compiler/Disassembler version 20130117-64 [Jan 31 2013] + * Copyright (c) 2000 - 2013 Intel Corporation + * + * Template for [HPET] ACPI Table + * Format: [ByteLength] FieldName : HexFieldValue + */ + +[0004] Signature : "HPET" [High Precision Event Timer table] +[0004] Table Length : 00000038 +[0001] Revision : 01 +[0001] Checksum : 09 +[0006] Oem ID : "INTEL " +[0008] Oem Table ID : "TEMPLATE" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20100528 + +[0004] Hardware Block ID : 00000000 + +[0012] Timer Block Register : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 00 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 00 [Undefined/Legacy] +[0008] Address : 0000000000000000 + +[0001] Sequence Number : 00 +[0002] Minimum Clock Ticks : 0000 +[0001] Flags (decoded below) : 00 + 4K Page Protect : 0 + 64K Page Protect : 0 diff --git a/platforms/dummy.acpi/ivrs.asl b/platforms/dummy.acpi/ivrs.asl new file mode 100644 index 0000000..9f64314 --- /dev/null +++ b/platforms/dummy.acpi/ivrs.asl @@ -0,0 +1,86 @@ +/* + * Intel ACPI Component Architecture + * iASL Compiler/Disassembler version 20130117-64 [Jan 31 2013] + * Copyright (c) 2000 - 2013 Intel Corporation + * + * Template for [IVRS] ACPI Table + * Format: [ByteLength] FieldName : HexFieldValue + */ + +[0004] Signature : "IVRS" [I/O Virtualization Reporting Structure] +[0004] Table Length : 000000BC +[0001] Revision : 01 +[0001] Checksum : 87 +[0006] Oem ID : "INTEL " +[0008] Oem Table ID : "TEMPLATE" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20100528 + +[0004] Virtualization Info : 00000000 +[0008] Reserved : 0000000000000000 + +[0001] Subtable Type : 10 [Hardware Definition Block] +[0001] Flags : 14 +[0002] Length : 0034 +[0002] DeviceId : 0000 + +[0002] Capability Offset : 0000 +[0008] Base Address : 0000000000000000 +[0002] PCI Segment Group : 0000 +[0002] Virtualization Info : 0000 +[0004] Reserved : 00000000 + +[0001] Entry Type : 00 +[0002] Device ID : 0000 +[0001] Data Setting : 00 + +[0001] Entry Type : 40 +[0002] Device ID : 0000 +[0001] Data Setting : 00 +[0004] Extended Data : 00000000 + +[0001] Entry Type : 42 +[0002] Device ID : 0000 +[0001] Data Setting : 00 +[0001] Reserved : 00 +[0002] Source Used Device ID : 0000 +[0001] Reserved : 00 + +[0001] Entry Type : 48 +[0002] Device ID : 0000 +[0001] Data Setting : 00 +[0001] Handle : 00 +[0002] Source Used Device ID : 0000 +[0001] Variety : 00 + +[0001] Subtable Type : 20 [Memory Definition Block] +[0001] Flags : 08 +[0002] Length : 0020 +[0002] DeviceId : 0000 + +[0002] Auxiliary Data : 0000 +[0008] Reserved : 0000000000000000 +[0008] Start Address : 0000000000000000 +[0008] Memory Length : 0000000000000000 + +[0001] Subtable Type : 21 [Memory Definition Block] +[0001] Flags : 04 +[0002] Length : 0020 +[0002] DeviceId : 0000 + +[0002] Auxiliary Data : 0000 +[0008] Reserved : 0000000000000000 +[0008] Start Address : 0000000000000000 +[0008] Memory Length : 0000000000000000 + +[0001] Subtable Type : 10 [Hardware Definition Block] +[0001] Flags : 14 +[0002] Length : 0018 +[0002] DeviceId : 0000 + +[0002] Capability Offset : 0000 +[0008] Base Address : 0000000000000000 +[0002] PCI Segment Group : 0000 +[0002] Virtualization Info : 0000 +[0004] Reserved : 00000000 diff --git a/platforms/dummy.acpi/mcfg.asl b/platforms/dummy.acpi/mcfg.asl new file mode 100644 index 0000000..a3e93e9 --- /dev/null +++ b/platforms/dummy.acpi/mcfg.asl @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org> + * + * [MCFG] PCIe Memory Mapped Configuration Table + * Format: [ByteLength] FieldName : HexFieldValue + * + * This source is released under the terms of the GPLv2. + */ + +[0004] Signature : "MCFG" +[0004] Table Length : 0000003C +[0001] Revision : 01 +[0001] Checksum : 19 +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "DUMMY " +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20100528 + +[0008] Reserved : 0000000000000000 + +[0008] Base Address : 0000000000000000 +[0002] Segment Group Number : 0000 +[0001] Start Bus Number : 00 +[0001] End Bus Number : 00 +[0004] Reserved : 00000000 diff --git a/platforms/dummy.acpi/mchi.asl b/platforms/dummy.acpi/mchi.asl new file mode 100644 index 0000000..c10b8e9 --- /dev/null +++ b/platforms/dummy.acpi/mchi.asl @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org> + * + * [MCHI] Management Controller Host Interface Table + * Format: [ByteLength] FieldName : HexFieldValue + * + * This source released under the terms of the GPLv2. + */ + +[0004] Signature : "MCHI" +[0004] Table Length : 00000045 +[0001] Revision : 01 +[0001] Checksum : E4 +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "DUMMY " +[0004] Oem Revision : 02000715 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20100528 + +[0001] Interface Type : 01 +[0001] Protocol : 00 +[0008] Protocol Data : 0000000000000000 +[0001] Interrupt Type : 00 +[0001] Gpe : 00 +[0001] Pci Device Flag : 00 +[0004] Global Interrupt : 00000000 + +[0012] Control Register : [Generic Address Structure] +[0001] Space ID : 02 [PCI_Config] +[0001] Bit Width : 08 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 00 [Undefined/Legacy] +[0008] Address : 0000000000000000 + +[0001] Pci Segment : 00 +[0001] Pci Bus : 00 +[0001] Pci Device : 00 +[0001] Pci Function : 00 diff --git a/platforms/dummy.acpi/mpst.asl b/platforms/dummy.acpi/mpst.asl new file mode 100644 index 0000000..624e351 --- /dev/null +++ b/platforms/dummy.acpi/mpst.asl @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org> + * + * [MPST] Memory Power State Table + * Format: [ByteLength] FieldName : HexFieldValue + * + * This source is released under the terms of the GPLv2. + */ + +[0004] Signature : "MPST" +[0004] Table Length : 000000B6 +[0001] Revision : 01 +[0001] Checksum : 77 +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "DUMMY " +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20120913 + +[0001] Channel ID : 00 +[0003] Reserved : 000000 +[0002] Power Node Count : 0002 +[0002] Reserved : 0000 + +[0001] Flags (decoded below) : 00 + Node Enabled : 0 + Power Managed : 0 + Hot Plug Capable : 0 +[0001] Reserved : 00 +[0002] Node ID : 0000 +[0004] Length : 00000000 +[0008] Range Address : 0000000000000000 +[0008] Range Length : 0000000000000000 +[0004] Num Power States : 00000002 +[0004] Num Physical Components : 00000003 + +[0001] Power State : 00 +[0001] InfoIndex : 00 + +[0001] Power State : 00 +[0001] InfoIndex : 00 + +[0002] Component Id : 0000 +[0002] Component Id : 0001 +[0002] Component Id : 0002 + +[0001] Flags (decoded below) : 00 + Node Enabled : 0 + Power Managed : 0 + Hot Plug Capable : 0 +[0001] Reserved : 00 +[0002] Node ID : 0000 +[0004] Length : 00000000 +[0008] Range Address : 0000000000000000 +[0008] Range Length : 0000000000000000 +[0004] Num Power States : 00000001 +[0004] Num Physical Components : 00000001 + +[0001] Power State : 00 +[0001] InfoIndex : 00 + +[0002] Component Id : 0000 + +[0002] Characteristics Count : 0002 +[0002] Reserved : 0000 + +[0001] Structure ID : 01 +[0001] Flags (decoded below) : 00 + Memory Preserved : 0 + Auto Entry : 0 + Auto Exit : 0 +[0002] Reserved : 0000 +[0004] Average Power : 00000000 +[0004] Power Saving : 00000000 +[0008] Exit Latency : 0000000000000000 +[0008] Reserved : 0000000000000000 + +[0001] Structure ID : 01 +[0001] Flags (decoded below) : 00 + Memory Preserved : 0 + Auto Entry : 0 + Auto Exit : 0 +[0002] Reserved : 0000 +[0004] Average Power : 00000000 +[0004] Power Saving : 00000000 +[0008] Exit Latency : 0000000000000000 +[0008] Reserved : 0000000000000000 diff --git a/platforms/dummy.acpi/msct.asl b/platforms/dummy.acpi/msct.asl new file mode 100644 index 0000000..9635902 --- /dev/null +++ b/platforms/dummy.acpi/msct.asl @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org> + * + * [MSCT] Maximum System Characteristics Table + * Format: [ByteLength] FieldName : HexFieldValue + * + * This source released under the terms of the GPLv2. + */ + +[0004] Signature : "MSCT" +[0004] Table Length : 00000090 +[0001] Revision : 01 +[0001] Checksum : B7 +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "DUMMY " +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20100528 + +[0004] Proximity Offset : 00000038 +[0004] Max Proximity Domains : 00000003 +[0004] Max Clock Domains : 00000000 +[0008] Max Physical Address : 00000FFFFFFFFFFF + +[0001] Revision : 01 +[0001] Length : 16 +[0004] Domain Range Start : 00000000 +[0004] Domain Range End : 00000003 +[0004] Processor Capacity : 00000010 +[0008] Memory Capacity : 0000004000000000 + +[0001] Revision : 01 +[0001] Length : 16 +[0004] Domain Range Start : 00000000 +[0004] Domain Range End : 00000000 +[0004] Processor Capacity : 00000000 +[0008] Memory Capacity : 0000000000000000 + +[0001] Revision : 01 +[0001] Length : 16 +[0004] Domain Range Start : 00000000 +[0004] Domain Range End : 00000000 +[0004] Processor Capacity : 00000000 +[0008] Memory Capacity : 0000000000000000 + +[0001] Revision : 01 +[0001] Length : 16 +[0004] Domain Range Start : 00000000 +[0004] Domain Range End : 00000000 +[0004] Processor Capacity : 00000000 +[0008] Memory Capacity : 0000000000000000 diff --git a/platforms/dummy.acpi/oem0.asl b/platforms/dummy.acpi/oem0.asl new file mode 100644 index 0000000..6b9e810 --- /dev/null +++ b/platforms/dummy.acpi/oem0.asl @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org> + * + * [OEMx] OEM Specific Table + * Format: [ByteLength] FieldName : HexFieldValue + * + * This source is released under the terms of the GPLv2. + */ + +[0004] Signature : "OEM0" +[0004] Table Length : 00000024 +[0001] Revision : 01 +[0001] Checksum : 8B +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "DUMMY " +[0004] Oem Revision : 0000000A +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20100528 diff --git a/platforms/dummy.acpi/pmtt.asl b/platforms/dummy.acpi/pmtt.asl new file mode 100644 index 0000000..a337c99 --- /dev/null +++ b/platforms/dummy.acpi/pmtt.asl @@ -0,0 +1,105 @@ +/* + * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org> + * + * [PMTT] Platform Memory Topology Table + * Format: [ByteLength] FieldName : HexFieldValue + * + * This source is released under the terms of the GPLv2. + */ + +[0004] Signature : "PMTT" +[0004] Table Length : 000000B4 +[0001] Revision : 01 +[0001] Checksum : 3A +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "DUMMY " +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20110826 + +[0004] Reserved : 00000000 + +[0001] Subtable Type : 00 [Socket] +[0001] Reserved : 00 +[0002] Length : 0080 +[0002] Flags (decoded below) : 0001 + Top-level Device : 1 + Physical Element : 0 + Memory Type : 0 +[0002] Reserved : 0000 +[0002] Socket ID : 0000 +[0002] Reserved : 0000 + +[0001] Subtable Type : 01 [Memory Controller] +[0001] Reserved : 00 +[0002] Length : 0054 +[0002] Flags (decoded below) : 0005 + Top-level Device : 1 + Physical Element : 0 + Memory Type : 1 +[0002] Reserved : 0000 +[0004] Read Latency : 00000000 +[0004] Write Latency : 00000000 +[0004] Read Bandwidth : 00000000 +[0004] Write Bandwidth : 00000000 +[0002] Access Width : 0000 +[0002] Alignment : 0000 +[0002] Reserved : 0000 +[0002] Domain Count : 0003 +[0004] Proximity Domain : 00000000 +[0004] Proximity Domain : 00000000 +[0004] Proximity Domain : 00000000 + +[0001] Subtable Type : 02 [Physical Component (DIMM)] +[0001] Reserved : 00 +[0002] Length : 0014 +[0002] Flags (decoded below) : 0002 + Top-level Device : 0 + Physical Element : 1 + Memory Type : 0 +[0002] Reserved : 0000 +[0002] Component ID : 0000 +[0002] Reserved : 0000 +[0004] Memory Size : 00000000 +[0004] Bios Handle : 00000000 + +[0001] Subtable Type : 02 [Physical Component (DIMM)] +[0001] Reserved : 00 +[0002] Length : 0014 +[0002] Flags (decoded below) : 0002 + Top-level Device : 0 + Physical Element : 1 + Memory Type : 0 +[0002] Reserved : 0000 +[0002] Component ID : 0000 +[0002] Reserved : 0000 +[0004] Memory Size : 00000000 +[0004] Bios Handle : 00000000 + +[0001] Subtable Type : 01 [Memory Controller] +[0001] Reserved : 00 +[0002] Length : 0020 +[0002] Flags (decoded below) : 0001 + Top-level Device : 1 + Physical Element : 0 + Memory Type : 0 +[0002] Reserved : 0000 +[0004] Read Latency : 00000000 +[0004] Write Latency : 00000000 +[0004] Read Bandwidth : 00000000 +[0004] Write Bandwidth : 00000000 +[0002] Access Width : 0000 +[0002] Alignment : 0000 +[0002] Reserved : 0000 +[0002] Domain Count : 0000 + +[0001] Subtable Type : 00 [Socket] +[0001] Reserved : 00 +[0002] Length : 000C +[0002] Flags (decoded below) : 0001 + Top-level Device : 1 + Physical Element : 0 + Memory Type : 0 +[0002] Reserved : 0000 +[0002] Socket ID : 0000 +[0002] Reserved : 0000 diff --git a/platforms/dummy.acpi/rsdp.asl b/platforms/dummy.acpi/rsdp.asl new file mode 100644 index 0000000..3460a77 --- /dev/null +++ b/platforms/dummy.acpi/rsdp.asl @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org> + * + * [RSDP] ACPI Table + * + * This source is released under the terms of the GPLv2. + */ + +[0008] Signature : "RSD PTR " +[0001] Checksum : 43 +[0006] Oem ID : "LINARO" +[0001] Revision : 02 +[0004] RSDT Address : 00000000 +[0004] Length : 00000024 +[0008] XSDT Address : 0000000000000000 +[0001] Extended Checksum : DC +[0003] Reserved : 000000 diff --git a/platforms/dummy.acpi/rsdt.asl b/platforms/dummy.acpi/rsdt.asl new file mode 100644 index 0000000..a94868f --- /dev/null +++ b/platforms/dummy.acpi/rsdt.asl @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org> + * + * [RSDT] ACPI Table + * Format: [ByteLength] FieldName : HexFieldValue + * + * This source is released under the terms of the GPLv2. + */ + +[0004] Signature : "RSDT" +[0004] Table Length : 00000044 +[0001] Revision : 01 +[0001] Checksum : 8B +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "DUMMY " +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20100528 + +[0008] ACPI Table Address 0 : 42009000 /* FACP */ diff --git a/platforms/dummy.acpi/s3pt.asl b/platforms/dummy.acpi/s3pt.asl new file mode 100644 index 0000000..694caf7 --- /dev/null +++ b/platforms/dummy.acpi/s3pt.asl @@ -0,0 +1,26 @@ +/* + * Intel ACPI Component Architecture + * iASL Compiler/Disassembler version 20130117-64 [Jan 31 2013] + * Copyright (c) 2000 - 2013 Intel Corporation + * + * Template for [S3PT] ACPI Table + * Format: [ByteLength] FieldName : HexFieldValue + */ + +[0004] Signature : "S3PT" [S3 Performance Table] +[0004] Length : 00000034 + +[0002] Type : 0000 +[0001] Length : 18 +[0001] Revision : 01 + +[0004] Resume Count : 00000000 +[0008] Full Resume : 0000000000000000 +[0008] Average Resume : 0000000000000000 + +[0002] Type : 0001 +[0001] Length : 14 +[0001] Revision : 01 + +[0008] Suspend Start : 0000000000000000 +[0008] Suspend End : 0000000000000000 diff --git a/platforms/dummy.acpi/sbst.asl b/platforms/dummy.acpi/sbst.asl new file mode 100644 index 0000000..714b15f --- /dev/null +++ b/platforms/dummy.acpi/sbst.asl @@ -0,0 +1,22 @@ +/* + * Intel ACPI Component Architecture + * iASL Compiler/Disassembler version 20130117-64 [Jan 31 2013] + * Copyright (c) 2000 - 2013 Intel Corporation + * + * Template for [SBST] ACPI Table + * Format: [ByteLength] FieldName : HexFieldValue + */ + +[0004] Signature : "SBST" [Smart Battery Specification Table] +[0004] Table Length : 00000030 +[0001] Revision : 01 +[0001] Checksum : 06 +[0006] Oem ID : "INTEL " +[0008] Oem Table ID : "TEMPLATE" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20100528 + +[0004] Warning Level : 00000000 +[0004] Low Level : 00000000 +[0004] Critical Level : 00000000 diff --git a/platforms/dummy.acpi/slic.asl b/platforms/dummy.acpi/slic.asl new file mode 100644 index 0000000..df77bf2 --- /dev/null +++ b/platforms/dummy.acpi/slic.asl @@ -0,0 +1,56 @@ +/* + * Intel ACPI Component Architecture + * iASL Compiler/Disassembler version 20130117-64 [Jan 31 2013] + * Copyright (c) 2000 - 2013 Intel Corporation + * + * Template for [SLIC] ACPI Table + * Format: [ByteLength] FieldName : HexFieldValue + */ + +[0004] Signature : "SLIC" [Software Licensing Description Table] +[0004] Table Length : 00000176 +[0001] Revision : 01 +[0001] Checksum : 07 +[0006] Oem ID : "INTEL " +[0008] Oem Table ID : "TEMPLATE" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20110211 + + +[0004] Subtable Type : 00000000 [Public Key Structure] +[0004] Length : 0000009C + +[0001] Key Type : 06 +[0001] Version : 02 +[0002] Reserved : 0000 +[0004] Algorithm : 00002400 +[0004] Magic : "RSA1" +[0004] BitLength : 00000400 +[0004] Exponent : 00000000 +[0128] Modulus : 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 \ + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 \ + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 \ + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 \ + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 \ + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 \ + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 \ + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + +[0004] Subtable Type : 00000001 [Windows Marker Structure] +[0004] Length : 000000B6 + +[0004] Version : 00020000 +[0006] Oem ID : "INTEL " +[0008] Oem Table ID : "TEMPLATE" +[0008] Windows Flag : "WINDOWS " +[0004] SLIC Version : 00020001 +[0016] Reserved : 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +[0128] Signature : 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 \ + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 \ + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 \ + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 \ + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 \ + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 \ + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 \ + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/platforms/dummy.acpi/slit.asl b/platforms/dummy.acpi/slit.asl new file mode 100644 index 0000000..ecaadd8 --- /dev/null +++ b/platforms/dummy.acpi/slit.asl @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org> + * + * [SLIT] System Locality Information Table + * Format: [ByteLength] FieldName : HexFieldValue + * + * This source is released under the terms of the GPLv2. + */ + +[0004] Signature : "SLIT" +[0004] Table Length : 000001BC +[0001] Revision : 01 +[0001] Checksum : 00 +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "DUMMY " +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20110316 + +[0008] Localities : 0000000000000014 +[0020] Locality 0 : 0A 10 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 \ + 24 25 26 27 +[0020] Locality 1 : 10 0A 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 \ + 23 24 25 26 +[0020] Locality 2 : 16 15 0A 10 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 \ + 22 23 24 25 +[0020] Locality 3 : 17 16 10 0A 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 \ + 21 22 23 24 +[0020] Locality 4 : 18 17 16 15 0A 10 16 17 18 19 1A 1B 1C 1D 1E 1F \ + 20 21 22 23 +[0020] Locality 5 : 19 18 17 16 10 0A 15 16 17 18 19 1A 1B 1C 1D 1E \ + 1F 20 21 22 +[0020] Locality 6 : 1A 19 18 17 16 15 0A 10 16 17 18 19 1A 1B 1C 1D \ + 1E 1F 20 21 +[0020] Locality 7 : 1B 1A 19 18 17 16 10 0A 15 16 17 18 19 1A 1B 1C \ + 1D 1E 1F 20 +[0020] Locality 8 : 1C 1B 1A 19 18 17 16 15 0A 10 16 17 18 19 1A 1B \ + 1C 1D 1E 1F +[0020] Locality 9 : 1D 1C 1B 1A 19 18 17 16 10 0A 15 16 17 18 19 1A \ + 1B 1C 1D 1E +[0020] Locality 10 : 1E 1D 1C 1B 1A 19 18 17 16 15 0A 10 16 17 18 19 \ + 1A 1B 1C 1D +[0020] Locality 11 : 1F 1E 1D 1C 1B 1A 19 18 17 16 10 0A 15 16 17 18 \ + 19 1A 1B 1C +[0020] Locality 12 : 20 1F 1E 1D 1C 1B 1A 19 18 17 16 15 0A 10 16 17 \ + 18 19 1A 1B +[0020] Locality 13 : 21 20 1F 1E 1D 1C 1B 1A 19 18 17 16 10 0A 15 16 \ + 17 18 19 1A +[0020] Locality 14 : 22 21 20 1F 1E 1D 1C 1B 1A 19 18 17 16 15 0A 10 \ + 16 17 18 19 +[0020] Locality 15 : 23 22 21 20 1F 1E 1D 1C 1B 1A 19 18 17 16 10 0A \ + 15 16 17 18 +[0020] Locality 16 : 24 23 22 21 20 1F 1E 1D 1C 1B 1A 19 18 17 16 15 \ + 0A 10 16 17 +[0020] Locality 17 : 25 24 23 22 21 20 1F 1E 1D 1C 1B 1A 19 18 17 16 \ + 10 0A 15 16 +[0020] Locality 18 : 26 25 24 23 22 21 20 1F 1E 1D 1C 1B 1A 19 18 17 \ + 16 15 0A 10 +[0020] Locality 19 : 27 26 25 24 23 22 21 20 1F 1E 1D 1C 1B 1A 19 18 \ + 17 16 10 0A diff --git a/platforms/dummy.acpi/spcr.asl b/platforms/dummy.acpi/spcr.asl new file mode 100644 index 0000000..7998ba8 --- /dev/null +++ b/platforms/dummy.acpi/spcr.asl @@ -0,0 +1,46 @@ +/* + * Intel ACPI Component Architecture + * iASL Compiler/Disassembler version 20130117-64 [Jan 31 2013] + * Copyright (c) 2000 - 2013 Intel Corporation + * + * Template for [SPCR] ACPI Table + * Format: [ByteLength] FieldName : HexFieldValue + */ + +[0004] Signature : "SPCR" [Serial Port Console Redirection table] +[0004] Table Length : 00000050 +[0001] Revision : 01 +[0001] Checksum : E3 +[0006] Oem ID : "INTEL " +[0008] Oem Table ID : "TEMPLATE" +[0004] Oem Revision : 00000000 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20100528 + +[0001] Interface Type : 00 +[0003] Reserved : 000000 + +[0012] Serial Port Register : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 08 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 00 [Undefined/Legacy] +[0008] Address : 0000000000000000 + +[0001] Interrupt Type : 00 +[0001] PCAT-compatible IRQ : 00 +[0004] Interrupt : 00000000 +[0001] Baud Rate : 00 +[0001] Parity : 00 +[0001] Stop Bits : 00 +[0001] Flow Control : 00 +[0001] Terminal Type : 00 +[0001] Reserved : 00 +[0002] PCI Device ID : 0000 +[0002] PCI Vendor ID : 0000 +[0001] PCI Bus : 00 +[0001] PCI Device : 00 +[0001] PCI Function : 00 +[0004] PCI Flags : 00000000 +[0001] PCI Segment : 00 +[0004] Reserved : 00000000 diff --git a/platforms/dummy.acpi/spmi.asl b/platforms/dummy.acpi/spmi.asl new file mode 100644 index 0000000..0fe75e5 --- /dev/null +++ b/platforms/dummy.acpi/spmi.asl @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org + * + * [SPMI] Server Platform Management Interface Table + * Format: [ByteLength] FieldName : HexFieldValue + * + * This source is released under the terms of the GPLv2. + */ + +[0004] Signature : "SPMI" +[0004] Table Length : 00000041 +[0001] Revision : 04 +[0001] Checksum : ED +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "DUMMY " +[0004] Oem Revision : 00000000 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20100528 + +[0001] Interface Type : 00 +[0001] Reserved : 00 +[0002] IPMI Spec Version : 0000 +[0001] Interrupt Type : 00 +[0001] GPE Number : 00 +[0001] Reserved : 00 +[0001] PCI Device Flag : 00 +[0004] Interrupt : 00000000 + +[0012] IPMI Register : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 08 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 01 [Byte Access:8] +[0008] Address : 0000000000000000 + +[0001] PCI Segment : 00 +[0001] PCI Bus : 00 +[0001] PCI Device : 00 +[0001] PCI Function : 00 +[0001] Reserved : 00 diff --git a/platforms/dummy.acpi/srat.asl b/platforms/dummy.acpi/srat.asl new file mode 100644 index 0000000..f82c4ae --- /dev/null +++ b/platforms/dummy.acpi/srat.asl @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org> + * + * [SRAT] System Resource Affinity Table + * Format: [ByteLength] FieldName : HexFieldValue + * + * This source is released under the terms of the GPLv2. + */ + +[0004] Signature : "SRAT" +[0004] Table Length : 00000080 +[0001] Revision : 03 +[0001] Checksum : 5A +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "DUMMY " +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20100528 + +[0004] Table Revision : 00000001 +[0008] Reserved : 0000000000000000 + +[0001] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity] +[0001] Length : 10 + +[0001] Proximity Domain Low(8) : 00 +[0001] Apic ID : 00 +[0004] Flags (decoded below) : 00000001 + Enabled : 1 +[0001] Local Sapic EID : 00 +[0003] Proximity Domain High(24) : 000000 +[0004] Reserved : 00000000 + +[0001] Subtable Type : 01 [Memory Affinity] +[0001] Length : 28 + +[0004] Proximity Domain : 00000000 +[0002] Reserved1 : 0000 +[0008] Base Address : 0000000000000000 +[0008] Address Length : 000000000009FC00 +[0004] Reserved2 : 00000000 +[0004] Flags (decoded below) : 00000001 + Enabled : 1 + Hot Pluggable : 0 + Non-Volatile : 0 +[0008] Reserved3 : 0000000000000000 + +[0001] Subtable Type : 02 [Processor Local x2APIC Affinity] +[0001] Length : 18 + +[0002] Reserved1 : 0000 +[0004] Proximity Domain : 00000000 +[0004] Apic ID : 00000000 +[0004] Flags (decoded below) : 00000001 + Enabled : 1 +[0004] Clock Domain : 00000000 +[0004] Reserved2 : 00000000 diff --git a/platforms/dummy.acpi/ssdt0.asl b/platforms/dummy.acpi/ssdt0.asl new file mode 100644 index 0000000..5d593ef --- /dev/null +++ b/platforms/dummy.acpi/ssdt0.asl @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org> + * + * [SSDT] Null Description + * + * This source is released under the terms of the GPLv2. + */ + +DefinitionBlock ( + "ssdt0.aml", // output filename + "SSDT", // table signature + 2, // SSDT compliance revision + "LINARO", // OEM ID + "DUMMY ", // table ID + 0x00000001) // OEM revision +{ +} diff --git a/platforms/dummy.acpi/tcpa.asl b/platforms/dummy.acpi/tcpa.asl new file mode 100644 index 0000000..cfdfa39 --- /dev/null +++ b/platforms/dummy.acpi/tcpa.asl @@ -0,0 +1,22 @@ +/* + * Intel ACPI Component Architecture + * iASL Compiler/Disassembler version 20130117-64 [Jan 31 2013] + * Copyright (c) 2000 - 2013 Intel Corporation + * + * Template for [TCPA] ACPI Table + * Format: [ByteLength] FieldName : HexFieldValue + */ + +[0004] Signature : "TCPA" [Trusted Computing Platform Alliance table] +[0004] Table Length : 00000032 +[0001] Revision : 01 +[0001] Checksum : 67 +[0006] Oem ID : "INTEL " +[0008] Oem Table ID : "TEMPLATE" +[0004] Oem Revision : 00003180 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20100528 + +[0002] Reserved : 0000 +[0004] Max Event Log Length : 00000000 +[0008] Event Log Address : 0000000000000001 diff --git a/platforms/dummy.acpi/tpm2.asl b/platforms/dummy.acpi/tpm2.asl new file mode 100644 index 0000000..38cc502 --- /dev/null +++ b/platforms/dummy.acpi/tpm2.asl @@ -0,0 +1,22 @@ +/* + * Intel ACPI Component Architecture + * iASL Compiler/Disassembler version 20130117-64 [Jan 31 2013] + * Copyright (c) 2000 - 2013 Intel Corporation + * + * Template for [TPM2] ACPI Table + * Format: [ByteLength] FieldName : HexFieldValue + */ + +[0004] Signature : "TPM2" [Trusted Platform Module hardware interface table] +[0004] Table Length : 00000034 +[0001] Revision : 03 +[0001] Checksum : 42 +[0006] Oem ID : "INTEL " +[0008] Oem Table ID : "TEMPLATE" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20121114 + +[0004] Flags : 00000000 +[0008] Control Address : 0011223344556677 +[0004] Start Method : 00000001 diff --git a/platforms/dummy.acpi/uefi.asl b/platforms/dummy.acpi/uefi.asl new file mode 100644 index 0000000..efad184 --- /dev/null +++ b/platforms/dummy.acpi/uefi.asl @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org> + * + * [UEFI] UEFI Boot Optimization Table + * Format: [ByteLength] FieldName : HexFieldValue + * + * This source is released under the terms of the GPLv2. + */ + +[0004] Signature : "UEFI" +[0004] Table Length : 00000036 +[0001] Revision : 01 +[0001] Checksum : 9B +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "DUMMY " +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20100528 + +[0016] UUID Identifier : 03020100-0504-0706-0809-0A0B0C0D0E0F +[0002] Data Offset : 0000 diff --git a/platforms/dummy.acpi/waet.asl b/platforms/dummy.acpi/waet.asl new file mode 100644 index 0000000..b459110 --- /dev/null +++ b/platforms/dummy.acpi/waet.asl @@ -0,0 +1,22 @@ +/* + * Intel ACPI Component Architecture + * iASL Compiler/Disassembler version 20130117-64 [Jan 31 2013] + * Copyright (c) 2000 - 2013 Intel Corporation + * + * Template for [WAET] ACPI Table + * Format: [ByteLength] FieldName : HexFieldValue + */ + +[0004] Signature : "WAET" [Windows ACPI Emulated Devices Table] +[0004] Table Length : 00000028 +[0001] Revision : 01 +[0001] Checksum : 19 +[0006] Oem ID : "INTEL " +[0008] Oem Table ID : "TEMPLATE" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20100528 + +[0004] Flags (decoded below) : 00000000 + RTC needs no INT ack : 0 + PM timer, one read only : 0 diff --git a/platforms/dummy.acpi/wdat.asl b/platforms/dummy.acpi/wdat.asl new file mode 100644 index 0000000..e49205a --- /dev/null +++ b/platforms/dummy.acpi/wdat.asl @@ -0,0 +1,47 @@ +/* + * Intel ACPI Component Architecture + * iASL Compiler/Disassembler version 20130117-64 [Jan 31 2013] + * Copyright (c) 2000 - 2013 Intel Corporation + * + * Template for [WDAT] ACPI Table + * Format: [ByteLength] FieldName : HexFieldValue + */ + +[0004] Signature : "WDAT" [Watchdog Action Table] +[0004] Table Length : 0000005C +[0001] Revision : 01 +[0001] Checksum : E3 +[0006] Oem ID : "INTEL " +[0008] Oem Table ID : "TEMPLATE" +[0004] Oem Revision : 00000000 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20100528 + +[0004] Header Length : 00000020 +[0002] PCI Segment : 00FF +[0001] PCI Bus : FF +[0001] PCI Device : FF +[0001] PCI Function : FF +[0003] Reserved : 000000 +[0004] Timer Period : 00000258 +[0004] Max Count : 000003FF +[0004] Min Count : 00000002 +[0001] Flags (decoded below) : 00 + Enabled : 0 + Stopped When Asleep : 0 +[0003] Reserved : 000000 +[0004] Watchdog Entry Count : 0000000E + +[0001] Watchdog Action : 01 +[0001] Instruction : 02 +[0002] Reserved : 0000 + +[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 01 [SystemIO] +[0001] Bit Width : 10 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 02 [Word Access:16] +[0008] Address : 0000000000000460 + +[0004] Value : 00000001 +[0004] Register Mask : 00000001 diff --git a/platforms/dummy.acpi/wddt.asl b/platforms/dummy.acpi/wddt.asl new file mode 100644 index 0000000..a0b039e --- /dev/null +++ b/platforms/dummy.acpi/wddt.asl @@ -0,0 +1,44 @@ +/* + * Intel ACPI Component Architecture + * iASL Compiler/Disassembler version 20130117-64 [Jan 31 2013] + * Copyright (c) 2000 - 2013 Intel Corporation + * + * Template for [WDDT] ACPI Table + * Format: [ByteLength] FieldName : HexFieldValue + */ + +[0004] Signature : "WDDT" [Watchdog Description Table] +[0004] Table Length : 00000040 +[0001] Revision : 01 +[0001] Checksum : 00 +[0006] Oem ID : "INTEL " +[0008] Oem Table ID : "TEMPLATE" +[0004] Oem Revision : 00000000 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20100528 + +[0002] Specification Version : 0000 +[0002] Table Version : 0000 +[0002] PCI Vendor ID : 0000 + +[0012] Timer Register : [Generic Address Structure] +[0001] Space ID : 01 [SystemIO] +[0001] Bit Width : FF +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 00 [Undefined/Legacy] +[0008] Address : 0000000000000000 + +[0002] Max Count : 0000 +[0002] Min Count : 0000 +[0002] Period : 0000 +[0002] Status (decoded below) : 0000 + Available : 0 + Active : 0 + OS Owns : 0 + User Reset : 0 + Timeout Reset : 0 + Power Fail Reset : 0 + Unknown Reset : 0 +[0002] Capability (decoded below) : 0000 + Auto Reset : 0 + Timeout Alert : 0 diff --git a/platforms/dummy.acpi/wdrt.asl b/platforms/dummy.acpi/wdrt.asl new file mode 100644 index 0000000..14453c7 --- /dev/null +++ b/platforms/dummy.acpi/wdrt.asl @@ -0,0 +1,42 @@ +/* + * Intel ACPI Component Architecture + * iASL Compiler/Disassembler version 20130117-64 [Jan 31 2013] + * Copyright (c) 2000 - 2013 Intel Corporation + * + * Template for [WDRT] ACPI Table + * Format: [ByteLength] FieldName : HexFieldValue + */ + +[0004] Signature : "WDRT" [Watchdog Resource Table] +[0004] Table Length : 00000047 +[0001] Revision : 01 +[0001] Checksum : B0 +[0006] Oem ID : "INTEL " +[0008] Oem Table ID : "TEMPLATE" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20100528 + + +[0012] Control Register : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 20 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 00 [Undefined/Legacy] +[0008] Address : 0000000000000000 + +[0012] Count Register : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 20 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 00 [Undefined/Legacy] +[0008] Address : 0000000000000000 + +[0002] PCI Device ID : FFFF +[0002] PCI Vendor ID : FFFF +[0001] PCI Bus : 00 +[0001] PCI Device : 00 +[0001] PCI Function : 00 +[0001] PCI Segment : 00 +[0002] Max Count : FFFF +[0001] Counter Units : 00 diff --git a/platforms/dummy.acpi/xsdt.asl b/platforms/dummy.acpi/xsdt.asl new file mode 100644 index 0000000..ff718be --- /dev/null +++ b/platforms/dummy.acpi/xsdt.asl @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2013, Al Stone <al.stone(a)linaro.org> + * + * [XSDT] Extended System Description Table + * Format: [ByteLength] FieldName : HexFieldValue + * + * This source is released under the terms of the GPLv2. + */ + +[0004] Signature : "XSDT" +[0004] Table Length : 00000064 +[0001] Revision : 01 +[0001] Checksum : 8B +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "DUMMY " +[0004] Oem Revision : 00000014 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20100528 + +[0008] ACPI Table Address 0 : 0000000000000010 +[0008] ACPI Table Address 0 : 0000000000000020 +[0008] ACPI Table Address 0 : 0000000000000030 +[0008] ACPI Table Address 0 : 0000000000000040 +[0008] ACPI Table Address 0 : 0000000000000050 +[0008] ACPI Table Address 0 : 0000000000000060 +[0008] ACPI Table Address 0 : 0000000000000070 +[0008] ACPI Table Address 0 : 0000000000000080 +[0008] ACPI Table Address 0 : 0000000000000090 +[0008] ACPI Table Address 0 : 00000000000000A0 +[0008] ACPI Table Address 0 : 00000000000000B0 +[0008] ACPI Table Address 0 : 00000000000000C0 +[0008] ACPI Table Address 0 : 00000000000000D0 +[0008] ACPI Table Address 0 : 00000000000000E0 +[0008] ACPI Table Address 0 : 00000000000000F0 +[0008] ACPI Table Address 0 : 0000000000000100 +[0008] ACPI Table Address 0 : 0000000000000110 +[0008] ACPI Table Address 0 : 0000000000000120 +[0008] ACPI Table Address 0 : 0000000000000130 +[0008] ACPI Table Address 0 : 0000000000000140 -- 1.8.1.4

11 years, 11 months

Wiki page on the implications of the Reduced Hardware Profile

by Al Stone

As I've been working through the detailed requirements of the reduced hardware mode in ACPI, and more particularly, working through where the current Linux implementation is either lacking or incorrect, I had a bunch of hand-scribbled notes scattered around. Since those had a bit of a tendency to wander off, I finally put them all in a wiki page: https://wiki.linaro.org/LEG/Engineering/Kernel/ACPI/AcpiReducedHw Now it will be much easier to lose them all at once. If there are corrections needed or things missing, feel free to edit the page or let me know. -- ciao, al ----------------------------------- Al Stone Software Engineer Linaro Enterprise Group al.stone(a)linaro.org -----------------------------------

11 years, 11 months

ACPI ASL git repository

by Graeme Gregory

Hi, I have moved the acpi asl definitions out of the kernel repository into their own repository so that they can be used for building UEFI. The new repository for ASL is :- http://git.linaro.org/gitweb?p=arm/acpi/acpi-asl.git;a=summary There will be a strict all patches require one Ack policy on this repo for changes. And a NAK will deny access. Currently there are two platforms defined in the platforms/ directory. One for the Arndale board and one for the foundation v8 model. Obviously this ASL is currently a work in progress. For acpi team members the "blob" can be built with mab using either :- make exynos5250-arndale.acpi or make foundation-v8.acpi in the root directory of the repo. Thanks Graeme

11 years, 11 months

[PATCH 1/3] cpu topology: remove stale arch_provides_topology_pointers and define_siblings_show_map/list()

by Hanjun Guo

arch_provides_topology_pointers was introduced in commit 23ca4bba3 (x86: cleanup early per cpu variables/accesses v4) to indicate pointers to the topology cpumask_t maps are valid to avoid copying data on to/off of the stack. But later in commit fbd59a8d (cpumask: Use topology_core_cpumask()/ topology_thread_cpumask()), the pointers to the topology struct cpumask maps are always valid. After that commit, the only difference is that there is a redundant "unsigned int cpu = dev->id;" if arch_provides_topology_pointers defined, but dev->id is type 'u32' which devolves to 'unsigned int' on all supported arches. So this arch_provides_topology_pointers define is pointless and only cause obfuscation now, remove it. Tested on x86 machine, topology information in sys/devices/system/cpu/ cpuX/topology/ is the same after appling this patch set. Signed-off-by: Hanjun Guo <hanjun.guo(a)linaro.org> --- drivers/base/topology.c | 20 -------------------- 1 file changed, 20 deletions(-) diff --git a/drivers/base/topology.c b/drivers/base/topology.c index 2f5919e..94ffee3 100644 --- a/drivers/base/topology.c +++ b/drivers/base/topology.c @@ -62,25 +62,6 @@ static ssize_t show_cpumap(int type, const struct cpumask *mask, char *buf) } #endif -#ifdef arch_provides_topology_pointers -#define define_siblings_show_map(name) \ -static ssize_t show_##name(struct device *dev, \ - struct device_attribute *attr, char *buf) \ -{ \ - unsigned int cpu = dev->id; \ - return show_cpumap(0, topology_##name(cpu), buf); \ -} - -#define define_siblings_show_list(name) \ -static ssize_t show_##name##_list(struct device *dev, \ - struct device_attribute *attr, \ - char *buf) \ -{ \ - unsigned int cpu = dev->id; \ - return show_cpumap(1, topology_##name(cpu), buf); \ -} - -#else #define define_siblings_show_map(name) \ static ssize_t show_##name(struct device *dev, \ struct device_attribute *attr, char *buf) \ @@ -95,7 +76,6 @@ static ssize_t show_##name##_list(struct device *dev, \ { \ return show_cpumap(1, topology_##name(dev->id), buf); \ } -#endif #define define_siblings_show_func(name) \ define_siblings_show_map(name); define_siblings_show_list(name) -- 1.7.9.5

11 years, 11 months

acpica-tools for Linaro

by Al Stone

Just an FYI: I've cloned the git tree I use to maintain the acpica-tools package for Debian and put a copy here: https://git.linaro.org/gitweb?p=people/ahs3/acpica-tools.git;a=summary This is of course the ever fun package that includes iasl and acpiexec and acpidump and all of your favorite ACPI user space tools. I've also filed the proper bug to get this into the CI loop. Once it is, the Linaro overlay PPA will get automatically updated with new versions as they get pushed up. In the meantime, it has also been uploaded to Debian unstable and a Fedora repository is also ready (it is still pending final review for Fedora). Latest version pushed is 20130626-1. Apart from corrections, the biggest change is that the package added running the AAPITS tests as part of the build (the ASLTS tests are already being run as part of the build). And, of course, as I expected would happen, 20130725 was just announced by upstream, so I'll push that sometime next week. -- ciao, al ----------------------------------- Al Stone Software Engineer Linaro Enterprise Group al.stone(a)linaro.org -----------------------------------

11 years, 11 months

[PATCH 0/5] ASL fix and virtio converted to ACPI

by Graeme Gregory

In this series I fix a warning that iasl is outputting about DSDT code. I also conver the virtio device to probe via ACPI. The virtio device is a bus which is probeable and contains the block device that is used as the rootfs in the model. Thanks Graeme

11 years, 11 months

acpi branch updated to 3.11-rc2

by Graeme Gregory

Hi Guys, I have rebased our work on 3.11-rc2, there are some quite major changes in the driver/acpi directory. In this release Arndale board seems to be broken oopsing which is nothing to do with our work. For this reason acpi-ltfixes will remain at 3.10 level for now! I have attached the config I used for armv8 Thanks Graeme [ 0.000000] Machine: SAMSUNG EXYNOS5 (Flattened Device Tree), model: Insignal Arndale evaluation board based on EXYNOS5250 [ 0.000000] bootconsole [earlycon0] enabled [ 0.000000] NR_BANKS too low, ignoring high memory [ 0.000000] ------------[ cut here ]------------ [ 0.000000] kernel BUG at mm/vmalloc.c:1134! [ 0.000000] Internal error: Oops - BUG: 0 [#1] PREEMPT SMP ARM [ 0.000000] Modules linked in: [ 0.000000] CPU: 0 PID: 0 Comm: swapper Not tainted 3.11.0-rc2 #202 [ 0.000000] task: c0554c88 ti: c054a000 task.ti: c054a000 [ 0.000000] PC is at vm_area_add_early+0x40/0x80 [ 0.000000] LR is at add_static_vm_early+0xc/0x60 [ 0.000000] pc : [<c051da5c>] lr : [<c0515c6c>] psr: 800001d3 [ 0.000000] sp : c054befc ip : ef7fdec0 fp : 00008402 [ 0.000000] r10: 40000001 r9 : 00010406 r8 : c05163a0 [ 0.000000] r7 : ef7fdf88 r6 : 00000000 r5 : ef7fdf88 r4 : 00080000 [ 0.000000] r3 : ef7fdfd8 r2 : f7020000 r1 : f7080000 r0 : ef7fdf88 [ 0.000000] Flags: Nzcv IRQs off FIQs off Mode SVC_32 ISA ARM Segment kernel [ 0.000000] Control: 10c5387d Table: 4000406a DAC: 00000015 [ 0.000000] Process swapper (pid: 0, stack limit = 0xc054a238) [ 0.000000] Stack: (0xc054befc to 0xc054c000)

11 years, 11 months

[PATCHv2 0/5] Foundation model network by ACPI

by Graeme Gregory

Hi Guys, In the spirit of starting things for our LCU target here is the network device on Foundation model converted to probe from ACPI. Things that have come out of this conversion: 1) we need an ACPI equivalent of simple-bus from FDT 2) we need to decide on how to handle irq domains and especially the domain for the GIC. Changes Since v1 small typo in the ASL and a whitespace change in smc9x driver that should not have been committed. Thanks Graeme

11 years, 11 months

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Linaro-acpi July 2013