Linaro-acpi August 2013

linaro-acpi@lists.linaro.org

15 participants
57 discussions

[PATCH 0/2] Boot Error Record Table (BERT) support

by Tomasz Nowicki

This is re-use existing patch submitted by Huang Ying <ying.huang(a)intel.com> with one small modification (see commits). The first idea was to use just printk to inform about any errors that were not consumed by OS. Errors listed in HEST table should point to the same "Error status block" ESB structures as BERT does. OS handling errors should clear errors status bit in ESB for given error at the end of error recovery procedure. Case where error appeared to be too serious OS can reset machine immediately without clearing bit in ESB. During boot, kernel examine each error status bit from ESB list (pointed from BERT) and see if there are any unhandled errors. BERT table was tested along with HEST and EINJ driver, in the following way: 1. Fill in ESB using EINJ hacked driver and do not clear erros status in ESB, this way unhandler error is simulated and BERT table could be used later: root@localhost:~# echo 1 > /sys/kernel/debug/apei/einj/error_inject 2. Reboot machin and check whether BERT driver notice injected error: ... [ 2.518179] [Hardware Error]: Error record from previous boot: [ 2.523342] [Hardware Error]: APEI generic hardware error status [ 2.548457] [Hardware Error]: severity: 1, fatal [ 2.574705] [Hardware Error]: section: 0, severity: 0, recoverable [ 2.584010] [Hardware Error]: flags: 0x00 [ 2.587937] [Hardware Error]: section_type: memory error ... 3. Kernel clear status bit so next boot would not print it again.

10 years, 6 months

[PATCH 0/6 v2] First of the Arndale GPIO/pinctrl patches

by al.stone＠linaro.org

From: Al Stone <ahs3(a)redhat.com> I should have sent these out for comment much sooner. Once these are in good shape, the next steps are to send patches for verifying that the pinconf code is working properly, connecting up the GPIO interrupts using ACPI, and then conversion of all of the pin controllers for Arndale (this patch converts one of four). This patch puts most of the infrastructure in place so that in the 3.11 kernel the Arndale pin controllers can be converted from FDT to ACPI. The changes in ASL are included in a separate patch. What this allows is for the pin controllers to be described in either FDT or ACPI for Arndale and -- in conjunction with the ASL changes -- shows how to describe a Samsung controller in ACPI. Changes for v2: -- Add patch 6 which allows compilation regardless of whether CONFIG_ACPI is used or not Al Stone (6): ACPI: ARM: arndale: remove GPZ GPIO definition from DT so it can be in ACPI ACPI: ARM: arndale: whitelist the samsung-pinctrl driver for ACPI ACPI: make an error message a little clearer ACPI: improve acpi_extract_package() utility ACPI: ARM: arndale: enable ACPI in the Samsung pinctrl driver ACPI: ARM: arndale: add CONFIG_ACPI ifdef's to pinctrl driver arch/arm/boot/dts/exynos5250-pinctrl.dtsi | 2 + arch/arm/boot/dts/exynos5250.dtsi | 6 +- drivers/acpi/acpi_platform.c | 3 + drivers/acpi/osl.c | 2 +- drivers/acpi/utils.c | 17 +- drivers/pinctrl/pinctrl-samsung.c | 517 +++++++++++++++++++++++++++++- drivers/pinctrl/pinctrl-samsung.h | 3 + 7 files changed, 536 insertions(+), 14 deletions(-) -- 1.8.3.1

10 years, 7 months

CSRT table can be used to describe DMA on SoC

by Hanjun Guo

Hi everyone, I read the wiki about ACPI Table Prioritization: https://wiki.linaro.org/LEG/Engineering/Kernel/ACPI/TablePriorities and I noticed that CSRT is in the *Never Tables* priority, here I got some different opinions. Yes, CSRT or Core System Resources Table is a proprietary ACPI table introduced by Microsoft, but This table can contain devices that are not in the system DSDT table. In particular DMA controllers, Timer, interrupt might be described here. we can get DMA description from DMAR (DMA Remapping Table) tables on Intel platform, but on ARM SoCs, there is no table to describe DMA, only CSRT is available. Actually, the support code of CSRT in Linux kernel already have submitted by Intel on Jan 17 this year, but only DMA is supported, still have something more to do (if needed). So, why not use the CSRT table to describe DMA? Thanks Hanjun

10 years, 7 months

[PATCH 1/6] ACPI / processor: Introduce apic_id in struct processor to save parsed APIC id

by Hanjun Guo

From: Jiang Liu <jiang.liu(a)huawei.com> For cpu hot add, we evaluate _MAT or parse MADT twice to get APIC id, here is the code logic: acpi_processor_add() acpi_processor_get_info() acpi_get_cpuid() will evaluate _MAT or parse MADT; acpi_processor_hotadd_init() acpi_map_lsapic() will evaluate _MAT again; This can be done more effectively, this patch introduces apic_id in struct processor to save parsed APIC id, and then we can use it and remove the duplicated _MAT evaluation. Signed-off-by: Jiang Liu <jiang.liu(a)huawei.com> Signed-off-by: Hanjun Guo <hanjun.guo(a)linaro.org> --- drivers/acpi/acpi_processor.c | 3 ++- drivers/acpi/processor_core.c | 26 +++++++++++++++++++++----- include/acpi/processor.h | 3 +++ 3 files changed, 26 insertions(+), 6 deletions(-) diff --git a/drivers/acpi/acpi_processor.c b/drivers/acpi/acpi_processor.c index f29e06e..d5a6c81 100644 --- a/drivers/acpi/acpi_processor.c +++ b/drivers/acpi/acpi_processor.c @@ -270,7 +270,8 @@ static int acpi_processor_get_info(struct acpi_device *device) device_declaration = 1; pr->acpi_id = value; } - cpu_index = acpi_get_cpuid(pr->handle, device_declaration, pr->acpi_id); + pr->apic_id = acpi_get_apicid(pr->handle, device_declaration, pr->acpi_id); + cpu_index = acpi_map_cpuid(pr->apic_id, pr->acpi_id); /* Handle UP system running SMP kernel, with no LAPIC in MADT */ if (!cpu0_initialized && (cpu_index == -1) && diff --git a/drivers/acpi/processor_core.c b/drivers/acpi/processor_core.c index cf34d90..b3171f3 100644 --- a/drivers/acpi/processor_core.c +++ b/drivers/acpi/processor_core.c @@ -162,16 +162,23 @@ exit: return apic_id; } -int acpi_get_cpuid(acpi_handle handle, int type, u32 acpi_id) +int acpi_get_apicid(acpi_handle handle, int type, u32 acpi_id) { -#ifdef CONFIG_SMP - int i; -#endif - int apic_id = -1; + int apic_id; apic_id = map_mat_entry(handle, type, acpi_id); if (apic_id == -1) apic_id = map_madt_entry(type, acpi_id); + + return apic_id; +} + +int acpi_map_cpuid(int apic_id, u32 acpi_id) +{ +#ifdef CONFIG_SMP + int i; +#endif + if (apic_id == -1) { /* * On UP processor, there is no _MAT or MADT table. @@ -211,6 +218,15 @@ int acpi_get_cpuid(acpi_handle handle, int type, u32 acpi_id) #endif return -1; } + +int acpi_get_cpuid(acpi_handle handle, int type, u32 acpi_id) +{ + int apic_id; + + apic_id = acpi_get_apicid(handle, type, acpi_id); + + return acpi_map_cpuid(apic_id, acpi_id); +} EXPORT_SYMBOL_GPL(acpi_get_cpuid); static bool __init processor_physically_present(acpi_handle handle) diff --git a/include/acpi/processor.h b/include/acpi/processor.h index 66096d0..7816e45 100644 --- a/include/acpi/processor.h +++ b/include/acpi/processor.h @@ -199,6 +199,7 @@ struct acpi_processor_flags { struct acpi_processor { acpi_handle handle; u32 acpi_id; + u32 apic_id; u32 id; u32 pblk; int performance_platform_limit; @@ -314,6 +315,8 @@ static inline int acpi_processor_get_bios_limit(int cpu, unsigned int *limit) /* in processor_core.c */ void acpi_processor_set_pdc(acpi_handle handle); +int acpi_get_apicid(acpi_handle, int type, u32 acpi_id); +int acpi_map_cpuid(int apic_id, u32 acpi_id); int acpi_get_cpuid(acpi_handle, int type, u32 acpi_id); /* in processor_throttling.c */ -- 1.7.9.5

10 years, 7 months

[PATCH 0/2] Enable a second GPIO controller on Arndale

by al.stone＠linaro.org

From: Al Stone <ahs3(a)redhat.com> This adds another GPIO/pinctrl device to Arndale. In the process, logic errors in the portions of the Samsung pinctrl driver that were using ACPI were weeded out. Al Stone (2): ACPI: ARM: arndale: move GPIO controller 3 of 4 from FDT to ACPI ACPI: ARM: arndale: Enable pinctrl for configuring many controllers via ACPI arch/arm/boot/dts/exynos5250-arndale.dts | 26 +++++++++++++++ arch/arm/boot/dts/exynos5250-pinctrl.dtsi | 2 +- arch/arm/boot/dts/exynos5250.dtsi | 6 ++-- drivers/pinctrl/pinctrl-samsung.c | 53 ++++++++++++++++--------------- 4 files changed, 59 insertions(+), 28 deletions(-) -- 1.8.3.1

10 years, 7 months

[PATCH] acpi: arm: remove unused code paths and features

by Graeme Gregory

Tidy the file a bit by removing unused paths. Also removed unused kernel options that do not currently make sense on arm/arm64 Signed-off-by: Graeme Gregory <graeme.gregory(a)linaro.org> --- drivers/acpi/plat/arm/boot.c | 115 ++----------------------------------------- 1 file changed, 5 insertions(+), 110 deletions(-) diff --git a/drivers/acpi/plat/arm/boot.c b/drivers/acpi/plat/arm/boot.c index 8600cd0..881478d 100644 --- a/drivers/acpi/plat/arm/boot.c +++ b/drivers/acpi/plat/arm/boot.c @@ -24,9 +24,6 @@ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */ -/* - * BOZO: this needs to be done right.... - */ #include <linux/init.h> #include <linux/acpi.h> #include <linux/acpi_pmtmr.h> @@ -46,8 +43,12 @@ #include <asm/smp.h> #include <asm/acpi.h> -static int __initdata acpi_force; +/* + * We never plad to use RSDT on arm/arm64 as its deprecated in spec but this + * variable is still required by the ACPI core + */ u32 acpi_rsdt_forced; + int acpi_disabled; EXPORT_SYMBOL(acpi_disabled); @@ -223,56 +224,6 @@ acpi_parse_gic_distributor(struct acpi_subtable_header *header, return 0; } -/* - * acpi_pic_sci_set_trigger() - * - * use ELCR to set PIC-mode trigger type for SCI - * - * If a PIC-mode SCI is not recognized or gives spurious IRQ7's - * it may require Edge Trigger -- use "acpi_sci=edge" - * - * Port 0x4d0-4d1 are ECLR1 and ECLR2, the Edge/Level Control Registers - * for the 8259 PIC. bit[n] = 1 means irq[n] is Level, otherwise Edge. - * ECLR1 is IRQs 0-7 (IRQ 0, 1, 2 must be 0) - * ECLR2 is IRQs 8-15 (IRQ 8, 13 must be 0) - */ - -void __init acpi_pic_sci_set_trigger(unsigned int irq, u16 trigger) -{ - unsigned int mask = 1 << irq; - unsigned int old, new; - - /* Real old ELCR mask */ - old = inb(0x4d0) | (inb(0x4d1) << 8); - - /* - * If we use ACPI to set PCI IRQs, then we should clear ELCR - * since we will set it correctly as we enable the PCI irq - * routing. - */ - new = acpi_noirq ? old : 0; - - /* - * Update SCI information in the ELCR, it isn't in the PCI - * routing tables.. - */ - switch (trigger) { - case 1: /* Edge - clear */ - new &= ~mask; - break; - case 3: /* Level - set */ - new |= mask; - break; - } - - if (old == new) - return; - - printk(PREFIX "setting ELCR to %04x (from %04x)\n", new, old); - outb(new, 0x4d0); - outb(new >> 8, 0x4d1); -} - int acpi_gsi_to_irq(u32 gsi, unsigned int *irq) { *irq = gsi_to_irq(gsi); @@ -812,70 +763,14 @@ static int __init parse_acpi(char *arg) if (strcmp(arg, "off") == 0) { disable_acpi(); } - /* acpi=force to over-ride black-list */ - else if (strcmp(arg, "force") == 0) { - acpi_force = 1; - acpi_disabled = 0; - } /* acpi=strict disables out-of-spec workarounds */ else if (strcmp(arg, "strict") == 0) { acpi_strict = 1; } - /* acpi=rsdt use RSDT instead of XSDT */ - else if (strcmp(arg, "rsdt") == 0) { - acpi_rsdt_forced = 1; - } - /* "acpi=noirq" disables ACPI interrupt routing */ - else if (strcmp(arg, "noirq") == 0) { - acpi_noirq_set(); - } - /* "acpi=copy_dsdt" copys DSDT */ - else if (strcmp(arg, "copy_dsdt") == 0) { - acpi_gbl_copy_dsdt_locally = 1; - } else { - /* Core will printk when we return error. */ - return -EINVAL; - } return 0; } early_param("acpi", parse_acpi); -/* FIXME: Using pci= for an ACPI parameter is a travesty. */ -static int __init parse_pci(char *arg) -{ - if (arg && strcmp(arg, "noacpi") == 0) - acpi_disable_pci(); - return 0; -} -early_param("pci", parse_pci); - -int __init acpi_mps_check(void) -{ - return 0; -} - -static int __init setup_acpi_sci(char *s) -{ - if (!s) - return -EINVAL; - if (!strcmp(s, "edge")) - acpi_sci_flags = ACPI_MADT_TRIGGER_EDGE | - (acpi_sci_flags & ~ACPI_MADT_TRIGGER_MASK); - else if (!strcmp(s, "level")) - acpi_sci_flags = ACPI_MADT_TRIGGER_LEVEL | - (acpi_sci_flags & ~ACPI_MADT_TRIGGER_MASK); - else if (!strcmp(s, "high")) - acpi_sci_flags = ACPI_MADT_POLARITY_ACTIVE_HIGH | - (acpi_sci_flags & ~ACPI_MADT_POLARITY_MASK); - else if (!strcmp(s, "low")) - acpi_sci_flags = ACPI_MADT_POLARITY_ACTIVE_LOW | - (acpi_sci_flags & ~ACPI_MADT_POLARITY_MASK); - else - return -EINVAL; - return 0; -} -early_param("acpi_sci", setup_acpi_sci); - int __acpi_acquire_global_lock(unsigned int *lock) { unsigned int old, new, val; -- 1.8.3.1

10 years, 7 months

[PATCH 1/2] Remove __cpuinit and fix __init attribute location

by Hanjun Guo

__cpuinit is gone in kernel now, remove them. __init belongs after the return type on functions, not before, correct them too. Signed-off-by: Hanjun Guo <hanjun.guo(a)linaro.org> --- drivers/acpi/plat/arm/boot.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/acpi/plat/arm/boot.c b/drivers/acpi/plat/arm/boot.c index 8600cd0..928f6c9 100644 --- a/drivers/acpi/plat/arm/boot.c +++ b/drivers/acpi/plat/arm/boot.c @@ -147,7 +147,7 @@ static int __init acpi_parse_madt(struct acpi_table_header *table) } /* Local APIC = GIC cpu interface on ARM */ -static void __cpuinit acpi_register_lapic(int id, u8 enabled) +static void acpi_register_lapic(int id, u8 enabled) { int cpu; @@ -365,7 +365,7 @@ early_param("possible_cpus", _setup_possible_cpus); * We do this because additional CPUs waste a lot of memory. * -AK */ -__init void prefill_possible_map(void) +void __init prefill_possible_map(void) { int i; int possible, disabled_cpus; @@ -405,7 +405,7 @@ __init void prefill_possible_map(void) #ifdef CONFIG_ACPI_HOTPLUG_CPU #include <acpi/processor.h> -static void __cpuinit acpi_map_cpu2node(acpi_handle handle, int cpu, int physid) +static void acpi_map_cpu2node(acpi_handle handle, int cpu, int physid) { #ifdef CONFIG_ACPI_NUMA int nid; @@ -418,7 +418,7 @@ static void __cpuinit acpi_map_cpu2node(acpi_handle handle, int cpu, int physid) #endif } -static int __cpuinit _acpi_map_lsapic(acpi_handle handle, int *pcpu) +static int _acpi_map_lsapic(acpi_handle handle, int *pcpu) { struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; union acpi_object *obj; @@ -582,7 +582,7 @@ static int __init acpi_parse_hpet(struct acpi_table_header *table) * hpet_insert_resource inserts the HPET resources used into the resource * tree. */ -static __init int hpet_insert_resource(void) +static int __init hpet_insert_resource(void) { if (!hpet_res) return 1; -- 1.7.9.5

10 years, 7 months

[PATCH] ARMv8 foudation model: Fix cpu hot add failure on ARM64

by Hanjun Guo

All values in the ACPI blob are little-endian, but I creat the DSDT table with values in big-endian format, so when I evaluate _MAT object I will get values unexperted, this leads to cpu hot add failure, fix it. Signed-off-by: Hanjun Guo <hanjun.guo(a)linaro.org> --- platforms/foundation-v8.acpi/dsdt.asl | 27 ++++++++++++++------------- 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/platforms/foundation-v8.acpi/dsdt.asl b/platforms/foundation-v8.acpi/dsdt.asl index d1a9716..9c128d3 100644 --- a/platforms/foundation-v8.acpi/dsdt.asl +++ b/platforms/foundation-v8.acpi/dsdt.asl @@ -38,8 +38,9 @@ DefinitionBlock ( Name (MAT0, Buffer (0x28) { + /* Be careful, little-endian here */ /* 0000 */ 0x0B, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* type, len, reserved, gic_id */ - /* 0008 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, /* uid, flags */ + /* 0008 */ 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, /* uid, flags */ /* 0010 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* parking_version, performance_interrupt */ /* 0018 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* parked_address */ /* 0020 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* base_address */ @@ -88,8 +89,8 @@ DefinitionBlock ( Name (MAT0, Buffer (0x28) { - /* 0000 */ 0x0B, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, - /* 0008 */ 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, + /* 0000 */ 0x0B, 0x28, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, + /* 0008 */ 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, /* 0010 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0018 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0020 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 @@ -97,8 +98,8 @@ DefinitionBlock ( Name (MAT1, Buffer (0x28) { - /* 0000 */ 0x0B, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, - /* 0008 */ 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, + /* 0000 */ 0x0B, 0x28, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, + /* 0008 */ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0010 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0018 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0020 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 @@ -138,8 +139,8 @@ DefinitionBlock ( Name (MAT0, Buffer (0x28) { - /* 0000 */ 0x0B, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, - /* 0008 */ 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x01, + /* 0000 */ 0x0B, 0x28, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, + /* 0008 */ 0x02, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, /* 0010 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0018 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0020 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 @@ -147,8 +148,8 @@ DefinitionBlock ( Name (MAT1, Buffer (0x28) { - /* 0000 */ 0x0B, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, - /* 0008 */ 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, + /* 0000 */ 0x0B, 0x28, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, + /* 0008 */ 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0010 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0018 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0020 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 @@ -188,8 +189,8 @@ DefinitionBlock ( Name (MAT0, Buffer (0x28) { - /* 0000 */ 0x0B, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, - /* 0008 */ 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x01, + /* 0000 */ 0x0B, 0x28, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, + /* 0008 */ 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, /* 0010 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0018 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0020 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 @@ -197,8 +198,8 @@ DefinitionBlock ( Name (MAT1, Buffer (0x28) { - /* 0000 */ 0x0B, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, - /* 0008 */ 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, + /* 0000 */ 0x0B, 0x28, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, + /* 0008 */ 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0010 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0018 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0020 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -- 1.7.9.5

10 years, 7 months

[PATCH][acpi-asl] ACPI: ARM: arndale: convert GPIO controller 3 of 4 to ACPI

by al.stone＠linaro.org

From: Al Stone <ahs3(a)redhat.com> This builds on the prior Arndale GPIO patch by adding another controller to the ACPI configuration. Signed-off-by: Al Stone <al.stone(a)linaro.org> --- platforms/exynos5250-arndale.acpi/ssdt0.asl | 156 +++++++++++++++++++++++++++- 1 file changed, 154 insertions(+), 2 deletions(-) diff --git a/platforms/exynos5250-arndale.acpi/ssdt0.asl b/platforms/exynos5250-arndale.acpi/ssdt0.asl index 8b8efc7..48fa409 100644 --- a/platforms/exynos5250-arndale.acpi/ssdt0.asl +++ b/platforms/exynos5250-arndale.acpi/ssdt0.asl @@ -12,10 +12,162 @@ DefinitionBlock ( 2, // SSDT compliance revision "LINARO", // OEM ID "ARNDALE ", // table ID - 0x00000003) // OEM revision + 0x00000004) // OEM revision { Scope (\_SB) { + // Base Address: 0x10d10000 + Device (SPC2) // Samsung pin controller + { + Name (_HID, "LINA0002") + Name (_UID, 0x2) + + Name (BNKS, 0x5) // number of pin banks + Name (NGRP, 0x2) // number of pin groups + + Method (_CRS, 0x0, Serialized) + { + // Base address for the pin controller + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + 0x10d10000, + 0x20) + }) + Return (RBUF) + } + + Device (GPV0) // GPIO chip GPV0 -- first bank + { + Name (TAG, "gpv0") // human-readable name + Name (BASE, 0x0) // base pin number + Name (NPIN, 0x8) // number of pins + + Method (_CRS, 0x0, Serialized) + { + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + 0x10d10000, + 0x20) + }) + Return (RBUF) + } + } + + Device (GPV1) // GPIO chip GPV1 + { + Name (TAG, "gpv1") // human-readable name + Name (BASE, 0x0) // base pin number + Name (NPIN, 0x8) // number of pins + + Method (_CRS, 0x0, Serialized) + { + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + 0x10d10020, + 0x20) + }) + Return (RBUF) + } + } + + Device (GPV2) // GPIO chip GPV2 + { + Name (TAG, "gpv2") // human-readable name + Name (BASE, 0x0) // base pin number + Name (NPIN, 0x8) // number of pins + + Method (_CRS, 0x0, Serialized) + { + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + 0x10d10060, + 0x20) + }) + Return (RBUF) + } + } + + Device (GPV3) // GPIO chip GPV3 + { + Name (TAG, "gpv3") // human-readable name + Name (BASE, 0x0) // base pin number + Name (NPIN, 0x8) // number of pins + + Method (_CRS, 0x0, Serialized) + { + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + 0x10d10080, + 0x20) + }) + Return (RBUF) + } + } + + Device (GPV4) // GPIO chip GPV4 + { + Name (TAG, "gpv4") // human-readable name + Name (BASE, 0x0) // base pin number + Name (NPIN, 0x8) // number of pins + + Method (_CRS, 0x0, Serialized) + { + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + 0x10d100c0, + 0x20) + }) + Return (RBUF) + } + } + + Device (C2RX) // First pin group + { + Name (NPIN, 0x10) // number of pins + Name (FUNC, 0x2) // function number + Name (PUD, 0x0) // direction + Name (DRV, 0x0) // drive + + Method (PINS, 0x0, NotSerialized) + { + Return (Package () { + "gpv0-0", "gpv0-1", "gpv0-2", + "gpv0-3", "gpv0-4", "gpv0-5", + "gpv0-6", "gpv0-7", + "gpv1-0", "gpv1-1", "gpv1-2", + "gpv1-3", "gpv1-4", "gpv1-5", + "gpv1-6", "gpv1-7", + }) + } + } + + Device (C2TX) // second pin group + { + Name (NPIN, 0x10) // number of pins + Name (FUNC, 0x2) // function number + Name (PUD, 0x0) // direction + Name (DRV, 0x0) // drive + + Method (PINS, 0x0, NotSerialized) + { + Return (Package () { + "gpv2-0", "gpv2-1", "gpv2-2", + "gpv2-3", "gpv2-4", "gpv2-5", + "gpv2-6", "gpv2-7", + "gpv3-0", "gpv3-1", "gpv3-2", + "gpv3-3", "gpv3-4", "gpv3-5", + "gpv3-6", "gpv3-7", + }) + } + } + } + // Base Address: 0x03860000 Device (SPC3) // Samsung pin controller { @@ -24,7 +176,6 @@ DefinitionBlock ( Name (BNKS, 0x1) // number of pin banks Name (NGRP, 0x1) // number of pin groups - Name (NFUN, 0x1) // number of pinmux functions Method (_CRS, 0x0, Serialized) { @@ -65,6 +216,7 @@ DefinitionBlock ( Name (FUNC, 0x2) // function number Name (PUD, 0x0) // direction Name (DRV, 0x0) // drive + Method (PINS, 0x0, NotSerialized) { Return (Package () { -- 1.8.3.1

10 years, 7 months

of: fix fdt parsing of acpi blob addr/size for arm64

by Mark Salter

The early_init_dt_scan_acpi() function currently uses be32_to_cpu() helpers to read the "linux,acpi-start" and "linux,acpi-len" properties. This may not be safe for arm64. This patch uses of_read_ulong to read the property values which should be safe for both arm and arm64. Signed-off-by: Mark Salter <msalter(a)redhat.com> --- drivers/of/fdt.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/of/fdt.c b/drivers/of/fdt.c index 875a4c1..d48ab6a 100644 --- a/drivers/of/fdt.c +++ b/drivers/of/fdt.c @@ -720,13 +720,13 @@ int __init early_init_dt_scan_acpi(unsigned long node, const char *uname, /* Retrieve acpi,address line */ pinfo = (struct acpi_arm_root *)data; p = of_get_flat_dt_prop(node, "linux,acpi-start", &l); - if (p != NULL && l > 0) - pinfo->phys_address = be32_to_cpu(*p); + if (p) + pinfo->phys_address = of_read_ulong(p, l/4); /* Retrieve acpi,size line */ p = of_get_flat_dt_prop(node, "linux,acpi-len", &l); - if (p != NULL && l > 0) - pinfo->size = be32_to_cpu(*p); + if (p) + pinfo->size = of_read_ulong(p, l/4); return 1; } -- 1.8.3.1

10 years, 7 months

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Linaro-acpi August 2013