From: "Jonathan (Zhixiong) Zhang" <zjzhang(a)codeaurora.org>
On a platform with APEI (ACPI Platform Error Interface) enabled, firmware
updates a memory region with hardware error record using nocache
attribute. When OS reads the region, since it maps the region with
cacahed attribute even though EFI memory map defines this region as
uncached, OS gets stale data and errorneously reports there is no new
HW error.
When ghes driver maps the memory region, it uses the cache attribute
according to EFI memory map, if EFI memory map feature is enabled
at runtime.
Since both arch/x86 and arch/ia64 implemented architecture agnostic EFI
memory map attribue lookup function efi_memattributes(), the code is
moved from arch/x86 into EFI subsystem and is declared as __weak; archs
other than ia64 should not override the default implementation.
V5:
1. Rebased to next-20150713 of linux-next/master, efi-next-14359 of
efi/next, pm+acpi-4.2-rc2 of linux-pm/master,
arm64-fixes-1215 of arm64/master.
2. Added comment for efi_mem_attributes(), explained why it is marked
as __weak at the function definition site.
V4:
1. Introduced arch_apei_get_mem_attributes() to allow arch specific
implementation of getting pgprot_t appropriate for a physical
address.
2. Implemented arch_apei_get_mem_attributes() for x86 and for arm64.
V3:
1. Rebased to v4.1-rc7.
2. Moved efi_mem_attributes() from arch/x86 to drivers/firmware/efi
and declared it as __weak.
3. Introduced ARCH_APEI_PAGE_KERNEL_UC to allow arch specific page
protection type for UC.
4. Removed efi_ioremap(). It can not be used for GHES memory region
mapping purpose since ioremap can not be used in atomic context.
V2:
1. Rebased to v4.1-rc5.
2. Split removal of efi_mem_attributes() and creation of efi_ioremap()
into two patches.
Jonathan (Zhixiong) Zhang (4):
efi: x86: rearrange efi_mem_attributes()
x86: acpi: implement arch_apei_get_mem_attributes()
arm64: apei: implement arch_apei_get_mem_attributes()
acpi, apei: use appropriate pgprot_t to map GHES memory
arch/arm64/kernel/apei.c | 11 +++++++++++
arch/x86/kernel/acpi/apei.c | 10 ++++++++++
arch/x86/platform/efi/efi.c | 18 ------------------
drivers/acpi/apei/ghes.c | 6 ++++--
drivers/firmware/efi/efi.c | 31 +++++++++++++++++++++++++++++++
include/acpi/apei.h | 1 +
6 files changed, 57 insertions(+), 20 deletions(-)
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
This patch set introduce self-probe infrastructure to init IRQ
controllers and stacked irqdomain support for ACPI based GICv2/3
init.
This patch set add its support for GIC verion which is introduced
in ACPI 6.0, based on that, we introduce the self-probe infrastructure,
the self-probe infrastructure for ACPI GIC init is similar as
IRQCHIP_DECLARE() and based on the GIC version support in ACPI
MADT table. we match the GIC version and GIC driver and load
it.
After the self-probe infrastructure is ready, I cleanuped the GICv2
code to use the framework.
Patch 4 implement the stacked irqdomain support for GICv2 based on
the model of mapping interrupt and device in ACPI.
Patch 5~8 are ACPI based GICv3 init.
Any comments are warmly welcomed.
v2->v3:
- Introduced a mechanism to match the GSI with its irqdomain instead of
referring to the acpi_irq_domain in previous version
- Add finding GICR base address in GICC structures in GICv3 code.
- Address the comments from Lorenzo and Marc
- Rebased on top of 4.2-rc1, since ACPICA patches were pushed to
4.2 by Rafael, I removed ACPICA patches in previous version.
v1->v2:
- Remove the gicv2/v3 related driver code in drivers/irqchip/irq-gic-acpi.c
which I was trying to consolidate them in one file, then arm-gic.h and
arm-gic-v3.h will be used separately within parent driver only
- Drop the gsi_mutex patch
- Use the GIC version to match the GIC driver, then no need to test
for the version in each driver
- Move acpi_irq_init() to drivers/irqchip/irq-gic-acpi.c instead of
in drivers/acpi/irq.c. maybe we need to rename acpi_irq_init() as
acpi_gic_init() but I keep that name to accommodate of_irq_init(),
any objections please let me know.
update from RFC version:
- Consolidate all the GIC init code into drivers/irqchip/irq-gic-acpi.c
Hanjun Guo (6):
irqchip / GIC: Add GIC version support in ACPI MADT
ACPI / irqchip: Add self-probe infrastructure to initialize IRQ
controller
irqchip / GIC / ACPI: Use IRQCHIP_ACPI_DECLARE to simplify GICv2 init
code
irqchip / gic: Add stacked irqdomain support for ACPI based GICv2 init
irqchip / GICv3: Add stacked irqdomain support for ACPI based init
irqchip / gicv3 / ACPI: Add GICR support via GICC structures
Tomasz Nowicki (2):
irqchip / GICv3: Refactor gic_of_init() for GICv3 driver
irqchip / GICv3: Add ACPI support for GICv3+ initialization
arch/arm64/Kconfig | 1 +
arch/arm64/include/asm/acpi.h | 1 -
arch/arm64/include/asm/irq.h | 13 --
arch/arm64/kernel/acpi.c | 25 --
drivers/acpi/gsi.c | 78 +++++--
drivers/irqchip/Kconfig | 3 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-gic-acpi.c | 171 ++++++++++++++
drivers/irqchip/irq-gic-v3.c | 427 ++++++++++++++++++++++++++++++-----
drivers/irqchip/irq-gic.c | 40 ++--
include/asm-generic/vmlinux.lds.h | 13 ++
include/linux/acpi.h | 21 ++
include/linux/acpi_irq.h | 4 +-
include/linux/irqchip.h | 13 ++
include/linux/irqchip/arm-gic-acpi.h | 10 +-
include/linux/mod_devicetable.h | 8 +
16 files changed, 695 insertions(+), 134 deletions(-)
create mode 100644 drivers/irqchip/irq-gic-acpi.c
--
1.9.1
IORT, IO remapping tables, which is a table to describe the connections
of PCI root complex, devices, ITS (msi controller) and SMMU, for example,
it presents the topology of which device under which SMMU and(or) ITS.
This patch set first do some cleanup for the ITS dirver, then init the ITS
with the information presented by MADT ITS entries, then follows the IORT spec,
implementing:
- PCI root complex using ITS as msi controller, mapping its domain (segemnt)
number with the MSI controller;
- init the SMMU and use the mapping of PCI and no-PCI device to SMMU to
connect them
- No-PCI devices using MSI (connect to ITS) is not covered by this patch
set.
please refer to the ARM documentation:
http://infocenter.arm.com/help/topic/com.arm.doc.den0049a/DEN0049A_IO_Remap…
This patch set is based on Tomasz Nowicki's work, but I rework some of
the patches significantly, more work is needed for this patch set
and I'm still not satisfy with the some of implementation, anyway, I
will continue working on that, and at the same time, sending them out
for review to see if there are some major problems.
you can get them form
git://git.linaro.org/leg/acpi/acpi.git devel
Comments and test are warmly welcomed.
Hanjun Guo (5):
irqchip / GICv3: remove gic root node in ITS
irqchip / GICv3 / ITS: mark its_init() as __init
irqchip/GICv3/ITS: refator ITS dt init code to prepare for ACPI
irqchip: gicv3: its: probe ITS in ACPI way
ARM64, ACPI, PCI, MSI: I/O Remapping Table (IORT) initial support.
Tomasz Nowicki (2):
arm, smmu: Use more generic structure for SMMU master list.
ARM64, ACPI, IORT: Bind SMMU driver via IORT table
drivers/acpi/Kconfig | 3 +
drivers/acpi/Makefile | 1 +
drivers/acpi/iort.c | 536 +++++++++++++++++++++++++++++++++++++++
drivers/acpi/pci_root.c | 2 +
drivers/iommu/arm-smmu.c | 290 ++++++++++++++++-----
drivers/irqchip/Kconfig | 1 +
drivers/irqchip/irq-gic-v3-its.c | 188 ++++++++++----
include/linux/iort.h | 63 +++++
8 files changed, 966 insertions(+), 118 deletions(-)
create mode 100644 drivers/acpi/iort.c
create mode 100644 include/linux/iort.h
--
1.9.1
Currently, the BAD_MADT_ENTRY macro is used to do a very simple sanity
check on the various subtables that are defined for the MADT. The check
compares the size of the subtable data structure as defined by ACPICA to
the length entry in the subtable. If they are not the same, the assumption
is that the subtable is incorrect.
Over time, the ACPI spec has allowed for MADT subtables where this can
never be true (the local SAPIC subtable). Or, more recently, the spec
has accumulated some minor flaws where there are three possible sizes for
a subtable, all of which are valid, but only for specific versions of the
spec (the GICC subtable). In both cases, BAD_MADT_ENTRY reports these
subtables as bad when they are not. In order to retain some sanity check
on the MADT subtables, we now have to special case these subtables. Of
necessity, these special cases have ended up in arch-dependent code (arm64)
or an arch has simply decided to forgo the check (ia64).
This patch set replaces the BAD_MADT_ENTRY macro with a function called
bad_madt_entry(). This function uses a data set of details about the
subtables to provide more sanity checking than before:
-- is the subtable legal for the version given in the FADT?
-- is the subtable legal for the revision of the MADT in use?
-- is the subtable of the proper length (including checking
on the one variable length subtable), given the FADT version
and the MADT revision?
Further, this patch set adds in the call to bad_madt_entry() from the
acpi_table_parse_madt() function, allowing it to be used consistently
by all architectures, for all subtables, and removing the need for each
of the subtable traversal callback functions to use BAD_MADT_ENTRY.
In theory, as the ACPI specification changes, we would only have to add
additional information to the data set describing the MADT subtables in
order to continue providing sanity checks, even when new subtables are
added.
These patches have been tested on an APM Mustang (arm64) and are known to
work there. They have NOT been tested anywhere else yet.
Al Stone (5):
ACPI: add in a bad_madt_entry() function to eventually replace the
macro
ACPI / ARM64: remove usage of BAD_MADT_ENTRY/BAD_MADT_GICC_ENTRY
ACPI / IA64: remove usage of BAD_MADT_ENTRY
ACPI / X86: remove usage of BAD_MADT_ENTRY
ACPI: remove definition of BAD_MADT_ENTRY macro
arch/arm64/include/asm/acpi.h | 8 --
arch/arm64/kernel/perf_event.c | 3 -
arch/arm64/kernel/smp.c | 2 -
arch/ia64/kernel/acpi.c | 20 ----
arch/x86/kernel/acpi/boot.c | 27 -----
drivers/acpi/tables.c | 241 +++++++++++++++++++++++++++++++++++++++++
drivers/irqchip/irq-gic-v2m.c | 2 -
drivers/irqchip/irq-gic.c | 6 -
include/linux/acpi.h | 4 -
9 files changed, 241 insertions(+), 72 deletions(-)
--
2.4.3
From: Fu Wei <fu.wei(a)linaro.org>
This patchset:
(1)Introduce Documentation/devicetree/bindings/watchdog/sbsa-gwdt.txt
for FDT info of SBSA Generic Watchdog, and give two examples of
adding SBSA Generic Watchdog device node into the dts files:
foundation-v8.dts and amd-seattle-soc.dtsi.
(2)Introduce "pretimeout" into the watchdog framework, and update
Documentation/watchdog/watchdog-kernel-api.txt to introduce:
(1)the new elements in the watchdog_device and watchdog_ops struct;
(2)the new API "watchdog_init_timeouts".
(3)Introduce ARM SBSA watchdog driver:
a.Use linux kernel watchdog framework;
b.Work with FDT on ARM64;
c.Use "pretimeout" in watchdog framework;
d.Support getting timeout and pretimeout from parameter and FDT
at the driver init stage.
e.In the first timeout, do panic to save system context;
f.In the second stage, user can still feed the dog without
cleaning WS0. By this feature, we can avoid the panic infinite
loops, while backing up a large system context in a server.
g.In the second stage, can trigger WS1 by setting pretimeout = 0
if necessary.
(4)Introduce ACPI GTDT parser: drivers/acpi/gtdt.c
Parse SBSA Generic Watchdog Structure in GTDT table of ACPI,
and create a platform device with that information.
This platform device can be used by This Watchdog driver.
drivers/clocksource/arm_arch_timer.c is simplified by this GTDT support.
This patchset has been tested with watchdog daemon
(ACPI/FDT, module/build-in) on the following platforms:
(1)ARM Foundation v8 model
Changelog:
v6: Improve the dtb example files: reduce the register frame size to 4K.
Improve pretimeout support:
(1) improve watchdog_init_timeouts function
(2) rename watchdog_check_min_max_timeouts back to the original name
(1) improve watchdog_timeout_invalid/watchdog_pretimeout_invalid
Add the new features in the sbsa_gwdt driver:
(1) In the second stage, user can feed the dog without cleaning WS0.
(2) In the second stage, user can trigger WS1 by setting pretimeout = 0.
(3) expand the max value of pretimeout, in case 10 second is not enough
for a kdump kernel reboot in panic.
v5: Improve pretimeout support:
(1)fix typo in documentation and comments.
(2)fix the timeout limits validation bug.
Simplify sbsa_gwdt driver:
(1)integrate all the registers access functions into caller.
v4: Refactor GTDT support code: remove it from arch/arm64/kernel/acpi.c,
put it into drivers/acpi/gtdt.c file.
Integrate the GTDT code of drivers/clocksource/arm_arch_timer.c into
drivers/acpi/gtdt.c.
Improve pretimeout support, fix "pretimeout == 0" problem.
Simplify sbsa_gwdt driver:
(1)timeout/pretimeout limits setup;
(2)keepalive function;
(3)delete "clk == 0" check;
(4)delete WS0 status bit check in interrupt routine;
(5)sbsa_gwdt_set_wcv function.
v3: Delete "export arch_timer_get_rate" patch.
Driver back to use arch_timer_get_cntfrq.
Improve watchdog_init_timeouts function and update relevant documentation.
Improve watchdog_timeout_invalid and watchdog_pretimeout_invalid.
Improve foundation-v8.dts: delete the unnecessary tag of device node.
Remove "ARM64 || COMPILE_TEST" from Kconfig.
Add comments in arch/arm64/kernel/acpi.c
Fix typoes and incorrect comments.
v2: Improve watchdog-kernel-api.txt documentation for pretimeout support.
Export "arch_timer_get_rate" in arm_arch_timer.c.
Add watchdog_init_timeouts API for pretimeout support in framework.
Improve suspend and resume foundation in driver
Improve timeout/pretimeout values init code in driver.
Delete unnecessary items of the sbsa_gwdt struct and #define.
Delete all unnecessary debug info in driver.
Fix 64bit division bug.
Use the arch_timer interface to get watchdog clock rate.
Add MODULE_DEVICE_TABLE for platform device id.
Fix typoes.
v1: The first version upstream patchset to linux mailing list.
Fu Wei (8):
Documentation: add sbsa-gwdt.txt documentation
ARM64: add SBSA Generic Watchdog device node in foundation-v8.dts
ARM64: add SBSA Generic Watchdog device node in amd-seattle-soc.dtsi
Watchdog: introdouce "pretimeout" into framework
Watchdog: introduce ARM SBSA watchdog driver
ACPI: add GTDT table parse driver into ACPI driver
Watchdog: enable ACPI GTDT support for ARM SBSA watchdog driver
clocksource: simplify ACPI code in arm_arch_timer.c
.../devicetree/bindings/watchdog/sbsa-gwdt.txt | 36 ++
Documentation/watchdog/watchdog-kernel-api.txt | 47 ++-
arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi | 11 +
arch/arm64/boot/dts/arm/foundation-v8.dts | 10 +
arch/arm64/kernel/time.c | 4 +-
drivers/acpi/Kconfig | 9 +
drivers/acpi/Makefile | 1 +
drivers/acpi/gtdt.c | 180 ++++++++
drivers/clocksource/Kconfig | 1 +
drivers/clocksource/arm_arch_timer.c | 60 +--
drivers/watchdog/Kconfig | 15 +
drivers/watchdog/Makefile | 1 +
drivers/watchdog/sbsa_gwdt.c | 455 +++++++++++++++++++++
drivers/watchdog/watchdog_core.c | 98 +++--
drivers/watchdog/watchdog_dev.c | 53 +++
include/clocksource/arm_arch_timer.h | 8 +
include/linux/acpi.h | 5 +
include/linux/clocksource.h | 4 +-
include/linux/watchdog.h | 39 +-
19 files changed, 947 insertions(+), 90 deletions(-)
create mode 100644 Documentation/devicetree/bindings/watchdog/sbsa-gwdt.txt
create mode 100644 drivers/acpi/gtdt.c
create mode 100644 drivers/watchdog/sbsa_gwdt.c
--
1.9.1
Hi Al,
Please take these as bug reports to Redhat maintained patches. I am unsure of
the correct fixes in these cases.
I have pushed these to the mustang topic branch and will push the SPCR one
to the other topics as well.
Thanks
Graeme
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This patch set introduce self-probe infrastructure to init IRQ
controllers and stacked irqdomain support for ACPI based GICv2/3
init.
The self-probe infrastructure for ACPI GIC init is similar as
IRQCHIP_DECLARE() and based on the GIC version support in ACPI
MADT table. we match the GIC version and GIC driver and load
it.
We introduce acpi_irq_domain for GICv2/3 core domain to support
stacked irqdomain, and pass the gsi (global system interrupt) as
the agument (void *arg) for gic_irq_domain_alloc(), then we can
alloc virqs via acpi_register_gsi() with stacked irqdomain.
The stacked irq domain will be:
acpi_irq_domain == gicv2 or gicv3 core domain
^
| (parent)
|
ITS domain or GIv2m domain
^
|
|
MSI chip irq domain
Since there is one GICD supported for now, so there will be only
one irqdomain created when GICv2/3 initialized, for all the wired
hardware irqs for PPI, SGI and SPI, they will have unique hardware
irq number (GSI), so we can match the device to the acpi_irq_domain
with unique GSI and it will work. If there will be multi GICD in the
future, this will still works to follow the solution for x86 of ACPI
(mutil IOAPICs).
Note: patch 1~2 already merged in ACPICA core, I just send them out
for helping of better understanding later 7 patches.
Any comments are warmly welcomed.
update from RFC version:
- Consolidate all the GIC init code into drivers/irqchip/irq-gic-acpi.c
v1->v2:
- Remove the gicv2/v3 related driver code in drivers/irqchip/irq-gic-acpi.c
which I was trying to consolidate them in one file, then arm-gic.h and
arm-gic-v3.h will be used separately within parent driver only
- Drop the gsi_mutex patch
- Use the GIC version to match the GIC driver, then no need to test
for the version in each driver
- Move acpi_irq_init() to drivers/irqchip/irq-gic-acpi.c instead of
in drivers/acpi/irq.c. maybe we need to rename acpi_irq_init() as
acpi_gic_init() but I keep that name to accommodate of_irq_init(),
any objections please let me know.
Bob Moore (1):
ACPICA: ACPI 6.0: Add changes for MADT table.
Hanjun Guo (6):
ACPICA: ACPI 6.0: Add values for MADT GIC version field.
irqchip / GIC: Add GIC version support in ACPI MADT
ACPI / irqchip: Add self-probe infrastructure to initialize IRQ
controller
irqchip / GIC / ACPI: Use IRQCHIP_ACPI_DECLARE to simplify GICv2 init
code
irqchip / gic: Add stacked irqdomain support for ACPI based GICv2 init
irqchip / GICv3: Add stacked irqdomain support for ACPI based init
Tomasz Nowicki (2):
irqchip / GICv3: Refactor gic_of_init() for GICv3 driver
irqchip / GICv3: Add ACPI support for GICv3+ initialization
arch/arm64/Kconfig | 1 +
arch/arm64/include/asm/acpi.h | 1 -
arch/arm64/include/asm/irq.h | 13 --
arch/arm64/kernel/acpi.c | 25 ----
drivers/acpi/gsi.c | 28 ++--
drivers/irqchip/Kconfig | 3 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-gic-acpi.c | 141 +++++++++++++++++++
drivers/irqchip/irq-gic-v3.c | 264 ++++++++++++++++++++++++++++-------
drivers/irqchip/irq-gic.c | 35 ++---
drivers/irqchip/irqchip.h | 12 ++
include/acpi/actbl1.h | 33 ++++-
include/asm-generic/vmlinux.lds.h | 13 ++
include/linux/acpi.h | 16 +++
include/linux/acpi_irq.h | 4 +-
include/linux/irqchip/arm-gic-acpi.h | 10 +-
include/linux/mod_devicetable.h | 8 ++
17 files changed, 473 insertions(+), 135 deletions(-)
create mode 100644 drivers/irqchip/irq-gic-acpi.c
--
1.9.1
CPPC:
====
CPPC (Collaborative Processor Performance Control) is a new way to control CPU
performance using an abstract continous scale as against a discretized P-state scale
which is tied to CPU frequency only. It is defined in the ACPI 5.0+ spec. In brief,
the basic operation involves:
- OS makes a CPU performance request. (Can provide min and max tolerable bounds)
- Platform (such as BMC) is free to optimize request within requested bounds depending
on power/thermal budgets etc.
- Platform conveys its decision back to OS
The communication between OS and platform occurs through another medium called (PCC)
Platform communication Channel. This is a generic mailbox like mechanism which includes
doorbell semantics to indicate register updates. See drivers/mailbox/pcc.c
This patchset introduces a CPPC based CPUFreq driver that works with existing governors
such as ondemand. The CPPC table parsing and the CPPC communication semantics are
abstracted into separate files to allow future CPPC based drivers to implement their
own governors if required.
Initial patchsets included an adaptation of the PID governor from intel_pstate.c. However
recent experiments led to extensive modifications of the algorithm to calculate CPU
busyness. Until it is verified that these changes are worthwhile, the existing governors
should provide for a good enough starting point for ARM64 servers.
Finer details about the PCC and CPPC spec are available in the latest ACPI 5.1
specification.[2]
Testing:
=======
This was tested on an SBSA compatible ARMv8 server with CPPCv2
firmware running on a remote processor. I verified that each CPUs
performance limits were detected and that new performance requests
were made by the on-demand governor proportional to the load on each
CPU. I also verified that using the acpi_processor driver correctly
maps the physical CPU ids to logical CPU ids, which helps in picking
up the proper _CPC details from a processor object, in the case where
CPU physical ids may not be contiguous.
Changes since V5:
- Checkpatch cleanups.
- Change pss_init to pss_perf_init. Rec by Srinivas Pandruvada.
- Explicit comment explaining why postcore_initcall to pcc mailbox.
- Fold acpi_processor_syscore_init/exit into CONFIG_ACPI_CST.
- Added patch with dummy functions used by ACPI_HOTPLUG_CPU.
Changes since V4:
- Misc cleanups. Addressed feedback from Rafael.
- Made acpi_processor.c independent of C-states, P-states and others.
- Per CPU scanning for _CPC is now made from acpi_processor.c
- Added new Kconfig options for legacy C states and P states to enable future
support for newer alternatives as defined in the ACPI spec 6.0.
Changes since V3:
- Split CPPC backend methods into separate files.
- Add frontend driver which plugs into existing CPUfreq governors.
- Simplify PCC driver by moving communication space mapping and read/write
into client drivers.
Changes since V2:
- Select driver if !X86, since intel_pstate will use HWP extensions instead.
- Added more comments.
- Added Freq domain awareness and PSD parsing.
Changes since V1:
- Create a new driver based on Dirks suggestion.
- Fold in CPPC backend hooks into main driver.
Changes since V0: [1]
- Split intel_pstate.c into a generic PID governor and platform specific backend.
- Add CPPC accessors as PID backend.
[1] - http://lwn.net/Articles/608715/
[2] - http://www.uefi.org/sites/default/files/resources/ACPI_5_1release.pdf
[3] - https://patches.linaro.org/40705/
Ashwin Chaugule (7):
PCC: Initialize PCC Mailbox earlier at boot
ACPI: Make ACPI processor driver more extensible
ACPI: Introduce CPU performance controls using CPPC
CPPC: Add a CPUFreq driver for use with CPPC
CPPC: Probe for CPPC tables for each ACPI Processor object
PCC: Enable PCC only when needed
ACPI: Add weak routines for ACPI CPU Hotplug
drivers/acpi/Kconfig | 48 ++-
drivers/acpi/Makefile | 8 +-
drivers/acpi/acpi_processor.c | 18 +
drivers/acpi/cppc_acpi.c | 812 ++++++++++++++++++++++++++++++++++++++++
drivers/acpi/processor_driver.c | 90 +++--
drivers/cpufreq/Kconfig | 2 +-
drivers/cpufreq/Kconfig.arm | 16 +
drivers/cpufreq/Kconfig.x86 | 2 +
drivers/cpufreq/Makefile | 2 +
drivers/cpufreq/cppc_cpufreq.c | 197 ++++++++++
drivers/mailbox/Kconfig | 2 +-
drivers/mailbox/pcc.c | 8 +-
include/acpi/cppc_acpi.h | 137 +++++++
include/acpi/processor.h | 129 +++++--
14 files changed, 1397 insertions(+), 74 deletions(-)
create mode 100644 drivers/acpi/cppc_acpi.c
create mode 100644 drivers/cpufreq/cppc_cpufreq.c
create mode 100644 include/acpi/cppc_acpi.h
--
1.9.1
Howdy.
I've updated the acpi-topic-mustang branch so that it now works properly
again (mostly because I needed it to run some experiments and tests).
It's basically our acpi.git master plus ports of patches scavenged mostly
from the Fedora kernel, some of which may or may not end up in mainline in
their present form. Use these patches wisely. They should not be considered
final since they have not been accepted upstream.
Pretty much everything on the box works.
--
ciao,
al
-----------------------------------
Al Stone
Software Engineer
Linaro Enterprise Group
al.stone(a)linaro.org
-----------------------------------
In the ACPI 5.1 version of the spec, the struct for the GICC subtable
(struct acpi_madt_generic_interrupt) of the MADT is 76 bytes long; in
ACPI 6.0, the struct is 80 bytes long. But, there is only one definition
in ACPICA for this struct -- and that is the 6.0 version. Hence, when
BAD_MADT_ENTRY() compares the struct size to the length in the GICC
subtable, it fails if 5.1 structs are in use, and there are systems in
the wild that have them.
Note that this was found in linux-next and these patches apply against
that tree and the arm64 kernel tree; 4.1 does not appear to have this
problem since it still has the 5.1 struct definition.
Though there is precedent in ia64 code for ignoring the changes in size,
this patch set instead verifies correctness. The first patch adds the
BAD_MADT_GICC_ENTRY() macro to check the GICC subtable only, accounting
for the difference in specification versions that are possible. The
second patch replaces BAD_MADT_ENTRY usage with the BAD_MADT_GICC_ENTRY
macro in arm64 code, which is currently the only architecture affected.
The BAD_MADT_ENTRY() will continue to work as is for all other MADT
subtables.
I have tested these patches on an APM Mustang with version 1.15 firmware,
where the problem was found, and they fix the problem -- i.e., the system
will boot with either Linux 4.1 or linux-next kernels using the same ACPI
5.1 compatible firmware.
Changes for v4:
-- Reword the cover letter to reflect smaller patch set
-- Simplify BAD_MADT_GICC_ENTRY to the minimum needed; this removed
the need for the first patch containing version number macros (Rafael)
-- Simplify determining the GICC subtable length (Catalin)
Changes for v3:
-- Modified the macros for using spec version numbers in order
to make them clearer (Rafael, Hanjun)
-- Moved the definition of the BAD_MADT_GICC_ENTRY macro to an
arm64-specific header file since only this architecture uses
the GICC subtable (Rafael)
-- Added Reviewed-by (Hanjun) and Acked-by (Will) tags to 3/3, the
only unchanged patch; other tags could be applied but the patches
have changed.
-- Added Fixes: tag to patches
Changes for v2:
-- Replace magic constants with proper defines (Lorenzo)
-- Minor syntax clean-up noted by checkpatch
-- Send out CCs properly this time
-- Minor clean-up of the paragraphs in this cover letter
Al Stone (2):
ACPI / ARM64: add BAD_MADT_GICC_ENTRY() macro
ACPI / ARM64 : use the new BAD_MADT_GICC_ENTRY macro
arch/arm64/include/asm/acpi.h | 8 ++++++++
arch/arm64/kernel/smp.c | 2 +-
drivers/irqchip/irq-gic.c | 2 +-
3 files changed, 10 insertions(+), 2 deletions(-)
--
2.4.3
As we use the acpi_irq_domain as the global pointer to the acpi core
irq domain, which lead to multi places referring it and the way is not
scalable, so introduce a struct gsi_cfg_data to abstract the gsi data
for the irqchips then match the irq domain with the gsi.
For a ACPI based irqchip for example a GICD, it defines System Vector
Base in the GICD entry, which means the global system interrupt number
where this GIC Distributor’s interrupt inputs start, then we can get
the irq number supported by reading the register for this GICD, so we
can explictly get the gsi's associated irqdomain if the gsi is within
the range of gsi supported by this GICD.
For ACPI device in DSDT, it using another mapping of device and hwirq
number than DT, in DT, we using the interrupt parent property to get
the device node of irqchip, that's why we need the matching function
that match the device node with the one associated with the irqdomain.
For ACPI, we only can get the gsi which the device is using, no interrupt
parent will be used, that because gsi is a flat hwirq number which is
unique in the system, then we can get its associated irq domain as I said
above, which can be without the token pointer matching the interrupt
controller.
the code is arch independent, it also can be expanted for x86 for multi
ioapics.
Signed-off-by: Hanjun Guo <hanjun.guo(a)linaro.org>
---
drivers/acpi/gsi.c | 51 ++++++++++++++++++++++++++++++++++++++------
drivers/irqchip/irq-gic-v3.c | 4 +++-
drivers/irqchip/irq-gic.c | 7 +++++-
include/linux/acpi.h | 10 ++++++++-
4 files changed, 62 insertions(+), 10 deletions(-)
diff --git a/drivers/acpi/gsi.c b/drivers/acpi/gsi.c
index 02c8408..7867ec2 100644
--- a/drivers/acpi/gsi.c
+++ b/drivers/acpi/gsi.c
@@ -15,11 +15,44 @@
enum acpi_irq_model_id acpi_irq_model;
-static struct irq_domain *acpi_irq_domain __read_mostly;
+static LIST_HEAD(gsi_cfg_data_list);
+static DEFINE_MUTEX(gsi_mutex);
-void set_acpi_irq_domain(struct irq_domain *domain)
+int gsi_cfg_data_add(struct irq_domain *domain, u32 gsi_base, u32 gsi_end)
{
- acpi_irq_domain = domain;
+ struct gsi_cfg_data *data;
+
+ data = kzalloc(sizeof(*data), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+
+ data->domain = domain;
+ data->gsi_base = gsi_base;
+ data->gsi_base = gsi_base;
+
+ mutex_lock(&gsi_mutex);
+ list_add(&data->list, &gsi_cfg_data_list);
+ mutex_unlock(&gsi_mutex);
+
+ return 0;
+}
+
+/* Find irqdomain with GSI (hwirq number) */
+static struct irq_domain *acpi_find_irqdomain(u32 gsi)
+{
+ struct gsi_cfg_data *data;
+ struct irq_domain *domain = NULL;
+
+ mutex_lock(&gsi_mutex);
+ list_for_each_entry(data, &gsi_cfg_data_list, list) {
+ if (gsi >= data->gsi_base && gsi <= data->gsi_end) {
+ domain = data->domain;
+ break;
+ }
+ }
+ mutex_unlock(&gsi_mutex);
+
+ return domain;
}
static unsigned int acpi_gsi_get_irq_type(int trigger, int polarity)
@@ -53,7 +86,9 @@ static unsigned int acpi_gsi_get_irq_type(int trigger, int polarity)
*/
int acpi_gsi_to_irq(u32 gsi, unsigned int *irq)
{
- *irq = irq_find_mapping(acpi_irq_domain, gsi);
+ struct irq_domain *domain = acpi_find_irqdomain(gsi);
+
+ *irq = irq_find_mapping(domain, gsi);
/*
* *irq == 0 means no mapping, that should
* be reported as a failure
@@ -77,12 +112,13 @@ int acpi_register_gsi(struct device *dev, u32 gsi, int trigger,
{
int irq;
unsigned int irq_type = acpi_gsi_get_irq_type(trigger, polarity);
+ struct irq_domain *domain = acpi_find_irqdomain(gsi);
- irq = irq_find_mapping(acpi_irq_domain, gsi);
+ irq = irq_find_mapping(domain, gsi);
if (irq > 0)
return irq;
- irq = irq_domain_alloc_irqs(acpi_irq_domain, 1, dev_to_node(dev),
+ irq = irq_domain_alloc_irqs(domain, 1, dev_to_node(dev),
&gsi);
if (irq <= 0)
return -EINVAL;
@@ -101,7 +137,8 @@ EXPORT_SYMBOL_GPL(acpi_register_gsi);
*/
void acpi_unregister_gsi(u32 gsi)
{
- int irq = irq_find_mapping(acpi_irq_domain, gsi);
+ struct irq_domain *domain = acpi_find_irqdomain(gsi);
+ int irq = irq_find_mapping(domain, gsi);
irq_dispose_mapping(irq);
}
diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
index a11c020..5c53af6 100644
--- a/drivers/irqchip/irq-gic-v3.c
+++ b/drivers/irqchip/irq-gic-v3.c
@@ -947,6 +947,7 @@ static LIST_HEAD(redist_list);
static struct redist_region *redist_regs __initdata;
static u32 nr_redist_regions __initdata;
static phys_addr_t dist_phy_base __initdata;
+u32 gsi_base __initdata;
static int __init
gic_acpi_register_redist(u64 phys_base, u64 size)
@@ -1014,6 +1015,7 @@ gic_acpi_parse_madt_distributor(struct acpi_subtable_header *header,
if (BAD_MADT_ENTRY(dist, end))
return -EINVAL;
+ gsi_base = dist->global_irq_base;
dist_phy_base = dist->base_address;
return 0;
}
@@ -1168,7 +1170,7 @@ init_base:
if (err)
goto out_release_redist;
- set_acpi_irq_domain(gic_data.domain);
+ gsi_cfg_data_add(gic_data.domain, gsi_base, gsi_base + gic_data.irq_nr);
return 0;
out_release_redist:
diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index 7f943ef..62e0640 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -1051,6 +1051,7 @@ IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init);
#ifdef CONFIG_ACPI
static phys_addr_t dist_phy_base, cpu_phy_base __initdata;
+u32 gsi_base __initdata;
static int __init
gic_acpi_parse_madt_cpu(struct acpi_subtable_header *header,
@@ -1089,6 +1090,7 @@ gic_acpi_parse_madt_distributor(struct acpi_subtable_header *header,
if (BAD_MADT_ENTRY(dist, end))
return -EINVAL;
+ gsi_base = dist->global_irq_base;
dist_phy_base = dist->base_address;
return 0;
}
@@ -1139,7 +1141,10 @@ gic_v2_acpi_init(struct acpi_table_header *table)
}
gic_init_bases(0, -1, dist_base, cpu_base, 0, NULL);
- set_acpi_irq_domain(gic_data[0].domain);
+
+ /* since we have only one GICD, we can safely use gic_data[0] here */
+ gsi_cfg_data_add(gic_data[0].domain, gsi_base,
+ gsi_base + gic_data[0].gic_irqs);
acpi_irq_model = ACPI_IRQ_MODEL_GIC;
return 0;
diff --git a/include/linux/acpi.h b/include/linux/acpi.h
index 6de4b0e..093d60e 100644
--- a/include/linux/acpi.h
+++ b/include/linux/acpi.h
@@ -223,7 +223,15 @@ void acpi_unregister_gsi (u32 gsi);
#ifdef CONFIG_ACPI_GENERIC_GSI
struct irq_domain;
-void set_acpi_irq_domain(struct irq_domain *domain);
+
+struct gsi_cfg_data {
+ struct list_head list;
+ u32 gsi_base;
+ u32 gsi_end;
+ struct irq_domain *domain;
+};
+
+int gsi_cfg_data_add(struct irq_domain *domain, u32 gsi_base, u32 gsi_end);
#endif
struct pci_dev;
--
1.9.1
In the ACPI 5.1 version of the spec, the struct for the GICC subtable
(struct acpi_madt_generic_interrupt) of the MADT is 76 bytes long; in
ACPI 6.0, the struct is 80 bytes long. But, there is only one definition
in ACPICA for this struct -- and that is the 6.0 version. Hence, when
BAD_MADT_ENTRY() compares the struct size to the length in the GICC
subtable, it fails if 5.1 structs are in use, and there are systems in
the wild that have them.
Note that this was found in linux-next and these patches apply against
that tree and the arm64 kernel tree; 4.1-rc8 does not appear to have this
problem since it still has the 5.1 struct definition.
Even though there is precendent in ia64 code for ignoring the changes in
size, this patch set instead tries to verify correctness. The first patch
in the set adds macros for easily using the ACPI spec version. The second
patch adds the BAD_MADT_GICC_ENTRY() macro that uses the version macros to
check the GICC subtable only, accounting for the difference in specification
versions that are possible. The final patch replaces BAD_MADT_ENTRY usage
with the BAD_MADT_GICC_ENTRY macro in arm64 code, which is currently the
only architecture affected. The BAD_MADT_ENTRY() will continue to work as
is for all other MADT subtables.
I have tested these patches on an APM Mustang with version 1.15 firmware,
where the problem was found, and they fix the problem.
Changes for v3:
-- Modified the macros for using spec version numbers in order
to make them clearer (Rafael, Hanjun)
-- Moved the definition of the BAD_MADT_GICC_ENTRY macro to an
arm64-specific header file since only this architecture uses
the GICC subtable (Rafael)
-- Added Reviewed-by (Hanjun) and Acked-by (Will) tags to 3/3, the
only unchanged patch; other tags could be applied but the patches
have changed.
-- Added Fixes: tag to patches
Changes for v2:
-- Replace magic constants with proper defines (Lorenzo)
-- Minor syntax clean-up noted by checkpatch
-- Send out CCs properly this time
-- Minor clean-up of the paragraphs in this cover letter
Al Stone (3):
ACPI : introduce macros for using the ACPI specification version
ACPI / ARM64: add BAD_MADT_GICC_ENTRY() macro
ACPI / ARM64 : use the new BAD_MADT_GICC_ENTRY macro
arch/arm64/include/asm/acpi.h | 11 +++++++++++
arch/arm64/kernel/smp.c | 2 +-
drivers/irqchip/irq-gic.c | 2 +-
include/linux/acpi.h | 10 ++++++++++
4 files changed, 23 insertions(+), 2 deletions(-)
--
2.4.3
Hi Guys,
I guess its time to put this to bed now that Roys patch has made it
into acpica-tools and FWTS has been fixed to work without /dev/mem.
I produced the patch to expose these three tables from the kernel.
BUT, is there actually a user for this? My gut feeling is no and they
really contain little of interest anyway.
Does anyone actually have a use for the patch that makes it worth
sending upstream?
Graeme
In the ACPI 5.1 version of the spec, the struct for the GICC subtable
(struct acpi_madt_generic_interrupt) of the MADT is 76 bytes long; in
ACPI 6.0, the struct is 80 bytes long. But, there is only one definition
in ACPICA for this struct -- and that is the 6.0 version. Hence, when
BAD_MADT_ENTRY() compares the struct size to the length in the GICC
subtable, it fails if 5.1 structs are in use, and there are systems in
the wild that have them.
Note that this was found in linux-next and these patches apply against
that tree and the arm64 kernel tree; 4.1-rc8 does not appear to have this
problem since it still has the 5.1 struct definition.
Even though there is precendent in ia64 code for ignoring the changes in
size, this patch set instead tries to verify correctness. The first patch
in the set adds macros for easily using the ACPI spec version. The second
patch adds the BAD_MADT_GICC_ENTRY() macro that uses the version macros to
check the GICC subtable only, accounting for the difference in specification
versions that are possible. The final patch replaces BAD_MADT_ENTRY usage
with the BAD_MADT_GICC_ENTRY macro in arm64 code, which is currently the
only architecture affected. The BAD_MADT_ENTRY() will continue to work as
is for all other MADT subtables.
I have tested these patches on an APM Mustang with version 1.15 firmware,
where the problem was found, and they fix the problem.
Changes for v2:
-- Replace magic constants with proper defines (Lorenzo)
-- Minor syntax clean-up noted by checkpatch
-- Send out CCs properly this time
-- Minor clean-up of the paragraphs in this cover letter
Al Stone (3):
ACPI : introduce macros for using the ACPI specification version
ACPI: add BAD_MADT_GICC_ENTRY() macro
ACPI / ARM64 : use the new BAD_MADT_GICC_ENTRY macro
arch/arm64/kernel/smp.c | 2 +-
drivers/irqchip/irq-gic.c | 2 +-
include/linux/acpi.h | 15 +++++++++++++++
3 files changed, 17 insertions(+), 2 deletions(-)
--
2.4.0
Películas y series 2015 estrenos Junio y Julio estan en xtop
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EZEL
On 6/24/2015 12:14 PM, Luck, Tony wrote:
>> Another option would be to have 2 structs, the first one
>> "struct cper_sec_mem_err" holds the structure as defined by UEFI
>> 2.1, the 2nd one "struct cper_sec_mem_err_24_ext" holds the 4
>> elements added in UEFI 2.3.1.
>
> Reading some more of the UEFI 2.5 spec ... I see we are in for a world of pain
> here.
>
> 2.5 adds some small tweaks to the memory structure (adding a couple of extra
> bits to the "row" entry that can be grabbed from the formerly reserved byte
> at offset 73).
I think this can be dealt with easily as long as all platforms observe
the rule that if a bit is reserved, the bit should be set a '0' instead
of being set randomly. Is this a fair assumption on all platforms?
> But then there is a whole new GUID for a "Memory Error Section 2"
> which has doubled the width of the device, row, column, rank, and bit_pos fields
> together with adding two new fields for chip_id and status. This will be painful
> because we hardwired the old sizes into extlog_mem_event in <ras/ras_event.h>
The old size is encoded in "stuct cper_mem_err_compact", other members
of the trace data are the same between "Memory Error Section" and
"Memory Error Section 2". One option we have without having to disturb
user space handler of memory error trace data would be to change
"struct cper_mem_err_compact" so the affected elements are of
__u32 instead of __u16. Drawback of this option is that the trace
buffer will be unnecessarily bigger if a platform generates
"Memory Error Section" data instead of "Memory Error Section 2" data.
Such drawback is not a big issue given that uncorrected memory error
happens infrequently and corrected memory error should be grouped
by platform.
--
Jonathan (Zhixiong) Zhang
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
From: Fu Wei <fu.wei(a)linaro.org>
This patchset:
(1)Introduce Documentation/devicetree/bindings/watchdog/sbsa-gwdt.txt
for FDT info of SBSA Generic Watchdog, and give two examples of
adding SBSA Generic Watchdog device node into the dts files:
foundation-v8.dts and amd-seattle-soc.dtsi.
(2)Introduce ACPI GTDT parser: drivers/acpi/gtdt.c
Parse SBSA Generic Watchdog Structure in GTDT table of ACPI,
and create a platform device with that information.
This platform device can be used by This Watchdog driver.
drivers/clocksource/arm_arch_timer.c is simplified by this GTDT support.
(3)Introduce ARM SBSA watchdog driver:
a.Use linux kernel watchdog framework;
b.Work with FDT on ARM64;
c.In first timeout, do panic to save system context;
d.Support getting timeout from parameter and FDT at the driver init stage.
This patchset has been tested with watchdog daemon
(ACPI/FDT, module/build-in) on the following platforms:
(1)ARM Foundation v8 model
Changelog:
non_pretimeout: Delete all pretimeout code
The time from enabling watchdog to WS0 is the same with
the time from WS0 to WS1, they are both timeout value.
v5: Improve pretimeout support:
(1)fix typo in documentation and comments.
(2)fix the timeout limits validation bug.
Simplify sbsa_gwdt driver:
(1)integrate all the registers access functions into caller.
v4: Refactor GTDT support code: remove it from arch/arm64/kernel/acpi.c,
put it into drivers/acpi/gtdt.c file.
Integrate the GTDT code of drivers/clocksource/arm_arch_timer.c into
drivers/acpi/gtdt.c.
Improve pretimeout support, fix "pretimeout == 0" problem.
Simplify sbsa_gwdt driver:
(1)timeout/pretimeout limits setup;
(2)keepalive function;
(3)delete "clk == 0" check;
(4)delete WS0 status bit check in interrupt routine;
(5)sbsa_gwdt_set_wcv function.
v3: Delete "export arch_timer_get_rate" patch.
Driver back to use arch_timer_get_cntfrq.
Improve watchdog_init_timeouts function and update relevant documentation.
Improve watchdog_timeout_invalid and watchdog_pretimeout_invalid.
Improve foundation-v8.dts: delete the unnecessary tag of device node.
Remove "ARM64 || COMPILE_TEST" from Kconfig.
Add comments in arch/arm64/kernel/acpi.c
Fix typoes and incorrect comments.
v2: Improve watchdog-kernel-api.txt documentation for pretimeout support.
Export "arch_timer_get_rate" in arm_arch_timer.c.
Add watchdog_init_timeouts API for pretimeout support in framework.
Improve suspend and resume foundation in driver
Improve timeout/pretimeout values init code in driver.
Delete unnecessary items of the sbsa_gwdt struct and #define.
Delete all unnecessary debug info in driver.
Fix 64bit division bug.
Use the arch_timer interface to get watchdog clock rate.
Add MODULE_DEVICE_TABLE for platform device id.
Fix typoes.
v1: The first version upstream patchset to linux mailing list.
Fu Wei (7):
Documentation: add sbsa-gwdt.txt documentation
ARM64: add SBSA Generic Watchdog device node in foundation-v8.dts
ARM64: add SBSA Generic Watchdog device node in amd-seattle-soc.dtsi
Watchdog: introduce ARM SBSA watchdog driver
ACPI: add GTDT table parse driver into ACPI driver
Watchdog: enable ACPI GTDT support for ARM SBSA watchdog driver
clocksource: simplify ACPI code in arm_arch_timer.c
.../devicetree/bindings/watchdog/sbsa-gwdt.txt | 35 ++
arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi | 11 +
arch/arm64/boot/dts/arm/foundation-v8.dts | 10 +
arch/arm64/kernel/time.c | 4 +-
drivers/acpi/Kconfig | 9 +
drivers/acpi/Makefile | 1 +
drivers/acpi/gtdt.c | 180 ++++++++++
drivers/clocksource/Kconfig | 1 +
drivers/clocksource/arm_arch_timer.c | 60 +---
drivers/watchdog/Kconfig | 12 +
drivers/watchdog/Makefile | 1 +
drivers/watchdog/sbsa_gwdt.c | 383 +++++++++++++++++++++
include/clocksource/arm_arch_timer.h | 8 +
include/linux/acpi.h | 5 +
include/linux/clocksource.h | 4 +-
15 files changed, 671 insertions(+), 53 deletions(-)
create mode 100644 Documentation/devicetree/bindings/watchdog/sbsa-gwdt.txt
create mode 100644 drivers/acpi/gtdt.c
create mode 100644 drivers/watchdog/sbsa_gwdt.c
--
1.9.1
This patch set introduce self-probe infrastructure to init IRQ
controllers and stacked irqdomain support for ACPI based GICv2/3
init.
The self-probe infrastructure for ACPI GIC init is similar as
IRQCHIP_DECLARE() and based on the GIC version support in ACPI
MADT table.
We introduce acpi_irq_domain for GICv2/3 core domain to support
stacked irqdomain, and pass the gsi (global system interrupt) as
the agument (void *arg) for gic_irq_domain_alloc(), then we can
alloc virqs via acpi_register_gsi() with stacked irqdomain.
In order to make ACPI related GIC init code slef-contained, I
consolidated all the GIC init code into drivers/irqchip/irq-gic-acpi.c.
update from RFC version:
- Consolidate all the GIC init code into drivers/irqchip/irq-gic-acpi.c
Hanjun Guo (8):
irqchip / GIC: Add GIC version support in ACPI MADT
irqchip / GIC / ACPI: Use IRQCHIP_ACPI_DECLARE to simplify GICv2 init
code
irqchip / gic: Add stacked irqdomain support for ACPI based GICv2 init
ACPI / gsi: Add gsi_mutex to synchronize
acpi_register_gsi()/acpi_unregister_gsi()
irqchip / GICv3: Add ACPI support for GICv3+ initialization
irqchip / GICv3: Add stacked irqdomain support for ACPI based init
irqchip / GICv2 / ACPI: Consolidate GICv2 ACPI related init code
irqchip / GICv3 / ACPI: Consolidate GICv3 ACPI related init code
Tomasz Nowicki (3):
ACPICA: Introduce GIC version for arm based system
ACPI / irqchip: Add self-probe infrastructure to initialize IRQ
controller
irqchip / GICv3: Refactor gic_of_init() for GICv3 driver
arch/arm64/Kconfig | 1 +
arch/arm64/include/asm/irq.h | 13 --
arch/arm64/kernel/acpi.c | 25 ---
drivers/acpi/Makefile | 1 +
drivers/acpi/gsi.c | 41 +++--
drivers/acpi/irq.c | 40 +++++
drivers/irqchip/Kconfig | 3 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-gic-acpi.c | 318 +++++++++++++++++++++++++++++++++++
drivers/irqchip/irq-gic-v3.c | 149 +++++++++-------
drivers/irqchip/irq-gic.c | 129 ++------------
drivers/irqchip/irqchip.h | 12 ++
include/acpi/actbl1.h | 17 +-
include/asm-generic/vmlinux.lds.h | 13 ++
include/linux/acpi.h | 14 ++
include/linux/acpi_irq.h | 4 +-
include/linux/irqchip/arm-gic-acpi.h | 13 +-
include/linux/irqchip/arm-gic-v3.h | 10 ++
include/linux/mod_devicetable.h | 7 +
19 files changed, 577 insertions(+), 234 deletions(-)
create mode 100644 drivers/acpi/irq.c
create mode 100644 drivers/irqchip/irq-gic-acpi.c
--
1.9.1