Linaro-acpi

linaro-acpi@lists.linaro.org

820 discussions

by Tomasz Nowicki

MCFG ACPI table and PCI ECAM standard have no arch dependencies so it can be used across all architectures. Currently MMCONFIG related code resides in arch/x86 directories. This patch set is going to isolate non-architecture specific code and make it accessible for all architectures. v4 -> v5 changes: - improvements for Makefile logic - provide arch-specific checks for MCFG entry - fix MCFG injection logic (support absence of _CBA() method) v3 -> v4 changes: - bug fixes after kbuild test robot report - add asm/io.h header for ecam.c - rename mmcfg -> ecam for drivers/xen/pci.c and arch/x86/pci/numachip.c - rework Kconfig logic v2 -> v3 changes: - rebase patch set v2 to v4.0-rc1 v1 -> v2 changes: - use generic readb/readw etc. accessors instead of AMD Fam10h workaround - separate ACPI and ECAM code - improve ECAM code naming Tomasz Nowicki (9): x86, pci: Clean up comment about buggy MMIO config space access for AMD Fam10h CPUs. x86, pci: Abstract PCI config accessors and use AMD Fam10h workaround exclusively. x86, pci: Reorder logic of pci_mmconfig_insert() function x86, pci, acpi: Move arch-agnostic MMCONFIG (aka ECAM) and ACPI code out of arch/x86/ directory pci, acpi, mcfg: Provide generic implementation of MCFG code initialization. x86, pci: mmconfig_{32,64}.c code refactoring - remove code duplication. x86, pci, ecam: mmconfig_64.c becomes default implementation for ECAM driver. pci, acpi, mcfg: Share ACPI PCI config space accessors. pci, ecam: Improve naming for ecam.c content and areas where it is used. arch/x86/Kconfig | 4 + arch/x86/include/asm/pci_x86.h | 34 +--- arch/x86/pci/Makefile | 5 +- arch/x86/pci/acpi.c | 3 +- arch/x86/pci/mmconfig-shared.c | 346 +++++++++++---------------------------- arch/x86/pci/mmconfig_32.c | 47 ++---- arch/x86/pci/mmconfig_64.c | 153 ------------------ arch/x86/pci/numachip.c | 29 +--- drivers/acpi/Makefile | 1 + drivers/acpi/mcfg.c | 121 ++++++++++++++ drivers/pci/Kconfig | 10 ++ drivers/pci/Makefile | 5 + drivers/pci/ecam.c | 358 +++++++++++++++++++++++++++++++++++++++++ drivers/xen/pci.c | 7 +- include/linux/ecam.h | 56 +++++++ 15 files changed, 679 insertions(+), 500 deletions(-) delete mode 100644 arch/x86/pci/mmconfig_64.c create mode 100644 drivers/acpi/mcfg.c create mode 100644 drivers/pci/ecam.c create mode 100644 include/linux/ecam.h -- 1.9.1

9 years, 5 months

[PATCHv2 0/2] Add SPCR/DBG2 tables for kernel testing/debug

by Graeme Gregory

These patches add the DBG2/SPCR tables for FVP/Juno for kernel testing. They allow a kernel to find a serial console without console= line. They have been tested using the Redhat patches for SPCR support which are work in progress! Thanks Changes since v1 Ryan pointed out I had used RTSM in the JUNO tables - fixed.

9 years, 5 months

leg-kernel tag leg-20150415.0 released

by Graeme Gregory

The leg-kernel release has been made and tagged as leg-20150415.0 This is based on mainline kernel v4.0 Repository : http://git.linaro.org/leg/acpi/leg-kernel.git Direct Link: https://git.linaro.org/leg/acpi/leg-kernel.git/commit/afdd440a8c69eea7f1365… Notes :- 1) Much improved Seattle support thanks to patches from Redhat. 2) This release incorporates the SBSA UART support for pl011 driver from Andre Przywara. This means that your console will become ttyAMA0 (console=ttyAMA0) on Juno/FVP. It also means to run FVP model you need these options :- -C bp.pl011_uart0.untimed_fifos=0 -C bp.pl011_uart0.revision="r1p5" 3) First release of leg-kernel where all preperation was done on a Seattle running this release of leg-kernel.

9 years, 5 months

leg-kernel tag leg-20150414.0 released

by Graeme Gregory

The leg-kernel release has been made and tagged as leg-20150414.0 This is based on mainline kernel v4.0 Repository : http://git.linaro.org/leg/acpi/leg-kernel.git Direct Link: https://git.linaro.org/leg/acpi/leg-kernel.git/commit/afdd440a8c69eea7f1365… Notes :- 1) This release restores support for AMD Seattle. 2) This release incorporates the SBSA UART support for pl011 driver from Andre Przywara. This means that your console will become ttyAMA0 (console=ttyAMA0) on Juno/FVP. It also means to run FVP model you need these options :- -C bp.pl011_uart0.untimed_fifos=0 -C bp.pl011_uart0.revision="r1p5"

9 years, 5 months

LINA, Problems with item delivery, n.000253016

by FedEx International Ground

Dear Lina, Courier was unable to deliver the parcel to you. Please, open email attachment to print shipment label. Thanks and best regards, Brad Ritchie, FedEx Operation Manager.

9 years, 5 months

LINA, Notice to Appear in Court

by District Court

Dear Lina, You have to appear in the Court on the April 15. Please, prepare all the documents relating to the case and bring them to Court on the specified date. Note: The case will be heard by the judge in your absence if you do not come. The Court Notice is attached to this email. Sincerely, Donald Galloway, District Clerk.

9 years, 5 months

[RFC PATCH] ACPI / scan: Introduce _CCA parsing logic and setting up device coherency

by Suravee Suthikulpanit

ACPI v5.1 introduced _CCA object for specifying cache coherency attribute for devices. This patch implements a logic, which traverses device namespace to parse the coherency information, and calling the corresponded arch_setup_dma_ops(). It checks the _CCA during ACPI scan, and setup coherency during acpi_device creation. Then, this is propagted to the platform_device when it is created at later time. CC: Mark Salter <msalter(a)redhat.com> CC: Hanjun Guo <hanjun.guo(a)linaro.org> CC: Al Stone <al.stone(a)linaro.org> Signed-off-by: Suravee Suthikulpanit <Suravee.Suthikulpanit(a)amd.com> --- NOTE: The original patch has been submitted by Mark Salter, and discussed here: * http://comments.gmane.org/gmane.linux.acpi.devel/70424 One of the reveiw comment was dissusing whether we need the do/while loop for travesing parents of the device. AFAIK, there are no APIs that would do upsearch from a particular node. The acpi_get_handle() is the closest one, but it is using ACPI_NS_NO_UPSEARCH. This has been rebased and tested with: * http://git.linaro.org/leg/acpi/acpi.git acpi-5.1-v11 * [V8 PATCH 0/3] Introduce ACPI support for ahci_platform driver (https://lkml.org/lkml/2015/3/30/729) drivers/acpi/acpi_platform.c | 5 +++- drivers/acpi/scan.c | 56 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 60 insertions(+), 1 deletion(-) diff --git a/drivers/acpi/acpi_platform.c b/drivers/acpi/acpi_platform.c index 1284138..47e37a8 100644 --- a/drivers/acpi/acpi_platform.c +++ b/drivers/acpi/acpi_platform.c @@ -108,9 +108,12 @@ struct platform_device *acpi_create_platform_device(struct acpi_device *adev) if (IS_ERR(pdev)) dev_err(&adev->dev, "platform device creation failed: %ld\n", PTR_ERR(pdev)); - else + else { + arch_setup_dma_ops(&pdev->dev, 0, 0, NULL, + is_device_dma_coherent(&adev->dev)); dev_dbg(&adev->dev, "created platform device %s\n", dev_name(&pdev->dev)); + } kfree(resources); return pdev; diff --git a/drivers/acpi/scan.c b/drivers/acpi/scan.c index 230ec983..4d81c55 100644 --- a/drivers/acpi/scan.c +++ b/drivers/acpi/scan.c @@ -11,6 +11,7 @@ #include <linux/kthread.h> #include <linux/dmi.h> #include <linux/nls.h> +#include <linux/dma-mapping.h> #include <asm/pgtable.h> @@ -57,6 +58,9 @@ struct acpi_device_bus_id{ struct list_head node; }; +static int acpi_bus_type_and_status(acpi_handle handle, int *type, + unsigned long long *sta); + void acpi_scan_lock_acquire(void) { mutex_lock(&acpi_scan_lock); @@ -1327,6 +1331,51 @@ void acpi_bus_put_acpi_device(struct acpi_device *adev) put_device(&adev->dev); } +/** + * acpi_check_and_set_coherency - check and set cache coherency of a device + * @device: ACPI device + * + * Search a device and its parents for a _CCA method and calculate + * the effective coherency property of the device. If found, set up + * appropriate dma_ops for the device. + * + * Note From ACPIv5.1 spec: + * If used _CCA must be included under all bus-master-capable + * devices defined as children of \_SB. The value of _CCA is inherited + * by all descendants of these devices, so it need not be repeated for + * their children devices and will be ignored by OSPM if it is provided + * there. + */ +static int acpi_check_and_set_coherency(struct acpi_device *device) +{ + acpi_status status; + unsigned long long eff_cca = ~0ULL; + acpi_handle tmp, handle = device->handle; + + /* Calculate effective _CCA from all parents of this device */ + do { + unsigned long cca; + + status = acpi_get_handle(handle, "_CCA", &tmp); + if (ACPI_SUCCESS(status)) { + status = acpi_evaluate_integer(tmp, "_CCA", NULL, &cca); + /* Other values besides 0 and 1 are reserved */ + if (ACPI_FAILURE(status) || (cca != 0 && cca != 1)) + return -EINVAL; + eff_cca = cca; + } + + status = acpi_get_parent(handle, &handle); + if (ACPI_FAILURE(status)) + break; + } while (ACPI_SUCCESS(status)); + + if (eff_cca != ~0ULL) + arch_setup_dma_ops(&device->dev, 0, 0, NULL, eff_cca); + + return 0; +} + int acpi_device_add(struct acpi_device *device, void (*release)(struct device *)) { @@ -1398,6 +1447,13 @@ int acpi_device_add(struct acpi_device *device, device->dev.parent = &device->parent->dev; device->dev.bus = &acpi_bus_type; device->dev.release = release; + + result = acpi_check_and_set_coherency(device); + if (result) { + dev_err(&device->dev, "Error getting device _CCA information\n"); + goto err; + } + result = device_add(&device->dev); if (result) { dev_err(&device->dev, "Error registering device\n"); -- 2.1.0

9 years, 5 months

leg-kernel tag leg-20150408.0 released

by Graeme Gregory

The leg-kernel release has been made and tagged as leg-20150408.0 This is based on mainline kernel v4.0-rc7 Repository : http://git.linaro.org/leg/acpi/leg-kernel.git Direct Link: https://git.linaro.org/leg/acpi/leg-kernel.git/commit/4a93b8470719866b46d92… Notes :- 1) This release restores support for AMD Seattle. 2) This release incorporates the SBSA UART support for pl011 driver from Andre Przywara. This means that your console will become ttyAMA0 (console=ttyAMA0) on Juno/FVP. It also means to run FVP model you need these options :- -C bp.pl011_uart0.untimed_fifos=0 -C bp.pl011_uart0.revision="r1p5"

9 years, 5 months

[PATCH v2] ArmPlatformPkg: fix gtdt.asl for ArmVExpressPkg

by fu.wei＠linaro.org

From: Fu Wei <fu.wei(a)linaro.org> Add Memory-mapped GT and SBSA Generic Watchdog timer info base on Foundation Model Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Fu Wei <fu.wei(a)linaro.org> --- .../AcpiTables/rtsm_ve-aemv8a/gtdt.asl | 67 +++++++++++++++++----- 1 file changed, 53 insertions(+), 14 deletions(-) diff --git a/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/gtdt.asl b/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/gtdt.asl index d304243..11d5f89 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/gtdt.asl +++ b/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/gtdt.asl @@ -36,16 +36,16 @@ */ [0004] Signature : "GTDT" -[0004] Table Length : 00000050 +[0004] Table Length : 000000D8 [0001] Revision : 02 [0001] Checksum : F1 [0006] Oem ID : "LINARO" [0008] Oem Table ID : "RTSMVEV8" -[0004] Oem Revision : 00000001 +[0004] Oem Revision : 00000002 [0004] Asl Compiler ID : "INTL" [0004] Asl Compiler Revision : 20110623 -[0008] Counter Block Address : 0000000000000000 +[0008] Counter Block Address : 000000002a430000 [0004] Reserved : 00000000 /* In RTSM model's dts file, the last cell of interrupts @@ -83,26 +83,35 @@ Always-on : 0 /* The 64-bit physical address at which the Counter Read block is located */ -[0008] CntReadBase Physical address : 0000000000000000 +[0008] CntReadBase Physical address : 000000002a800000 -[0004] Platform Timer Count : 00000001 -[0004] Platform Timer Offset : 0000005C +[0004] Platform Timer Count : 00000002 +[0004] Platform Timer Offset : 00000060 /* Memory-mapped GT (Generic Timer) structures */ [0001] Subtable Type : 00 [0002] Length : 0064 [0001] Reserved : 000000 [0008] Block Address : 000000002a810000 -[0004] Timer Count : 00000001 -[0004] Timer Offset : 00000010 +[0004] Timer Count : 00000002 +[0004] Timer Offset : 00000014 -/* One frame is available */ +/* Two frames is available + * In FVP base model's dts file, the last cell of interrupts + * is 0x04, it means its trigger type is 4 = active high level-sensitive. + * + * So in ACPI the Trigger Mode is 0 - Level triggered, and + * Polarity is 0 - Active high as ACPI spec describled. + * + * Using direct mapping for hwirqs, it means that we using IRQ ID: + * (SPI offset + 32), not SPI offset used in FDT. + */ [0001] Frame Number : 00 [0003] Reserved : 000000 [0008] Base Address : 000000002a820000 -[0008] EL0 Base Address : FFFFFFFFFFFFFFFF -[0004] Timer Interrupt : 00000029 /* 25+16 */ -[0004] Timer Flags (decoded below) : 00000000 /* Active high level-sensitive */ +[0008] EL0 Base Address : 000000002a820000 +[0004] Timer Interrupt : 00000039 /* 25(SPI)+32 */ +[0004] Timer Flags (decoded below) : 00000000 Trigger Mode : 0 Polarity : 0 /* No virtual timer */ @@ -110,7 +119,37 @@ [0004] Virtual Timer Flags (decoded below) : 00000000 Trigger Mode : 0 Polarity : 0 -[0004] Common Flags (decoded below) : 00000000 - Secure : 0 +/* CNTPSIRQ Secure physical timer event.*/ +[0004] Common Flags (decoded below) : 00000001 + Secure : 1 + Always On : 0 + +[0001] Frame Number : 01 +[0003] Reserved : 000000 +[0008] Base Address : 000000002a830000 +[0008] EL0 Base Address : 000000002a830000 +[0004] Timer Interrupt : 0000003A /* 26(SPI)+32 */ +[0004] Timer Flags (decoded below) : 00000000 + Trigger Mode : 0 + Polarity : 0 +/* No virtual timer */ +[0004] Virtual Timer Interrupt : 00000000 +[0004] Virtual Timer Flags (decoded below) : 00000000 + Trigger Mode : 0 + Polarity : 0 +/* CNTPSIRQ1 Secure physical timer event.*/ +[0004] Common Flags (decoded below) : 00000001 + Secure : 1 Always On : 0 +/* One EL2 SBSA Generic Watchdog timer is available */ +[0001] Subtable Type : 01 [SBSA Generic Watchdog] +[0001] Length : 1C +[0002] Reserved : 0000 +[0008] Refresh Frame Address : 000000002a450000 +[0008] Control Frame Address : 000000002a440000 +[0004] Timer Interrupt : 0000003B /* 27(SPI)+32 */ +[0004] Timer Flags (decoded below) : 00000000 + Trigger Mode : 0 + Polarity : 0 + Secure : 0 -- 1.8.3.1

9 years, 5 months

[PATCH] ArmPlatformPkg: fix gtdt.asl for ArmVExpressPkg

by fu.wei＠linaro.org

From: Fu Wei <fu.wei(a)linaro.org> Add Memory-mapped GT and SBSA Generic Watchdog timer info base on Foundation Model Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Fu Wei <fu.wei(a)linaro.org> --- .../AcpiTables/rtsm_ve-aemv8a/gtdt.asl | 54 +++++++++++++++++----- 1 file changed, 42 insertions(+), 12 deletions(-) diff --git a/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/gtdt.asl b/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/gtdt.asl index d304243..8adf7b6 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/gtdt.asl +++ b/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/gtdt.asl @@ -36,16 +36,16 @@ */ [0004] Signature : "GTDT" -[0004] Table Length : 00000050 +[0004] Table Length : 000000D8 [0001] Revision : 02 [0001] Checksum : F1 [0006] Oem ID : "LINARO" [0008] Oem Table ID : "RTSMVEV8" -[0004] Oem Revision : 00000001 +[0004] Oem Revision : 00000002 [0004] Asl Compiler ID : "INTL" [0004] Asl Compiler Revision : 20110623 -[0008] Counter Block Address : 0000000000000000 +[0008] Counter Block Address : 000000002a430000 [0004] Reserved : 00000000 /* In RTSM model's dts file, the last cell of interrupts @@ -83,34 +83,64 @@ Always-on : 0 /* The 64-bit physical address at which the Counter Read block is located */ -[0008] CntReadBase Physical address : 0000000000000000 +[0008] CntReadBase Physical address : 000000002a800000 -[0004] Platform Timer Count : 00000001 -[0004] Platform Timer Offset : 0000005C +[0004] Platform Timer Count : 00000002 +[0004] Platform Timer Offset : 00000060 /* Memory-mapped GT (Generic Timer) structures */ [0001] Subtable Type : 00 [0002] Length : 0064 [0001] Reserved : 000000 [0008] Block Address : 000000002a810000 -[0004] Timer Count : 00000001 -[0004] Timer Offset : 00000010 +[0004] Timer Count : 00000002 +[0004] Timer Offset : 00000014 -/* One frame is available */ +/* two frames is available */ [0001] Frame Number : 00 [0003] Reserved : 000000 [0008] Base Address : 000000002a820000 -[0008] EL0 Base Address : FFFFFFFFFFFFFFFF -[0004] Timer Interrupt : 00000029 /* 25+16 */ +[0008] EL0 Base Address : 000000002a820000 +[0004] Timer Interrupt : 00000039 /* 25+32 */ [0004] Timer Flags (decoded below) : 00000000 /* Active high level-sensitive */ + Trigger Mode : 1 + Polarity : 0 +/* No virtual timer */ +[0004] Virtual Timer Interrupt : 00000000 +[0004] Virtual Timer Flags (decoded below) : 00000000 Trigger Mode : 0 Polarity : 0 + +[0004] Common Flags (decoded below) : 00000000 + Secure : 1 + Always On : 0 + +[0001] Frame Number : 01 +[0003] Reserved : 000000 +[0008] Base Address : 000000002a830000 +[0008] EL0 Base Address : 000000002a830000 +[0004] Timer Interrupt : 0000003A /* 26+32 */ +[0004] Timer Flags (decoded below) : 00000000 /* Active high level-sensitive */ + Trigger Mode : 1 + Polarity : 0 /* No virtual timer */ [0004] Virtual Timer Interrupt : 00000000 [0004] Virtual Timer Flags (decoded below) : 00000000 Trigger Mode : 0 Polarity : 0 + [0004] Common Flags (decoded below) : 00000000 - Secure : 0 + Secure : 1 Always On : 0 +/* one EL2 SBSA Generic Watchdog timer is available */ +[0001] Subtable Type : 01 [SBSA Generic Watchdog] +[0001] Length : 1C +[0002] Reserved : 0000 +[0008] Refresh Frame Address : 000000002a450000 +[0008] Control Frame Address : 000000002a440000 +[0004] Timer Interrupt : 0000003B /* 27+32 */ +[0004] Timer Flags (decoded below) : 00000001 + Trigger Mode : 1 + Polarity : 0 + Secure : 0 -- 1.8.3.1

9 years, 6 months

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