Hi Suravee, Ah , thanks for reviewing my code, good to see you here.
yes, that is countdown reg, but according to the SBSA 2.3, it is not RO.
the word below is from SBSA 2.3 without any modification: --------------------------- WOR Watchdog offset register. A Read/Write register containing the unsigned 32 bit watchdog countdown timer value. ---------------------------
I just checked the ARM website , ARM-DEN-0029 Version 2.3 is the latest one. :-) ,
On 8 May 2015 at 05:42, Suravee Suthikulanit suravee.suthikulpanit@amd.com wrote:
On 5/4/2015 7:04 AM, fu.wei@linaro.org wrote:
+static int sbsa_gwdt_set_pretimeout(struct watchdog_device *wdd,
unsigned int pretimeout)+{
struct sbsa_gwdt *gwdt = to_sbsa_gwdt(wdd);u32 wor;if (watchdog_pretimeout_invalid(gwdt, pretimeout)) {pr_err("sbsa_gwdt: pretimeout %d is out ofrange(0~%d),skip\n",
pretimeout, gwdt->max_pretimeout);return -EINVAL;}gwdt->pretimeout = pretimeout;sbsa_gwdt_set_timeout_limits(gwdt);/* refresh the WOR, that will cause an explicit watchdog refresh*/
wor = pretimeout * sbsa_gwdt_rate;sbsa_gwdt_cf_write(SBSA_GWDT_WOR, wor, wdd);return 0;+}
Fu Wei,
IIUC, isn't the SBSA_GWDT_WOR (offset 8) is the watchdog countdown timer value which is read only?
Suravee